2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/platform_device.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/delay.h>
49 #include <linux/slab.h>
50 #include <linux/usb.h>
52 #include <linux/usb/hcd.h>
53 #include <linux/usb/ch11.h>
58 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
61 * =========================================================================
62 * Host Core Layer Functions
63 * =========================================================================
67 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
68 * used in both device and host modes
70 * @hsotg: Programming view of the DWC_otg controller
72 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
76 /* Clear any pending OTG Interrupts */
77 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
79 /* Clear any pending interrupts */
80 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
82 /* Enable the interrupts in the GINTMSK */
83 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
85 if (!hsotg->params.host_dma)
86 intmsk |= GINTSTS_RXFLVL;
87 if (!hsotg->params.external_id_pin_ctl)
88 intmsk |= GINTSTS_CONIDSTSCHNG;
90 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
93 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
97 * Initializes the FSLSPClkSel field of the HCFG register depending on the
100 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
104 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
105 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
106 hsotg->params.ulpi_fs_ls) ||
107 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
109 val = HCFG_FSLSPCLKSEL_48_MHZ;
111 /* High speed PHY running at full speed or high speed */
112 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
115 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
116 hcfg = dwc2_readl(hsotg->regs + HCFG);
117 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
118 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
119 dwc2_writel(hcfg, hsotg->regs + HCFG);
122 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
124 u32 usbcfg, ggpio, i2cctl;
128 * core_init() is now called on every switch so only call the
129 * following for the first time through
132 dev_dbg(hsotg->dev, "FS PHY selected\n");
134 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
135 if (!(usbcfg & GUSBCFG_PHYSEL)) {
136 usbcfg |= GUSBCFG_PHYSEL;
137 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
139 /* Reset after a PHY select */
140 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
144 "%s: Reset failed, aborting", __func__);
149 if (hsotg->params.activate_stm_fs_transceiver) {
150 ggpio = dwc2_readl(hsotg->regs + GGPIO);
151 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
152 dev_dbg(hsotg->dev, "Activating transceiver\n");
154 * STM32F4x9 uses the GGPIO register as general
155 * core configuration register.
157 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
158 dwc2_writel(ggpio, hsotg->regs + GGPIO);
164 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
165 * do this on HNP Dev/Host mode switches (done in dev_init and
168 if (dwc2_is_host_mode(hsotg))
169 dwc2_init_fs_ls_pclk_sel(hsotg);
171 if (hsotg->params.i2c_enable) {
172 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
174 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
175 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
176 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
177 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
179 /* Program GI2CCTL.I2CEn */
180 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
181 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
182 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
183 i2cctl &= ~GI2CCTL_I2CEN;
184 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
185 i2cctl |= GI2CCTL_I2CEN;
186 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
192 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
194 u32 usbcfg, usbcfg_old;
200 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
204 * HS PHY parameters. These parameters are preserved during soft reset
205 * so only program the first time. Do a soft reset immediately after
208 switch (hsotg->params.phy_type) {
209 case DWC2_PHY_TYPE_PARAM_ULPI:
211 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
212 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
213 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
214 if (hsotg->params.phy_ulpi_ddr)
215 usbcfg |= GUSBCFG_DDRSEL;
217 case DWC2_PHY_TYPE_PARAM_UTMI:
218 /* UTMI+ interface */
219 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
220 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
221 if (hsotg->params.phy_utmi_width == 16)
222 usbcfg |= GUSBCFG_PHYIF16;
225 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
229 if (usbcfg != usbcfg_old) {
230 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
232 /* Reset after setting the PHY parameters */
233 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
236 "%s: Reset failed, aborting", __func__);
244 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
249 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
250 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
251 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
252 /* If FS/LS mode with FS/LS PHY */
253 retval = dwc2_fs_phy_init(hsotg, select_phy);
258 retval = dwc2_hs_phy_init(hsotg, select_phy);
263 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
264 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
265 hsotg->params.ulpi_fs_ls) {
266 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
267 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
268 usbcfg |= GUSBCFG_ULPI_FS_LS;
269 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
270 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
272 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
273 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
274 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
275 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
281 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
283 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
285 switch (hsotg->hw_params.arch) {
286 case GHWCFG2_EXT_DMA_ARCH:
287 dev_err(hsotg->dev, "External DMA Mode not supported\n");
290 case GHWCFG2_INT_DMA_ARCH:
291 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
292 if (hsotg->params.ahbcfg != -1) {
293 ahbcfg &= GAHBCFG_CTRL_MASK;
294 ahbcfg |= hsotg->params.ahbcfg &
299 case GHWCFG2_SLAVE_ONLY_ARCH:
301 dev_dbg(hsotg->dev, "Slave Only Mode\n");
305 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
306 hsotg->params.host_dma,
307 hsotg->params.dma_desc_enable);
309 if (hsotg->params.host_dma) {
310 if (hsotg->params.dma_desc_enable)
311 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
313 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
315 dev_dbg(hsotg->dev, "Using Slave mode\n");
316 hsotg->params.dma_desc_enable = false;
319 if (hsotg->params.host_dma)
320 ahbcfg |= GAHBCFG_DMA_EN;
322 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
327 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
331 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
332 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
334 switch (hsotg->hw_params.op_mode) {
335 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
336 if (hsotg->params.otg_cap ==
337 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_HNPCAP;
339 if (hsotg->params.otg_cap !=
340 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
341 usbcfg |= GUSBCFG_SRPCAP;
344 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
345 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
346 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
347 if (hsotg->params.otg_cap !=
348 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
349 usbcfg |= GUSBCFG_SRPCAP;
352 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
353 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
354 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
359 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
363 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
365 * @hsotg: Programming view of DWC_otg controller
367 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
371 dev_dbg(hsotg->dev, "%s()\n", __func__);
373 /* Disable all interrupts */
374 dwc2_writel(0, hsotg->regs + GINTMSK);
375 dwc2_writel(0, hsotg->regs + HAINTMSK);
377 /* Enable the common interrupts */
378 dwc2_enable_common_interrupts(hsotg);
380 /* Enable host mode interrupts without disturbing common interrupts */
381 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
382 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
383 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
387 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
389 * @hsotg: Programming view of DWC_otg controller
391 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
393 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
395 /* Disable host mode interrupts without disturbing common interrupts */
396 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
397 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
398 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
402 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
403 * For system that have a total fifo depth that is smaller than the default
406 * @hsotg: Programming view of DWC_otg controller
408 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
410 struct dwc2_core_params *params = &hsotg->params;
411 struct dwc2_hw_params *hw = &hsotg->hw_params;
412 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
414 total_fifo_size = hw->total_fifo_size;
415 rxfsiz = params->host_rx_fifo_size;
416 nptxfsiz = params->host_nperio_tx_fifo_size;
417 ptxfsiz = params->host_perio_tx_fifo_size;
420 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
421 * allocation with support for high bandwidth endpoints. Synopsys
422 * defines MPS(Max Packet size) for a periodic EP=1024, and for
423 * non-periodic as 512.
425 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
427 * For Buffer DMA mode/Scatter Gather DMA mode
428 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
429 * with n = number of host channel.
430 * 2 * ((1024/4) + 2) = 516
432 rxfsiz = 516 + hw->host_channels;
435 * min non-periodic tx fifo depth
436 * 2 * (largest non-periodic USB packet used / 4)
442 * min periodic tx fifo depth
443 * (largest packet size*MC)/4
448 params->host_rx_fifo_size = rxfsiz;
449 params->host_nperio_tx_fifo_size = nptxfsiz;
450 params->host_perio_tx_fifo_size = ptxfsiz;
454 * If the summation of RX, NPTX and PTX fifo sizes is still
455 * bigger than the total_fifo_size, then we have a problem.
457 * We won't be able to allocate as many endpoints. Right now,
458 * we're just printing an error message, but ideally this FIFO
459 * allocation algorithm would be improved in the future.
461 * FIXME improve this FIFO allocation algorithm.
463 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
464 dev_err(hsotg->dev, "invalid fifo sizes\n");
467 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
469 struct dwc2_core_params *params = &hsotg->params;
470 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
472 if (!params->enable_dynamic_fifo)
475 dwc2_calculate_dynamic_fifo(hsotg);
478 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
479 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
480 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
481 grxfsiz |= params->host_rx_fifo_size <<
482 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
483 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
484 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
485 dwc2_readl(hsotg->regs + GRXFSIZ));
487 /* Non-periodic Tx FIFO */
488 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
489 dwc2_readl(hsotg->regs + GNPTXFSIZ));
490 nptxfsiz = params->host_nperio_tx_fifo_size <<
491 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
492 nptxfsiz |= params->host_rx_fifo_size <<
493 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
494 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
495 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
496 dwc2_readl(hsotg->regs + GNPTXFSIZ));
498 /* Periodic Tx FIFO */
499 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
500 dwc2_readl(hsotg->regs + HPTXFSIZ));
501 hptxfsiz = params->host_perio_tx_fifo_size <<
502 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
503 hptxfsiz |= (params->host_rx_fifo_size +
504 params->host_nperio_tx_fifo_size) <<
505 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
506 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
507 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + HPTXFSIZ));
510 if (hsotg->params.en_multiple_tx_fifo &&
511 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
513 * This feature was implemented in 2.91a version
514 * Global DFIFOCFG calculation for Host mode -
515 * include RxFIFO, NPTXFIFO and HPTXFIFO
517 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
518 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
519 dfifocfg |= (params->host_rx_fifo_size +
520 params->host_nperio_tx_fifo_size +
521 params->host_perio_tx_fifo_size) <<
522 GDFIFOCFG_EPINFOBASE_SHIFT &
523 GDFIFOCFG_EPINFOBASE_MASK;
524 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
529 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
530 * the HFIR register according to PHY type and speed
532 * @hsotg: Programming view of DWC_otg controller
534 * NOTE: The caller can modify the value of the HFIR register only after the
535 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
538 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
542 int clock = 60; /* default value */
544 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
545 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
547 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
548 !(usbcfg & GUSBCFG_PHYIF16))
550 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
551 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
553 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
554 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
556 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
557 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
559 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
560 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
562 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
563 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
565 if ((usbcfg & GUSBCFG_PHYSEL) &&
566 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
569 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
570 /* High speed case */
571 return 125 * clock - 1;
574 return 1000 * clock - 1;
578 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
581 * @core_if: Programming view of DWC_otg controller
582 * @dest: Destination buffer for the packet
583 * @bytes: Number of bytes to copy to the destination
585 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
587 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
588 u32 *data_buf = (u32 *)dest;
589 int word_count = (bytes + 3) / 4;
593 * Todo: Account for the case where dest is not dword aligned. This
594 * requires reading data from the FIFO into a u32 temp buffer, then
595 * moving it into the data buffer.
598 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
600 for (i = 0; i < word_count; i++, data_buf++)
601 *data_buf = dwc2_readl(fifo);
605 * dwc2_dump_channel_info() - Prints the state of a host channel
607 * @hsotg: Programming view of DWC_otg controller
608 * @chan: Pointer to the channel to dump
610 * Must be called with interrupt disabled and spinlock held
612 * NOTE: This function will be removed once the peripheral controller code
613 * is integrated and the driver is stable
615 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
616 struct dwc2_host_chan *chan)
619 int num_channels = hsotg->params.host_channels;
630 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
631 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
632 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
633 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
635 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
636 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
638 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
640 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
641 chan->dev_addr, chan->ep_num, chan->ep_is_in);
642 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
643 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
644 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
645 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
646 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
647 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
648 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
649 (unsigned long)chan->xfer_dma);
650 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
651 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
652 dev_dbg(hsotg->dev, " NP inactive sched:\n");
653 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
655 dev_dbg(hsotg->dev, " %p\n", qh);
656 dev_dbg(hsotg->dev, " NP active sched:\n");
657 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
659 dev_dbg(hsotg->dev, " %p\n", qh);
660 dev_dbg(hsotg->dev, " Channels:\n");
661 for (i = 0; i < num_channels; i++) {
662 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
664 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
666 #endif /* VERBOSE_DEBUG */
669 static int _dwc2_hcd_start(struct usb_hcd *hcd);
671 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
673 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
675 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
676 _dwc2_hcd_start(hcd);
679 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
681 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
683 hcd->self.is_b_host = 0;
686 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
687 int *hub_addr, int *hub_port)
689 struct urb *urb = context;
692 *hub_addr = urb->dev->tt->hub->devnum;
695 *hub_port = urb->dev->ttport;
699 * =========================================================================
700 * Low Level Host Channel Access Functions
701 * =========================================================================
704 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
705 struct dwc2_host_chan *chan)
707 u32 hcintmsk = HCINTMSK_CHHLTD;
709 switch (chan->ep_type) {
710 case USB_ENDPOINT_XFER_CONTROL:
711 case USB_ENDPOINT_XFER_BULK:
712 dev_vdbg(hsotg->dev, "control/bulk\n");
713 hcintmsk |= HCINTMSK_XFERCOMPL;
714 hcintmsk |= HCINTMSK_STALL;
715 hcintmsk |= HCINTMSK_XACTERR;
716 hcintmsk |= HCINTMSK_DATATGLERR;
717 if (chan->ep_is_in) {
718 hcintmsk |= HCINTMSK_BBLERR;
720 hcintmsk |= HCINTMSK_NAK;
721 hcintmsk |= HCINTMSK_NYET;
723 hcintmsk |= HCINTMSK_ACK;
726 if (chan->do_split) {
727 hcintmsk |= HCINTMSK_NAK;
728 if (chan->complete_split)
729 hcintmsk |= HCINTMSK_NYET;
731 hcintmsk |= HCINTMSK_ACK;
734 if (chan->error_state)
735 hcintmsk |= HCINTMSK_ACK;
738 case USB_ENDPOINT_XFER_INT:
740 dev_vdbg(hsotg->dev, "intr\n");
741 hcintmsk |= HCINTMSK_XFERCOMPL;
742 hcintmsk |= HCINTMSK_NAK;
743 hcintmsk |= HCINTMSK_STALL;
744 hcintmsk |= HCINTMSK_XACTERR;
745 hcintmsk |= HCINTMSK_DATATGLERR;
746 hcintmsk |= HCINTMSK_FRMOVRUN;
749 hcintmsk |= HCINTMSK_BBLERR;
750 if (chan->error_state)
751 hcintmsk |= HCINTMSK_ACK;
752 if (chan->do_split) {
753 if (chan->complete_split)
754 hcintmsk |= HCINTMSK_NYET;
756 hcintmsk |= HCINTMSK_ACK;
760 case USB_ENDPOINT_XFER_ISOC:
762 dev_vdbg(hsotg->dev, "isoc\n");
763 hcintmsk |= HCINTMSK_XFERCOMPL;
764 hcintmsk |= HCINTMSK_FRMOVRUN;
765 hcintmsk |= HCINTMSK_ACK;
767 if (chan->ep_is_in) {
768 hcintmsk |= HCINTMSK_XACTERR;
769 hcintmsk |= HCINTMSK_BBLERR;
773 dev_err(hsotg->dev, "## Unknown EP type ##\n");
777 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
779 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
782 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
783 struct dwc2_host_chan *chan)
785 u32 hcintmsk = HCINTMSK_CHHLTD;
788 * For Descriptor DMA mode core halts the channel on AHB error.
789 * Interrupt is not required.
791 if (!hsotg->params.dma_desc_enable) {
793 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
794 hcintmsk |= HCINTMSK_AHBERR;
797 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
798 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
799 hcintmsk |= HCINTMSK_XFERCOMPL;
802 if (chan->error_state && !chan->do_split &&
803 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
805 dev_vdbg(hsotg->dev, "setting ACK\n");
806 hcintmsk |= HCINTMSK_ACK;
807 if (chan->ep_is_in) {
808 hcintmsk |= HCINTMSK_DATATGLERR;
809 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
810 hcintmsk |= HCINTMSK_NAK;
814 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
816 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
819 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
820 struct dwc2_host_chan *chan)
824 if (hsotg->params.host_dma) {
826 dev_vdbg(hsotg->dev, "DMA enabled\n");
827 dwc2_hc_enable_dma_ints(hsotg, chan);
830 dev_vdbg(hsotg->dev, "DMA disabled\n");
831 dwc2_hc_enable_slave_ints(hsotg, chan);
834 /* Enable the top level host channel interrupt */
835 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
836 intmsk |= 1 << chan->hc_num;
837 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
839 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
841 /* Make sure host channel interrupts are enabled */
842 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
843 intmsk |= GINTSTS_HCHINT;
844 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
846 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
850 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
851 * a specific endpoint
853 * @hsotg: Programming view of DWC_otg controller
854 * @chan: Information needed to initialize the host channel
856 * The HCCHARn register is set up with the characteristics specified in chan.
857 * Host channel interrupts that may need to be serviced while this transfer is
858 * in progress are enabled.
860 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
862 u8 hc_num = chan->hc_num;
868 dev_vdbg(hsotg->dev, "%s()\n", __func__);
870 /* Clear old interrupt conditions for this host channel */
871 hcintmsk = 0xffffffff;
872 hcintmsk &= ~HCINTMSK_RESERVED14_31;
873 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
875 /* Enable channel interrupts required for this transfer */
876 dwc2_hc_enable_ints(hsotg, chan);
879 * Program the HCCHARn register with the endpoint characteristics for
880 * the current transfer
882 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
883 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
885 hcchar |= HCCHAR_EPDIR;
886 if (chan->speed == USB_SPEED_LOW)
887 hcchar |= HCCHAR_LSPDDEV;
888 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
889 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
890 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
892 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
895 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
897 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
899 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
901 dev_vdbg(hsotg->dev, " Is In: %d\n",
903 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
904 chan->speed == USB_SPEED_LOW);
905 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
907 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
911 /* Program the HCSPLT register for SPLITs */
912 if (chan->do_split) {
915 "Programming HC %d with split --> %s\n",
917 chan->complete_split ? "CSPLIT" : "SSPLIT");
918 if (chan->complete_split)
919 hcsplt |= HCSPLT_COMPSPLT;
920 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
922 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
924 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
927 dev_vdbg(hsotg->dev, " comp split %d\n",
928 chan->complete_split);
929 dev_vdbg(hsotg->dev, " xact pos %d\n",
931 dev_vdbg(hsotg->dev, " hub addr %d\n",
933 dev_vdbg(hsotg->dev, " hub port %d\n",
935 dev_vdbg(hsotg->dev, " is_in %d\n",
937 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
939 dev_vdbg(hsotg->dev, " xferlen %d\n",
944 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
948 * dwc2_hc_halt() - Attempts to halt a host channel
950 * @hsotg: Controller register interface
951 * @chan: Host channel to halt
952 * @halt_status: Reason for halting the channel
954 * This function should only be called in Slave mode or to abort a transfer in
955 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
956 * controller halts the channel when the transfer is complete or a condition
957 * occurs that requires application intervention.
959 * In slave mode, checks for a free request queue entry, then sets the Channel
960 * Enable and Channel Disable bits of the Host Channel Characteristics
961 * register of the specified channel to intiate the halt. If there is no free
962 * request queue entry, sets only the Channel Disable bit of the HCCHARn
963 * register to flush requests for this channel. In the latter case, sets a
964 * flag to indicate that the host channel needs to be halted when a request
965 * queue slot is open.
967 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
968 * HCCHARn register. The controller ensures there is space in the request
969 * queue before submitting the halt request.
971 * Some time may elapse before the core flushes any posted requests for this
972 * host channel and halts. The Channel Halted interrupt handler completes the
973 * deactivation of the host channel.
975 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
976 enum dwc2_halt_status halt_status)
978 u32 nptxsts, hptxsts, hcchar;
981 dev_vdbg(hsotg->dev, "%s()\n", __func__);
984 * In buffer DMA or external DMA mode channel can't be halted
985 * for non-split periodic channels. At the end of the next
986 * uframe/frame (in the worst case), the core generates a channel
987 * halted and disables the channel automatically.
989 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
990 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
991 if (!chan->do_split &&
992 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
993 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
994 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1000 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1001 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1003 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1004 halt_status == DWC2_HC_XFER_AHB_ERR) {
1006 * Disable all channel interrupts except Ch Halted. The QTD
1007 * and QH state associated with this transfer has been cleared
1008 * (in the case of URB_DEQUEUE), so the channel needs to be
1009 * shut down carefully to prevent crashes.
1011 u32 hcintmsk = HCINTMSK_CHHLTD;
1013 dev_vdbg(hsotg->dev, "dequeue/error\n");
1014 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1017 * Make sure no other interrupts besides halt are currently
1018 * pending. Handling another interrupt could cause a crash due
1019 * to the QTD and QH state.
1021 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1024 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1025 * even if the channel was already halted for some other
1028 chan->halt_status = halt_status;
1030 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1031 if (!(hcchar & HCCHAR_CHENA)) {
1033 * The channel is either already halted or it hasn't
1034 * started yet. In DMA mode, the transfer may halt if
1035 * it finishes normally or a condition occurs that
1036 * requires driver intervention. Don't want to halt
1037 * the channel again. In either Slave or DMA mode,
1038 * it's possible that the transfer has been assigned
1039 * to a channel, but not started yet when an URB is
1040 * dequeued. Don't want to halt a channel that hasn't
1046 if (chan->halt_pending) {
1048 * A halt has already been issued for this channel. This might
1049 * happen when a transfer is aborted by a higher level in
1052 dev_vdbg(hsotg->dev,
1053 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1054 __func__, chan->hc_num);
1058 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1060 /* No need to set the bit in DDMA for disabling the channel */
1061 /* TODO check it everywhere channel is disabled */
1062 if (!hsotg->params.dma_desc_enable) {
1064 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1065 hcchar |= HCCHAR_CHENA;
1068 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1070 hcchar |= HCCHAR_CHDIS;
1072 if (!hsotg->params.host_dma) {
1074 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1075 hcchar |= HCCHAR_CHENA;
1077 /* Check for space in the request queue to issue the halt */
1078 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1079 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1080 dev_vdbg(hsotg->dev, "control/bulk\n");
1081 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1082 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1083 dev_vdbg(hsotg->dev, "Disabling channel\n");
1084 hcchar &= ~HCCHAR_CHENA;
1088 dev_vdbg(hsotg->dev, "isoc/intr\n");
1089 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1090 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1091 hsotg->queuing_high_bandwidth) {
1093 dev_vdbg(hsotg->dev, "Disabling channel\n");
1094 hcchar &= ~HCCHAR_CHENA;
1099 dev_vdbg(hsotg->dev, "DMA enabled\n");
1102 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1103 chan->halt_status = halt_status;
1105 if (hcchar & HCCHAR_CHENA) {
1107 dev_vdbg(hsotg->dev, "Channel enabled\n");
1108 chan->halt_pending = 1;
1109 chan->halt_on_queue = 0;
1112 dev_vdbg(hsotg->dev, "Channel disabled\n");
1113 chan->halt_on_queue = 1;
1117 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1119 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1121 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1122 chan->halt_pending);
1123 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1124 chan->halt_on_queue);
1125 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1131 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1133 * @hsotg: Programming view of DWC_otg controller
1134 * @chan: Identifies the host channel to clean up
1136 * This function is normally called after a transfer is done and the host
1137 * channel is being released
1139 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1143 chan->xfer_started = 0;
1145 list_del_init(&chan->split_order_list_entry);
1148 * Clear channel interrupt enables and any unhandled channel interrupt
1151 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1152 hcintmsk = 0xffffffff;
1153 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1154 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1158 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1159 * which frame a periodic transfer should occur
1161 * @hsotg: Programming view of DWC_otg controller
1162 * @chan: Identifies the host channel to set up and its properties
1163 * @hcchar: Current value of the HCCHAR register for the specified host channel
1165 * This function has no effect on non-periodic transfers
1167 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1168 struct dwc2_host_chan *chan, u32 *hcchar)
1170 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1171 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1181 * Try to figure out if we're an even or odd frame. If we set
1182 * even and the current frame number is even the the transfer
1183 * will happen immediately. Similar if both are odd. If one is
1184 * even and the other is odd then the transfer will happen when
1185 * the frame number ticks.
1187 * There's a bit of a balancing act to get this right.
1188 * Sometimes we may want to send data in the current frame (AK
1189 * right away). We might want to do this if the frame number
1190 * _just_ ticked, but we might also want to do this in order
1191 * to continue a split transaction that happened late in a
1192 * microframe (so we didn't know to queue the next transfer
1193 * until the frame number had ticked). The problem is that we
1194 * need a lot of knowledge to know if there's actually still
1195 * time to send things or if it would be better to wait until
1198 * We can look at how much time is left in the current frame
1199 * and make a guess about whether we'll have time to transfer.
1203 /* Get speed host is running at */
1204 host_speed = (chan->speed != USB_SPEED_HIGH &&
1205 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1207 /* See how many bytes are in the periodic FIFO right now */
1208 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1209 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1210 bytes_in_fifo = sizeof(u32) *
1211 (hsotg->params.host_perio_tx_fifo_size -
1215 * Roughly estimate bus time for everything in the periodic
1216 * queue + our new transfer. This is "rough" because we're
1217 * using a function that makes takes into account IN/OUT
1218 * and INT/ISO and we're just slamming in one value for all
1219 * transfers. This should be an over-estimate and that should
1220 * be OK, but we can probably tighten it.
1222 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1223 chan->xfer_len + bytes_in_fifo);
1224 xfer_us = NS_TO_US(xfer_ns);
1226 /* See what frame number we'll be at by the time we finish */
1227 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1229 /* This is when we were scheduled to be on the wire */
1230 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1233 * If we'd finish _after_ the frame we're scheduled in then
1234 * it's hopeless. Just schedule right away and hope for the
1235 * best. Note that it _might_ be wise to call back into the
1236 * scheduler to pick a better frame, but this is better than
1239 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1240 dwc2_sch_vdbg(hsotg,
1241 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1242 chan->qh, wire_frame, frame_number,
1243 dwc2_frame_num_dec(frame_number,
1245 wire_frame = frame_number;
1248 * We picked a different frame number; communicate this
1249 * back to the scheduler so it doesn't try to schedule
1250 * another in the same frame.
1252 * Remember that next_active_frame is 1 before the wire
1255 chan->qh->next_active_frame =
1256 dwc2_frame_num_dec(frame_number, 1);
1260 *hcchar |= HCCHAR_ODDFRM;
1262 *hcchar &= ~HCCHAR_ODDFRM;
1266 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1268 /* Set up the initial PID for the transfer */
1269 if (chan->speed == USB_SPEED_HIGH) {
1270 if (chan->ep_is_in) {
1271 if (chan->multi_count == 1)
1272 chan->data_pid_start = DWC2_HC_PID_DATA0;
1273 else if (chan->multi_count == 2)
1274 chan->data_pid_start = DWC2_HC_PID_DATA1;
1276 chan->data_pid_start = DWC2_HC_PID_DATA2;
1278 if (chan->multi_count == 1)
1279 chan->data_pid_start = DWC2_HC_PID_DATA0;
1281 chan->data_pid_start = DWC2_HC_PID_MDATA;
1284 chan->data_pid_start = DWC2_HC_PID_DATA0;
1289 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1292 * @hsotg: Programming view of DWC_otg controller
1293 * @chan: Information needed to initialize the host channel
1295 * This function should only be called in Slave mode. For a channel associated
1296 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1297 * associated with a periodic EP, the periodic Tx FIFO is written.
1299 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1300 * the number of bytes written to the Tx FIFO.
1302 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1303 struct dwc2_host_chan *chan)
1306 u32 remaining_count;
1309 u32 __iomem *data_fifo;
1310 u32 *data_buf = (u32 *)chan->xfer_buf;
1313 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1315 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1317 remaining_count = chan->xfer_len - chan->xfer_count;
1318 if (remaining_count > chan->max_packet)
1319 byte_count = chan->max_packet;
1321 byte_count = remaining_count;
1323 dword_count = (byte_count + 3) / 4;
1325 if (((unsigned long)data_buf & 0x3) == 0) {
1326 /* xfer_buf is DWORD aligned */
1327 for (i = 0; i < dword_count; i++, data_buf++)
1328 dwc2_writel(*data_buf, data_fifo);
1330 /* xfer_buf is not DWORD aligned */
1331 for (i = 0; i < dword_count; i++, data_buf++) {
1332 u32 data = data_buf[0] | data_buf[1] << 8 |
1333 data_buf[2] << 16 | data_buf[3] << 24;
1334 dwc2_writel(data, data_fifo);
1338 chan->xfer_count += byte_count;
1339 chan->xfer_buf += byte_count;
1343 * dwc2_hc_do_ping() - Starts a PING transfer
1345 * @hsotg: Programming view of DWC_otg controller
1346 * @chan: Information needed to initialize the host channel
1348 * This function should only be called in Slave mode. The Do Ping bit is set in
1349 * the HCTSIZ register, then the channel is enabled.
1351 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1352 struct dwc2_host_chan *chan)
1358 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1361 hctsiz = TSIZ_DOPNG;
1362 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1363 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1365 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1366 hcchar |= HCCHAR_CHENA;
1367 hcchar &= ~HCCHAR_CHDIS;
1368 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1372 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1373 * channel and starts the transfer
1375 * @hsotg: Programming view of DWC_otg controller
1376 * @chan: Information needed to initialize the host channel. The xfer_len value
1377 * may be reduced to accommodate the max widths of the XferSize and
1378 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1379 * changed to reflect the final xfer_len value.
1381 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1382 * the caller must ensure that there is sufficient space in the request queue
1385 * For an OUT transfer in Slave mode, it loads a data packet into the
1386 * appropriate FIFO. If necessary, additional data packets are loaded in the
1389 * For an IN transfer in Slave mode, a data packet is requested. The data
1390 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1391 * additional data packets are requested in the Host ISR.
1393 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1394 * register along with a packet count of 1 and the channel is enabled. This
1395 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1396 * simply set to 0 since no data transfer occurs in this case.
1398 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1399 * all the information required to perform the subsequent data transfer. In
1400 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1401 * controller performs the entire PING protocol, then starts the data
1404 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1405 struct dwc2_host_chan *chan)
1407 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1408 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1415 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1417 if (chan->do_ping) {
1418 if (!hsotg->params.host_dma) {
1420 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1421 dwc2_hc_do_ping(hsotg, chan);
1422 chan->xfer_started = 1;
1427 dev_vdbg(hsotg->dev, "ping, DMA\n");
1429 hctsiz |= TSIZ_DOPNG;
1432 if (chan->do_split) {
1434 dev_vdbg(hsotg->dev, "split\n");
1437 if (chan->complete_split && !chan->ep_is_in)
1439 * For CSPLIT OUT Transfer, set the size to 0 so the
1440 * core doesn't expect any data written to the FIFO
1443 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1444 chan->xfer_len = chan->max_packet;
1445 else if (!chan->ep_is_in && chan->xfer_len > 188)
1446 chan->xfer_len = 188;
1448 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1451 /* For split set ec_mc for immediate retries */
1452 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1453 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1459 dev_vdbg(hsotg->dev, "no split\n");
1461 * Ensure that the transfer length and packet count will fit
1462 * in the widths allocated for them in the HCTSIZn register
1464 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1465 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1467 * Make sure the transfer size is no larger than one
1468 * (micro)frame's worth of data. (A check was done
1469 * when the periodic transfer was accepted to ensure
1470 * that a (micro)frame's worth of data can be
1471 * programmed into a channel.)
1473 u32 max_periodic_len =
1474 chan->multi_count * chan->max_packet;
1476 if (chan->xfer_len > max_periodic_len)
1477 chan->xfer_len = max_periodic_len;
1478 } else if (chan->xfer_len > max_hc_xfer_size) {
1480 * Make sure that xfer_len is a multiple of max packet
1484 max_hc_xfer_size - chan->max_packet + 1;
1487 if (chan->xfer_len > 0) {
1488 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1490 if (num_packets > max_hc_pkt_count) {
1491 num_packets = max_hc_pkt_count;
1492 chan->xfer_len = num_packets * chan->max_packet;
1493 } else if (chan->ep_is_in) {
1495 * Always program an integral # of max packets
1497 * Note: This assumes that the input buffer is
1498 * aligned and sized accordingly.
1500 chan->xfer_len = num_packets * chan->max_packet;
1503 /* Need 1 packet for transfer length of 0 */
1507 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1508 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1510 * Make sure that the multi_count field matches the
1511 * actual transfer length
1513 chan->multi_count = num_packets;
1515 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1516 dwc2_set_pid_isoc(chan);
1518 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1521 /* The ec_mc gets the multi_count for non-split */
1522 ec_mc = chan->multi_count;
1525 chan->start_pkt_count = num_packets;
1526 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1527 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1528 TSIZ_SC_MC_PID_MASK;
1529 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1531 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1532 hctsiz, chan->hc_num);
1534 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1536 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1537 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1538 TSIZ_XFERSIZE_SHIFT);
1539 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1540 (hctsiz & TSIZ_PKTCNT_MASK) >>
1542 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1543 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1544 TSIZ_SC_MC_PID_SHIFT);
1547 if (hsotg->params.host_dma) {
1548 dma_addr_t dma_addr;
1550 if (chan->align_buf) {
1552 dev_vdbg(hsotg->dev, "align_buf\n");
1553 dma_addr = chan->align_buf;
1555 dma_addr = chan->xfer_dma;
1557 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1560 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1561 (unsigned long)dma_addr, chan->hc_num);
1564 /* Start the split */
1565 if (chan->do_split) {
1566 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1568 hcsplt |= HCSPLT_SPLTENA;
1569 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1572 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1573 hcchar &= ~HCCHAR_MULTICNT_MASK;
1574 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1575 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1577 if (hcchar & HCCHAR_CHDIS)
1578 dev_warn(hsotg->dev,
1579 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1580 __func__, chan->hc_num, hcchar);
1582 /* Set host channel enable after all other setup is complete */
1583 hcchar |= HCCHAR_CHENA;
1584 hcchar &= ~HCCHAR_CHDIS;
1587 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1588 (hcchar & HCCHAR_MULTICNT_MASK) >>
1589 HCCHAR_MULTICNT_SHIFT);
1591 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1593 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1596 chan->xfer_started = 1;
1599 if (!hsotg->params.host_dma &&
1600 !chan->ep_is_in && chan->xfer_len > 0)
1601 /* Load OUT packet into the appropriate Tx FIFO */
1602 dwc2_hc_write_packet(hsotg, chan);
1606 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1607 * host channel and starts the transfer in Descriptor DMA mode
1609 * @hsotg: Programming view of DWC_otg controller
1610 * @chan: Information needed to initialize the host channel
1612 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1613 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1614 * with micro-frame bitmap.
1616 * Initializes HCDMA register with descriptor list address and CTD value then
1617 * starts the transfer via enabling the channel.
1619 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1620 struct dwc2_host_chan *chan)
1626 hctsiz |= TSIZ_DOPNG;
1628 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1629 dwc2_set_pid_isoc(chan);
1631 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1632 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1633 TSIZ_SC_MC_PID_MASK;
1635 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1636 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1638 /* Non-zero only for high-speed interrupt endpoints */
1639 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1642 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1644 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1645 chan->data_pid_start);
1646 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1649 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1651 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1652 chan->desc_list_sz, DMA_TO_DEVICE);
1654 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1657 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1658 &chan->desc_list_addr, chan->hc_num);
1660 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1661 hcchar &= ~HCCHAR_MULTICNT_MASK;
1662 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1663 HCCHAR_MULTICNT_MASK;
1665 if (hcchar & HCCHAR_CHDIS)
1666 dev_warn(hsotg->dev,
1667 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1668 __func__, chan->hc_num, hcchar);
1670 /* Set host channel enable after all other setup is complete */
1671 hcchar |= HCCHAR_CHENA;
1672 hcchar &= ~HCCHAR_CHDIS;
1675 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1676 (hcchar & HCCHAR_MULTICNT_MASK) >>
1677 HCCHAR_MULTICNT_SHIFT);
1679 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1681 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1684 chan->xfer_started = 1;
1689 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1690 * a previous call to dwc2_hc_start_transfer()
1692 * @hsotg: Programming view of DWC_otg controller
1693 * @chan: Information needed to initialize the host channel
1695 * The caller must ensure there is sufficient space in the request queue and Tx
1696 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1697 * the controller acts autonomously to complete transfers programmed to a host
1700 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1701 * if there is any data remaining to be queued. For an IN transfer, another
1702 * data packet is always requested. For the SETUP phase of a control transfer,
1703 * this function does nothing.
1705 * Return: 1 if a new request is queued, 0 if no more requests are required
1708 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1709 struct dwc2_host_chan *chan)
1712 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1716 /* SPLITs always queue just once per channel */
1719 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1720 /* SETUPs are queued only once since they can't be NAK'd */
1723 if (chan->ep_is_in) {
1725 * Always queue another request for other IN transfers. If
1726 * back-to-back INs are issued and NAKs are received for both,
1727 * the driver may still be processing the first NAK when the
1728 * second NAK is received. When the interrupt handler clears
1729 * the NAK interrupt for the first NAK, the second NAK will
1730 * not be seen. So we can't depend on the NAK interrupt
1731 * handler to requeue a NAK'd request. Instead, IN requests
1732 * are issued each time this function is called. When the
1733 * transfer completes, the extra requests for the channel will
1736 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1738 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1739 hcchar |= HCCHAR_CHENA;
1740 hcchar &= ~HCCHAR_CHDIS;
1742 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1744 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1751 if (chan->xfer_count < chan->xfer_len) {
1752 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1753 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1754 u32 hcchar = dwc2_readl(hsotg->regs +
1755 HCCHAR(chan->hc_num));
1757 dwc2_hc_set_even_odd_frame(hsotg, chan,
1761 /* Load OUT packet into the appropriate Tx FIFO */
1762 dwc2_hc_write_packet(hsotg, chan);
1771 * =========================================================================
1773 * =========================================================================
1777 * Processes all the URBs in a single list of QHs. Completes them with
1778 * -ETIMEDOUT and frees the QTD.
1780 * Must be called with interrupt disabled and spinlock held
1782 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1783 struct list_head *qh_list)
1785 struct dwc2_qh *qh, *qh_tmp;
1786 struct dwc2_qtd *qtd, *qtd_tmp;
1788 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1789 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1791 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1792 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1797 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1798 struct list_head *qh_list)
1800 struct dwc2_qtd *qtd, *qtd_tmp;
1801 struct dwc2_qh *qh, *qh_tmp;
1802 unsigned long flags;
1805 /* The list hasn't been initialized yet */
1808 spin_lock_irqsave(&hsotg->lock, flags);
1810 /* Ensure there are no QTDs or URBs left */
1811 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1813 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1814 dwc2_hcd_qh_unlink(hsotg, qh);
1816 /* Free each QTD in the QH's QTD list */
1817 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1819 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1821 if (qh->channel && qh->channel->qh == qh)
1822 qh->channel->qh = NULL;
1824 spin_unlock_irqrestore(&hsotg->lock, flags);
1825 dwc2_hcd_qh_free(hsotg, qh);
1826 spin_lock_irqsave(&hsotg->lock, flags);
1829 spin_unlock_irqrestore(&hsotg->lock, flags);
1833 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1834 * and periodic schedules. The QTD associated with each URB is removed from
1835 * the schedule and freed. This function may be called when a disconnect is
1836 * detected or when the HCD is being stopped.
1838 * Must be called with interrupt disabled and spinlock held
1840 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1842 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1843 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1844 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1845 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1846 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1847 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1851 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1853 * @hsotg: Pointer to struct dwc2_hsotg
1855 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1859 if (hsotg->op_state == OTG_STATE_B_HOST) {
1861 * Reset the port. During a HNP mode switch the reset
1862 * needs to occur within 1ms and have a duration of at
1865 hprt0 = dwc2_read_hprt0(hsotg);
1867 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1870 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1871 msecs_to_jiffies(50));
1874 /* Must be called with interrupt disabled and spinlock held */
1875 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1877 int num_channels = hsotg->params.host_channels;
1878 struct dwc2_host_chan *channel;
1882 if (!hsotg->params.host_dma) {
1883 /* Flush out any channel requests in slave mode */
1884 for (i = 0; i < num_channels; i++) {
1885 channel = hsotg->hc_ptr_array[i];
1886 if (!list_empty(&channel->hc_list_entry))
1888 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1889 if (hcchar & HCCHAR_CHENA) {
1890 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1891 hcchar |= HCCHAR_CHDIS;
1892 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1897 for (i = 0; i < num_channels; i++) {
1898 channel = hsotg->hc_ptr_array[i];
1899 if (!list_empty(&channel->hc_list_entry))
1901 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1902 if (hcchar & HCCHAR_CHENA) {
1903 /* Halt the channel */
1904 hcchar |= HCCHAR_CHDIS;
1905 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1908 dwc2_hc_cleanup(hsotg, channel);
1909 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1911 * Added for Descriptor DMA to prevent channel double cleanup in
1912 * release_channel_ddma(), which is called from ep_disable when
1913 * device disconnects
1917 /* All channels have been freed, mark them available */
1918 if (hsotg->params.uframe_sched) {
1919 hsotg->available_host_channels =
1920 hsotg->params.host_channels;
1922 hsotg->non_periodic_channels = 0;
1923 hsotg->periodic_channels = 0;
1928 * dwc2_hcd_connect() - Handles connect of the HCD
1930 * @hsotg: Pointer to struct dwc2_hsotg
1932 * Must be called with interrupt disabled and spinlock held
1934 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1936 if (hsotg->lx_state != DWC2_L0)
1937 usb_hcd_resume_root_hub(hsotg->priv);
1939 hsotg->flags.b.port_connect_status_change = 1;
1940 hsotg->flags.b.port_connect_status = 1;
1944 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1946 * @hsotg: Pointer to struct dwc2_hsotg
1947 * @force: If true, we won't try to reconnect even if we see device connected.
1949 * Must be called with interrupt disabled and spinlock held
1951 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1956 /* Set status flags for the hub driver */
1957 hsotg->flags.b.port_connect_status_change = 1;
1958 hsotg->flags.b.port_connect_status = 0;
1961 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1962 * interrupt mask and status bits and disabling subsequent host
1963 * channel interrupts.
1965 intr = dwc2_readl(hsotg->regs + GINTMSK);
1966 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1967 dwc2_writel(intr, hsotg->regs + GINTMSK);
1968 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1969 dwc2_writel(intr, hsotg->regs + GINTSTS);
1972 * Turn off the vbus power only if the core has transitioned to device
1973 * mode. If still in host mode, need to keep power on to detect a
1976 if (dwc2_is_device_mode(hsotg)) {
1977 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1978 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1979 dwc2_writel(0, hsotg->regs + HPRT0);
1982 dwc2_disable_host_interrupts(hsotg);
1985 /* Respond with an error status to all URBs in the schedule */
1986 dwc2_kill_all_urbs(hsotg);
1988 if (dwc2_is_host_mode(hsotg))
1989 /* Clean up any host channels that were in use */
1990 dwc2_hcd_cleanup_channels(hsotg);
1992 dwc2_host_disconnect(hsotg);
1995 * Add an extra check here to see if we're actually connected but
1996 * we don't have a detection interrupt pending. This can happen if:
1997 * 1. hardware sees connect
1998 * 2. hardware sees disconnect
1999 * 3. hardware sees connect
2000 * 4. dwc2_port_intr() - clears connect interrupt
2001 * 5. dwc2_handle_common_intr() - calls here
2003 * Without the extra check here we will end calling disconnect
2004 * and won't get any future interrupts to handle the connect.
2007 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2008 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2009 dwc2_hcd_connect(hsotg);
2014 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2016 * @hsotg: Pointer to struct dwc2_hsotg
2018 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2020 if (hsotg->bus_suspended) {
2021 hsotg->flags.b.port_suspend_change = 1;
2022 usb_hcd_resume_root_hub(hsotg->priv);
2025 if (hsotg->lx_state == DWC2_L1)
2026 hsotg->flags.b.port_l1_change = 1;
2030 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2032 * @hsotg: Pointer to struct dwc2_hsotg
2034 * Must be called with interrupt disabled and spinlock held
2036 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2038 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2041 * The root hub should be disconnected before this function is called.
2042 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2043 * and the QH lists (via ..._hcd_endpoint_disable).
2046 /* Turn off all host-specific interrupts */
2047 dwc2_disable_host_interrupts(hsotg);
2049 /* Turn off the vbus power */
2050 dev_dbg(hsotg->dev, "PortPower off\n");
2051 dwc2_writel(0, hsotg->regs + HPRT0);
2054 /* Caller must hold driver lock */
2055 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2056 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2057 struct dwc2_qtd *qtd)
2063 if (!hsotg->flags.b.port_connect_status) {
2064 /* No longer connected */
2065 dev_err(hsotg->dev, "Not connected\n");
2069 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2071 /* Some configurations cannot support LS traffic on a FS root port */
2072 if ((dev_speed == USB_SPEED_LOW) &&
2073 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2074 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2075 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2076 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2078 if (prtspd == HPRT0_SPD_FULL_SPEED)
2085 dwc2_hcd_qtd_init(qtd, urb);
2086 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2089 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2094 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2095 if (!(intr_mask & GINTSTS_SOF)) {
2096 enum dwc2_transaction_type tr_type;
2098 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2099 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2101 * Do not schedule SG transactions until qtd has
2102 * URB_GIVEBACK_ASAP set
2106 tr_type = dwc2_hcd_select_transactions(hsotg);
2107 if (tr_type != DWC2_TRANSACTION_NONE)
2108 dwc2_hcd_queue_transactions(hsotg, tr_type);
2114 /* Must be called with interrupt disabled and spinlock held */
2115 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2116 struct dwc2_hcd_urb *urb)
2119 struct dwc2_qtd *urb_qtd;
2123 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2129 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2135 if (urb_qtd->in_process && qh->channel) {
2136 dwc2_dump_channel_info(hsotg, qh->channel);
2138 /* The QTD is in process (it has been assigned to a channel) */
2139 if (hsotg->flags.b.port_connect_status)
2141 * If still connected (i.e. in host mode), halt the
2142 * channel so it can be used for other transfers. If
2143 * no longer connected, the host registers can't be
2144 * written to halt the channel since the core is in
2147 dwc2_hc_halt(hsotg, qh->channel,
2148 DWC2_HC_XFER_URB_DEQUEUE);
2152 * Free the QTD and clean up the associated QH. Leave the QH in the
2153 * schedule if it has any remaining QTDs.
2155 if (!hsotg->params.dma_desc_enable) {
2156 u8 in_process = urb_qtd->in_process;
2158 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2160 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2162 } else if (list_empty(&qh->qtd_list)) {
2163 dwc2_hcd_qh_unlink(hsotg, qh);
2166 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2172 /* Must NOT be called with interrupt disabled or spinlock held */
2173 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2174 struct usb_host_endpoint *ep, int retry)
2176 struct dwc2_qtd *qtd, *qtd_tmp;
2178 unsigned long flags;
2181 spin_lock_irqsave(&hsotg->lock, flags);
2189 while (!list_empty(&qh->qtd_list) && retry--) {
2192 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2197 spin_unlock_irqrestore(&hsotg->lock, flags);
2199 spin_lock_irqsave(&hsotg->lock, flags);
2207 dwc2_hcd_qh_unlink(hsotg, qh);
2209 /* Free each QTD in the QH's QTD list */
2210 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2211 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2215 if (qh->channel && qh->channel->qh == qh)
2216 qh->channel->qh = NULL;
2218 spin_unlock_irqrestore(&hsotg->lock, flags);
2220 dwc2_hcd_qh_free(hsotg, qh);
2226 spin_unlock_irqrestore(&hsotg->lock, flags);
2231 /* Must be called with interrupt disabled and spinlock held */
2232 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2233 struct usb_host_endpoint *ep)
2235 struct dwc2_qh *qh = ep->hcpriv;
2240 qh->data_toggle = DWC2_HC_PID_DATA0;
2246 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2247 * prepares the core for device mode or host mode operation
2249 * @hsotg: Programming view of the DWC_otg controller
2250 * @initial_setup: If true then this is the first init for this instance.
2252 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2257 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2259 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2261 /* Set ULPI External VBUS bit if needed */
2262 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2263 if (hsotg->params.phy_ulpi_ext_vbus)
2264 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2266 /* Set external TS Dline pulsing bit if needed */
2267 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2268 if (hsotg->params.ts_dline)
2269 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2271 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2274 * Reset the Controller
2276 * We only need to reset the controller if this is a re-init.
2277 * For the first init we know for sure that earlier code reset us (it
2278 * needed to in order to properly detect various parameters).
2280 if (!initial_setup) {
2281 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2283 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2290 * This needs to happen in FS mode before any other programming occurs
2292 retval = dwc2_phy_init(hsotg, initial_setup);
2296 /* Program the GAHBCFG Register */
2297 retval = dwc2_gahbcfg_init(hsotg);
2301 /* Program the GUSBCFG register */
2302 dwc2_gusbcfg_init(hsotg);
2304 /* Program the GOTGCTL register */
2305 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2306 otgctl &= ~GOTGCTL_OTGVER;
2307 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2309 /* Clear the SRP success bit for FS-I2c */
2310 hsotg->srp_success = 0;
2312 /* Enable common interrupts */
2313 dwc2_enable_common_interrupts(hsotg);
2316 * Do device or host initialization based on mode during PCD and
2317 * HCD initialization
2319 if (dwc2_is_host_mode(hsotg)) {
2320 dev_dbg(hsotg->dev, "Host Mode\n");
2321 hsotg->op_state = OTG_STATE_A_HOST;
2323 dev_dbg(hsotg->dev, "Device Mode\n");
2324 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2331 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2334 * @hsotg: Programming view of DWC_otg controller
2336 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2337 * request queues. Host channels are reset to ensure that they are ready for
2338 * performing transfers.
2340 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2342 u32 hcfg, hfir, otgctl, usbcfg;
2344 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2346 /* Set HS/FS Timeout Calibration to 7 (max available value).
2347 * The number of PHY clocks that the application programs in
2348 * this field is added to the high/full speed interpacket timeout
2349 * duration in the core to account for any additional delays
2350 * introduced by the PHY. This can be required, because the delay
2351 * introduced by the PHY in generating the linestate condition
2352 * can vary from one PHY to another.
2354 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2355 usbcfg |= GUSBCFG_TOUTCAL(7);
2356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2358 /* Restart the Phy Clock */
2359 dwc2_writel(0, hsotg->regs + PCGCTL);
2361 /* Initialize Host Configuration Register */
2362 dwc2_init_fs_ls_pclk_sel(hsotg);
2363 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2364 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2365 hcfg = dwc2_readl(hsotg->regs + HCFG);
2366 hcfg |= HCFG_FSLSSUPP;
2367 dwc2_writel(hcfg, hsotg->regs + HCFG);
2371 * This bit allows dynamic reloading of the HFIR register during
2372 * runtime. This bit needs to be programmed during initial configuration
2373 * and its value must not be changed during runtime.
2375 if (hsotg->params.reload_ctl) {
2376 hfir = dwc2_readl(hsotg->regs + HFIR);
2377 hfir |= HFIR_RLDCTRL;
2378 dwc2_writel(hfir, hsotg->regs + HFIR);
2381 if (hsotg->params.dma_desc_enable) {
2382 u32 op_mode = hsotg->hw_params.op_mode;
2384 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2385 !hsotg->hw_params.dma_desc_enable ||
2386 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2387 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2388 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2390 "Hardware does not support descriptor DMA mode -\n");
2392 "falling back to buffer DMA mode.\n");
2393 hsotg->params.dma_desc_enable = false;
2395 hcfg = dwc2_readl(hsotg->regs + HCFG);
2396 hcfg |= HCFG_DESCDMA;
2397 dwc2_writel(hcfg, hsotg->regs + HCFG);
2401 /* Configure data FIFO sizes */
2402 dwc2_config_fifos(hsotg);
2404 /* TODO - check this */
2405 /* Clear Host Set HNP Enable in the OTG Control Register */
2406 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2407 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2408 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2410 /* Make sure the FIFOs are flushed */
2411 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2412 dwc2_flush_rx_fifo(hsotg);
2414 /* Clear Host Set HNP Enable in the OTG Control Register */
2415 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2416 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2417 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2419 if (!hsotg->params.dma_desc_enable) {
2420 int num_channels, i;
2423 /* Flush out any leftover queued requests */
2424 num_channels = hsotg->params.host_channels;
2425 for (i = 0; i < num_channels; i++) {
2426 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2427 hcchar &= ~HCCHAR_CHENA;
2428 hcchar |= HCCHAR_CHDIS;
2429 hcchar &= ~HCCHAR_EPDIR;
2430 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2433 /* Halt all channels to put them into a known state */
2434 for (i = 0; i < num_channels; i++) {
2437 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2438 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2439 hcchar &= ~HCCHAR_EPDIR;
2440 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2441 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2444 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2445 if (++count > 1000) {
2447 "Unable to clear enable on channel %d\n",
2452 } while (hcchar & HCCHAR_CHENA);
2456 /* Turn on the vbus power */
2457 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2458 if (hsotg->op_state == OTG_STATE_A_HOST) {
2459 u32 hprt0 = dwc2_read_hprt0(hsotg);
2461 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2462 !!(hprt0 & HPRT0_PWR));
2463 if (!(hprt0 & HPRT0_PWR)) {
2465 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2469 dwc2_enable_host_interrupts(hsotg);
2473 * Initializes dynamic portions of the DWC_otg HCD state
2475 * Must be called with interrupt disabled and spinlock held
2477 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2479 struct dwc2_host_chan *chan, *chan_tmp;
2483 hsotg->flags.d32 = 0;
2484 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2486 if (hsotg->params.uframe_sched) {
2487 hsotg->available_host_channels =
2488 hsotg->params.host_channels;
2490 hsotg->non_periodic_channels = 0;
2491 hsotg->periodic_channels = 0;
2495 * Put all channels in the free channel list and clean up channel
2498 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2500 list_del_init(&chan->hc_list_entry);
2502 num_channels = hsotg->params.host_channels;
2503 for (i = 0; i < num_channels; i++) {
2504 chan = hsotg->hc_ptr_array[i];
2505 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2506 dwc2_hc_cleanup(hsotg, chan);
2509 /* Initialize the DWC core for host mode operation */
2510 dwc2_core_host_init(hsotg);
2513 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2514 struct dwc2_host_chan *chan,
2515 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2517 int hub_addr, hub_port;
2520 chan->xact_pos = qtd->isoc_split_pos;
2521 chan->complete_split = qtd->complete_split;
2522 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2523 chan->hub_addr = (u8)hub_addr;
2524 chan->hub_port = (u8)hub_port;
2527 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2528 struct dwc2_host_chan *chan,
2529 struct dwc2_qtd *qtd)
2531 struct dwc2_hcd_urb *urb = qtd->urb;
2532 struct dwc2_hcd_iso_packet_desc *frame_desc;
2534 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2535 case USB_ENDPOINT_XFER_CONTROL:
2536 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2538 switch (qtd->control_phase) {
2539 case DWC2_CONTROL_SETUP:
2540 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2543 chan->data_pid_start = DWC2_HC_PID_SETUP;
2544 if (hsotg->params.host_dma)
2545 chan->xfer_dma = urb->setup_dma;
2547 chan->xfer_buf = urb->setup_packet;
2551 case DWC2_CONTROL_DATA:
2552 dev_vdbg(hsotg->dev, " Control data transaction\n");
2553 chan->data_pid_start = qtd->data_toggle;
2556 case DWC2_CONTROL_STATUS:
2558 * Direction is opposite of data direction or IN if no
2561 dev_vdbg(hsotg->dev, " Control status transaction\n");
2562 if (urb->length == 0)
2566 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2569 chan->data_pid_start = DWC2_HC_PID_DATA1;
2571 if (hsotg->params.host_dma)
2572 chan->xfer_dma = hsotg->status_buf_dma;
2574 chan->xfer_buf = hsotg->status_buf;
2579 case USB_ENDPOINT_XFER_BULK:
2580 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2583 case USB_ENDPOINT_XFER_INT:
2584 chan->ep_type = USB_ENDPOINT_XFER_INT;
2587 case USB_ENDPOINT_XFER_ISOC:
2588 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2589 if (hsotg->params.dma_desc_enable)
2592 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2593 frame_desc->status = 0;
2595 if (hsotg->params.host_dma) {
2596 chan->xfer_dma = urb->dma;
2597 chan->xfer_dma += frame_desc->offset +
2598 qtd->isoc_split_offset;
2600 chan->xfer_buf = urb->buf;
2601 chan->xfer_buf += frame_desc->offset +
2602 qtd->isoc_split_offset;
2605 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2607 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2608 if (chan->xfer_len <= 188)
2609 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2611 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2617 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2619 struct dwc2_host_chan *chan)
2621 if (!hsotg->unaligned_cache ||
2622 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2625 if (!qh->dw_align_buf) {
2626 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2627 GFP_ATOMIC | GFP_DMA);
2628 if (!qh->dw_align_buf)
2632 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2633 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2636 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2637 dev_err(hsotg->dev, "can't map align_buf\n");
2638 chan->align_buf = 0;
2642 chan->align_buf = qh->dw_align_buf_dma;
2646 #define DWC2_USB_DMA_ALIGN 4
2648 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2650 void *stored_xfer_buffer;
2652 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2655 /* Restore urb->transfer_buffer from the end of the allocated area */
2656 memcpy(&stored_xfer_buffer,
2657 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
2658 dma_get_cache_alignment()),
2659 sizeof(urb->transfer_buffer));
2661 if (usb_urb_dir_in(urb))
2662 memcpy(stored_xfer_buffer, urb->transfer_buffer,
2663 urb->transfer_buffer_length);
2664 kfree(urb->transfer_buffer);
2665 urb->transfer_buffer = stored_xfer_buffer;
2667 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2670 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2673 size_t kmalloc_size;
2675 if (urb->num_sgs || urb->sg ||
2676 urb->transfer_buffer_length == 0 ||
2677 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2681 * Allocate a buffer with enough padding for original transfer_buffer
2682 * pointer. This allocation is guaranteed to be aligned properly for
2685 kmalloc_size = urb->transfer_buffer_length +
2686 (dma_get_cache_alignment() - 1) +
2687 sizeof(urb->transfer_buffer);
2689 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2694 * Position value of original urb->transfer_buffer pointer to the end
2695 * of allocation for later referencing
2697 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
2698 dma_get_cache_alignment()),
2699 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2701 if (usb_urb_dir_out(urb))
2702 memcpy(kmalloc_ptr, urb->transfer_buffer,
2703 urb->transfer_buffer_length);
2704 urb->transfer_buffer = kmalloc_ptr;
2706 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2711 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2716 /* We assume setup_dma is always aligned; warn if not */
2717 WARN_ON_ONCE(urb->setup_dma &&
2718 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2720 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2724 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2726 dwc2_free_dma_aligned_buffer(urb);
2731 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2733 usb_hcd_unmap_urb_for_dma(hcd, urb);
2734 dwc2_free_dma_aligned_buffer(urb);
2738 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2739 * channel and initializes the host channel to perform the transactions. The
2740 * host channel is removed from the free list.
2742 * @hsotg: The HCD state structure
2743 * @qh: Transactions from the first QTD for this QH are selected and assigned
2744 * to a free host channel
2746 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2748 struct dwc2_host_chan *chan;
2749 struct dwc2_hcd_urb *urb;
2750 struct dwc2_qtd *qtd;
2753 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2755 if (list_empty(&qh->qtd_list)) {
2756 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2760 if (list_empty(&hsotg->free_hc_list)) {
2761 dev_dbg(hsotg->dev, "No free channel to assign\n");
2765 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2768 /* Remove host channel from free list */
2769 list_del_init(&chan->hc_list_entry);
2771 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2774 qtd->in_process = 1;
2777 * Use usb_pipedevice to determine device address. This address is
2778 * 0 before the SET_ADDRESS command and the correct address afterward.
2780 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2781 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2782 chan->speed = qh->dev_speed;
2783 chan->max_packet = qh->maxp;
2785 chan->xfer_started = 0;
2786 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2787 chan->error_state = (qtd->error_count > 0);
2788 chan->halt_on_queue = 0;
2789 chan->halt_pending = 0;
2793 * The following values may be modified in the transfer type section
2794 * below. The xfer_len value may be reduced when the transfer is
2795 * started to accommodate the max widths of the XferSize and PktCnt
2796 * fields in the HCTSIZn register.
2799 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2803 chan->do_ping = qh->ping_state;
2805 chan->data_pid_start = qh->data_toggle;
2806 chan->multi_count = 1;
2808 if (urb->actual_length > urb->length &&
2809 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2810 urb->actual_length = urb->length;
2812 if (hsotg->params.host_dma)
2813 chan->xfer_dma = urb->dma + urb->actual_length;
2815 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2817 chan->xfer_len = urb->length - urb->actual_length;
2818 chan->xfer_count = 0;
2820 /* Set the split attributes if required */
2822 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2826 /* Set the transfer attributes */
2827 dwc2_hc_init_xfer(hsotg, chan, qtd);
2829 /* For non-dword aligned buffers */
2830 if (hsotg->params.host_dma && qh->do_split &&
2831 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2832 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2833 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2835 "Failed to allocate memory to handle non-aligned buffer\n");
2836 /* Add channel back to free list */
2837 chan->align_buf = 0;
2838 chan->multi_count = 0;
2839 list_add_tail(&chan->hc_list_entry,
2840 &hsotg->free_hc_list);
2841 qtd->in_process = 0;
2847 * We assume that DMA is always aligned in non-split
2848 * case or split out case. Warn if not.
2850 WARN_ON_ONCE(hsotg->params.host_dma &&
2851 (chan->xfer_dma & 0x3));
2852 chan->align_buf = 0;
2855 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2856 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2858 * This value may be modified when the transfer is started
2859 * to reflect the actual transfer length
2861 chan->multi_count = qh->maxp_mult;
2863 if (hsotg->params.dma_desc_enable) {
2864 chan->desc_list_addr = qh->desc_list_dma;
2865 chan->desc_list_sz = qh->desc_list_sz;
2868 dwc2_hc_init(hsotg, chan);
2875 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2876 * schedule and assigns them to available host channels. Called from the HCD
2877 * interrupt handler functions.
2879 * @hsotg: The HCD state structure
2881 * Return: The types of new transactions that were assigned to host channels
2883 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2884 struct dwc2_hsotg *hsotg)
2886 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2887 struct list_head *qh_ptr;
2891 #ifdef DWC2_DEBUG_SOF
2892 dev_vdbg(hsotg->dev, " Select Transactions\n");
2895 /* Process entries in the periodic ready list */
2896 qh_ptr = hsotg->periodic_sched_ready.next;
2897 while (qh_ptr != &hsotg->periodic_sched_ready) {
2898 if (list_empty(&hsotg->free_hc_list))
2900 if (hsotg->params.uframe_sched) {
2901 if (hsotg->available_host_channels <= 1)
2903 hsotg->available_host_channels--;
2905 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2906 if (dwc2_assign_and_init_hc(hsotg, qh))
2910 * Move the QH from the periodic ready schedule to the
2911 * periodic assigned schedule
2913 qh_ptr = qh_ptr->next;
2914 list_move_tail(&qh->qh_list_entry,
2915 &hsotg->periodic_sched_assigned);
2916 ret_val = DWC2_TRANSACTION_PERIODIC;
2920 * Process entries in the inactive portion of the non-periodic
2921 * schedule. Some free host channels may not be used if they are
2922 * reserved for periodic transfers.
2924 num_channels = hsotg->params.host_channels;
2925 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2926 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2927 if (!hsotg->params.uframe_sched &&
2928 hsotg->non_periodic_channels >= num_channels -
2929 hsotg->periodic_channels)
2931 if (list_empty(&hsotg->free_hc_list))
2933 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2934 if (hsotg->params.uframe_sched) {
2935 if (hsotg->available_host_channels < 1)
2937 hsotg->available_host_channels--;
2940 if (dwc2_assign_and_init_hc(hsotg, qh))
2944 * Move the QH from the non-periodic inactive schedule to the
2945 * non-periodic active schedule
2947 qh_ptr = qh_ptr->next;
2948 list_move_tail(&qh->qh_list_entry,
2949 &hsotg->non_periodic_sched_active);
2951 if (ret_val == DWC2_TRANSACTION_NONE)
2952 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2954 ret_val = DWC2_TRANSACTION_ALL;
2956 if (!hsotg->params.uframe_sched)
2957 hsotg->non_periodic_channels++;
2964 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2965 * a host channel associated with either a periodic or non-periodic transfer
2967 * @hsotg: The HCD state structure
2968 * @chan: Host channel descriptor associated with either a periodic or
2969 * non-periodic transfer
2970 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2971 * for periodic transfers or the non-periodic Tx FIFO
2972 * for non-periodic transfers
2974 * Return: 1 if a request is queued and more requests may be needed to
2975 * complete the transfer, 0 if no more requests are required for this
2976 * transfer, -1 if there is insufficient space in the Tx FIFO
2978 * This function assumes that there is space available in the appropriate
2979 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2980 * it checks whether space is available in the appropriate Tx FIFO.
2982 * Must be called with interrupt disabled and spinlock held
2984 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2985 struct dwc2_host_chan *chan,
2986 u16 fifo_dwords_avail)
2991 /* Put ourselves on the list to keep order straight */
2992 list_move_tail(&chan->split_order_list_entry,
2993 &hsotg->split_order);
2995 if (hsotg->params.host_dma) {
2996 if (hsotg->params.dma_desc_enable) {
2997 if (!chan->xfer_started ||
2998 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2999 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
3000 chan->qh->ping_state = 0;
3002 } else if (!chan->xfer_started) {
3003 dwc2_hc_start_transfer(hsotg, chan);
3004 chan->qh->ping_state = 0;
3006 } else if (chan->halt_pending) {
3007 /* Don't queue a request if the channel has been halted */
3008 } else if (chan->halt_on_queue) {
3009 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3010 } else if (chan->do_ping) {
3011 if (!chan->xfer_started)
3012 dwc2_hc_start_transfer(hsotg, chan);
3013 } else if (!chan->ep_is_in ||
3014 chan->data_pid_start == DWC2_HC_PID_SETUP) {
3015 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3016 if (!chan->xfer_started) {
3017 dwc2_hc_start_transfer(hsotg, chan);
3020 retval = dwc2_hc_continue_transfer(hsotg, chan);
3026 if (!chan->xfer_started) {
3027 dwc2_hc_start_transfer(hsotg, chan);
3030 retval = dwc2_hc_continue_transfer(hsotg, chan);
3038 * Processes periodic channels for the next frame and queues transactions for
3039 * these channels to the DWC_otg controller. After queueing transactions, the
3040 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3041 * to queue as Periodic Tx FIFO or request queue space becomes available.
3042 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3044 * Must be called with interrupt disabled and spinlock held
3046 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3048 struct list_head *qh_ptr;
3054 bool no_queue_space = false;
3055 bool no_fifo_space = false;
3058 /* If empty list then just adjust interrupt enables */
3059 if (list_empty(&hsotg->periodic_sched_assigned))
3063 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3065 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3066 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3067 TXSTS_QSPCAVAIL_SHIFT;
3068 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3069 TXSTS_FSPCAVAIL_SHIFT;
3072 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3074 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3078 qh_ptr = hsotg->periodic_sched_assigned.next;
3079 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3080 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3081 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3082 TXSTS_QSPCAVAIL_SHIFT;
3083 if (qspcavail == 0) {
3084 no_queue_space = true;
3088 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3090 qh_ptr = qh_ptr->next;
3094 /* Make sure EP's TT buffer is clean before queueing qtds */
3095 if (qh->tt_buffer_dirty) {
3096 qh_ptr = qh_ptr->next;
3101 * Set a flag if we're queuing high-bandwidth in slave mode.
3102 * The flag prevents any halts to get into the request queue in
3103 * the middle of multiple high-bandwidth packets getting queued.
3105 if (!hsotg->params.host_dma &&
3106 qh->channel->multi_count > 1)
3107 hsotg->queuing_high_bandwidth = 1;
3109 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3110 TXSTS_FSPCAVAIL_SHIFT;
3111 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3113 no_fifo_space = true;
3118 * In Slave mode, stay on the current transfer until there is
3119 * nothing more to do or the high-bandwidth request count is
3120 * reached. In DMA mode, only need to queue one request. The
3121 * controller automatically handles multiple packets for
3122 * high-bandwidth transfers.
3124 if (hsotg->params.host_dma || status == 0 ||
3125 qh->channel->requests == qh->channel->multi_count) {
3126 qh_ptr = qh_ptr->next;
3128 * Move the QH from the periodic assigned schedule to
3129 * the periodic queued schedule
3131 list_move_tail(&qh->qh_list_entry,
3132 &hsotg->periodic_sched_queued);
3134 /* done queuing high bandwidth */
3135 hsotg->queuing_high_bandwidth = 0;
3140 if (no_queue_space || no_fifo_space ||
3141 (!hsotg->params.host_dma &&
3142 !list_empty(&hsotg->periodic_sched_assigned))) {
3144 * May need to queue more transactions as the request
3145 * queue or Tx FIFO empties. Enable the periodic Tx
3146 * FIFO empty interrupt. (Always use the half-empty
3147 * level to ensure that new requests are loaded as
3148 * soon as possible.)
3150 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3151 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3152 gintmsk |= GINTSTS_PTXFEMP;
3153 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3157 * Disable the Tx FIFO empty interrupt since there are
3158 * no more transactions that need to be queued right
3159 * now. This function is called from interrupt
3160 * handlers to queue more transactions as transfer
3163 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3164 if (gintmsk & GINTSTS_PTXFEMP) {
3165 gintmsk &= ~GINTSTS_PTXFEMP;
3166 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3172 * Processes active non-periodic channels and queues transactions for these
3173 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3174 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3175 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3176 * FIFO Empty interrupt is disabled.
3178 * Must be called with interrupt disabled and spinlock held
3180 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3182 struct list_head *orig_qh_ptr;
3189 int no_queue_space = 0;
3190 int no_fifo_space = 0;
3193 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3195 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3196 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3197 TXSTS_QSPCAVAIL_SHIFT;
3198 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3199 TXSTS_FSPCAVAIL_SHIFT;
3200 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3202 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3206 * Keep track of the starting point. Skip over the start-of-list
3209 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3210 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3211 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3214 * Process once through the active list or until no more space is
3215 * available in the request queue or the Tx FIFO
3218 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3219 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3220 TXSTS_QSPCAVAIL_SHIFT;
3221 if (!hsotg->params.host_dma && qspcavail == 0) {
3226 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3231 /* Make sure EP's TT buffer is clean before queueing qtds */
3232 if (qh->tt_buffer_dirty)
3235 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3236 TXSTS_FSPCAVAIL_SHIFT;
3237 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3241 } else if (status < 0) {
3246 /* Advance to next QH, skipping start-of-list entry */
3247 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3248 if (hsotg->non_periodic_qh_ptr ==
3249 &hsotg->non_periodic_sched_active)
3250 hsotg->non_periodic_qh_ptr =
3251 hsotg->non_periodic_qh_ptr->next;
3252 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3254 if (!hsotg->params.host_dma) {
3255 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3256 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3257 TXSTS_QSPCAVAIL_SHIFT;
3258 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3259 TXSTS_FSPCAVAIL_SHIFT;
3260 dev_vdbg(hsotg->dev,
3261 " NP Tx Req Queue Space Avail (after queue): %d\n",
3263 dev_vdbg(hsotg->dev,
3264 " NP Tx FIFO Space Avail (after queue): %d\n",
3267 if (more_to_do || no_queue_space || no_fifo_space) {
3269 * May need to queue more transactions as the request
3270 * queue or Tx FIFO empties. Enable the non-periodic
3271 * Tx FIFO empty interrupt. (Always use the half-empty
3272 * level to ensure that new requests are loaded as
3273 * soon as possible.)
3275 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3276 gintmsk |= GINTSTS_NPTXFEMP;
3277 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3280 * Disable the Tx FIFO empty interrupt since there are
3281 * no more transactions that need to be queued right
3282 * now. This function is called from interrupt
3283 * handlers to queue more transactions as transfer
3286 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3287 gintmsk &= ~GINTSTS_NPTXFEMP;
3288 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3294 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3295 * and queues transactions for these channels to the DWC_otg controller. Called
3296 * from the HCD interrupt handler functions.
3298 * @hsotg: The HCD state structure
3299 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3302 * Must be called with interrupt disabled and spinlock held
3304 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3305 enum dwc2_transaction_type tr_type)
3307 #ifdef DWC2_DEBUG_SOF
3308 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3310 /* Process host channels associated with periodic transfers */
3311 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3312 tr_type == DWC2_TRANSACTION_ALL)
3313 dwc2_process_periodic_channels(hsotg);
3315 /* Process host channels associated with non-periodic transfers */
3316 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3317 tr_type == DWC2_TRANSACTION_ALL) {
3318 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3319 dwc2_process_non_periodic_channels(hsotg);
3322 * Ensure NP Tx FIFO empty interrupt is disabled when
3323 * there are no non-periodic transfers to process
3325 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3327 gintmsk &= ~GINTSTS_NPTXFEMP;
3328 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3333 static void dwc2_conn_id_status_change(struct work_struct *work)
3335 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3339 unsigned long flags;
3341 dev_dbg(hsotg->dev, "%s()\n", __func__);
3343 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3344 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3345 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3346 !!(gotgctl & GOTGCTL_CONID_B));
3348 /* B-Device connector (Device Mode) */
3349 if (gotgctl & GOTGCTL_CONID_B) {
3350 /* Wait for switch to device mode */
3351 dev_dbg(hsotg->dev, "connId B\n");
3352 if (hsotg->bus_suspended) {
3353 dev_info(hsotg->dev,
3354 "Do port resume before switching to device mode\n");
3355 dwc2_port_resume(hsotg);
3357 while (!dwc2_is_device_mode(hsotg)) {
3358 dev_info(hsotg->dev,
3359 "Waiting for Peripheral Mode, Mode=%s\n",
3360 dwc2_is_host_mode(hsotg) ? "Host" :
3364 * Sometimes the initial GOTGCTRL read is wrong, so
3365 * check it again and jump to host mode if that was
3368 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3369 if (!(gotgctl & GOTGCTL_CONID_B))
3376 "Connection id status change timed out\n");
3377 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3378 dwc2_core_init(hsotg, false);
3379 dwc2_enable_global_interrupts(hsotg);
3380 spin_lock_irqsave(&hsotg->lock, flags);
3381 dwc2_hsotg_core_init_disconnected(hsotg, false);
3382 spin_unlock_irqrestore(&hsotg->lock, flags);
3383 dwc2_hsotg_core_connect(hsotg);
3386 /* A-Device connector (Host Mode) */
3387 dev_dbg(hsotg->dev, "connId A\n");
3388 while (!dwc2_is_host_mode(hsotg)) {
3389 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3390 dwc2_is_host_mode(hsotg) ?
3391 "Host" : "Peripheral");
3398 "Connection id status change timed out\n");
3400 spin_lock_irqsave(&hsotg->lock, flags);
3401 dwc2_hsotg_disconnect(hsotg);
3402 spin_unlock_irqrestore(&hsotg->lock, flags);
3404 hsotg->op_state = OTG_STATE_A_HOST;
3405 /* Initialize the Core for Host mode */
3406 dwc2_core_init(hsotg, false);
3407 dwc2_enable_global_interrupts(hsotg);
3408 dwc2_hcd_start(hsotg);
3412 static void dwc2_wakeup_detected(unsigned long data)
3414 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3417 dev_dbg(hsotg->dev, "%s()\n", __func__);
3420 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3421 * so that OPT tests pass with all PHYs.)
3423 hprt0 = dwc2_read_hprt0(hsotg);
3424 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3425 hprt0 &= ~HPRT0_RES;
3426 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3427 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3428 dwc2_readl(hsotg->regs + HPRT0));
3430 dwc2_hcd_rem_wakeup(hsotg);
3431 hsotg->bus_suspended = false;
3433 /* Change to L0 state */
3434 hsotg->lx_state = DWC2_L0;
3437 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3439 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3441 return hcd->self.b_hnp_enable;
3444 /* Must NOT be called with interrupt disabled or spinlock held */
3445 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3447 unsigned long flags;
3452 dev_dbg(hsotg->dev, "%s()\n", __func__);
3454 spin_lock_irqsave(&hsotg->lock, flags);
3456 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3457 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3458 gotgctl |= GOTGCTL_HSTSETHNPEN;
3459 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3460 hsotg->op_state = OTG_STATE_A_SUSPEND;
3463 hprt0 = dwc2_read_hprt0(hsotg);
3464 hprt0 |= HPRT0_SUSP;
3465 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3467 hsotg->bus_suspended = true;
3470 * If hibernation is supported, Phy clock will be suspended
3471 * after registers are backuped.
3473 if (!hsotg->params.hibernation) {
3474 /* Suspend the Phy Clock */
3475 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3476 pcgctl |= PCGCTL_STOPPCLK;
3477 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3481 /* For HNP the bus must be suspended for at least 200ms */
3482 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3483 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3484 pcgctl &= ~PCGCTL_STOPPCLK;
3485 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3487 spin_unlock_irqrestore(&hsotg->lock, flags);
3491 spin_unlock_irqrestore(&hsotg->lock, flags);
3495 /* Must NOT be called with interrupt disabled or spinlock held */
3496 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3498 unsigned long flags;
3502 spin_lock_irqsave(&hsotg->lock, flags);
3505 * If hibernation is supported, Phy clock is already resumed
3506 * after registers restore.
3508 if (!hsotg->params.hibernation) {
3509 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3510 pcgctl &= ~PCGCTL_STOPPCLK;
3511 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3512 spin_unlock_irqrestore(&hsotg->lock, flags);
3514 spin_lock_irqsave(&hsotg->lock, flags);
3517 hprt0 = dwc2_read_hprt0(hsotg);
3519 hprt0 &= ~HPRT0_SUSP;
3520 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3521 spin_unlock_irqrestore(&hsotg->lock, flags);
3523 msleep(USB_RESUME_TIMEOUT);
3525 spin_lock_irqsave(&hsotg->lock, flags);
3526 hprt0 = dwc2_read_hprt0(hsotg);
3527 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3528 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3529 hsotg->bus_suspended = false;
3530 spin_unlock_irqrestore(&hsotg->lock, flags);
3533 /* Handles hub class-specific requests */
3534 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3535 u16 wvalue, u16 windex, char *buf, u16 wlength)
3537 struct usb_hub_descriptor *hub_desc;
3545 case ClearHubFeature:
3546 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3549 case C_HUB_LOCAL_POWER:
3550 case C_HUB_OVER_CURRENT:
3551 /* Nothing required here */
3557 "ClearHubFeature request %1xh unknown\n",
3562 case ClearPortFeature:
3563 if (wvalue != USB_PORT_FEAT_L1)
3564 if (!windex || windex > 1)
3567 case USB_PORT_FEAT_ENABLE:
3569 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3570 hprt0 = dwc2_read_hprt0(hsotg);
3572 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3575 case USB_PORT_FEAT_SUSPEND:
3577 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3579 if (hsotg->bus_suspended)
3580 dwc2_port_resume(hsotg);
3583 case USB_PORT_FEAT_POWER:
3585 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3586 hprt0 = dwc2_read_hprt0(hsotg);
3587 hprt0 &= ~HPRT0_PWR;
3588 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3591 case USB_PORT_FEAT_INDICATOR:
3593 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3594 /* Port indicator not supported */
3597 case USB_PORT_FEAT_C_CONNECTION:
3599 * Clears driver's internal Connect Status Change flag
3602 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3603 hsotg->flags.b.port_connect_status_change = 0;
3606 case USB_PORT_FEAT_C_RESET:
3607 /* Clears driver's internal Port Reset Change flag */
3609 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3610 hsotg->flags.b.port_reset_change = 0;
3613 case USB_PORT_FEAT_C_ENABLE:
3615 * Clears the driver's internal Port Enable/Disable
3619 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3620 hsotg->flags.b.port_enable_change = 0;
3623 case USB_PORT_FEAT_C_SUSPEND:
3625 * Clears the driver's internal Port Suspend Change
3626 * flag, which is set when resume signaling on the host
3630 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3631 hsotg->flags.b.port_suspend_change = 0;
3634 case USB_PORT_FEAT_C_PORT_L1:
3636 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3637 hsotg->flags.b.port_l1_change = 0;
3640 case USB_PORT_FEAT_C_OVER_CURRENT:
3642 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3643 hsotg->flags.b.port_over_current_change = 0;
3649 "ClearPortFeature request %1xh unknown or unsupported\n",
3654 case GetHubDescriptor:
3655 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3656 hub_desc = (struct usb_hub_descriptor *)buf;
3657 hub_desc->bDescLength = 9;
3658 hub_desc->bDescriptorType = USB_DT_HUB;
3659 hub_desc->bNbrPorts = 1;
3660 hub_desc->wHubCharacteristics =
3661 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3662 HUB_CHAR_INDV_PORT_OCPM);
3663 hub_desc->bPwrOn2PwrGood = 1;
3664 hub_desc->bHubContrCurrent = 0;
3665 hub_desc->u.hs.DeviceRemovable[0] = 0;
3666 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3670 dev_dbg(hsotg->dev, "GetHubStatus\n");
3675 dev_vdbg(hsotg->dev,
3676 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3678 if (!windex || windex > 1)
3682 if (hsotg->flags.b.port_connect_status_change)
3683 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3684 if (hsotg->flags.b.port_enable_change)
3685 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3686 if (hsotg->flags.b.port_suspend_change)
3687 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3688 if (hsotg->flags.b.port_l1_change)
3689 port_status |= USB_PORT_STAT_C_L1 << 16;
3690 if (hsotg->flags.b.port_reset_change)
3691 port_status |= USB_PORT_STAT_C_RESET << 16;
3692 if (hsotg->flags.b.port_over_current_change) {
3693 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3694 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3697 if (!hsotg->flags.b.port_connect_status) {
3699 * The port is disconnected, which means the core is
3700 * either in device mode or it soon will be. Just
3701 * return 0's for the remainder of the port status
3702 * since the port register can't be read if the core
3703 * is in device mode.
3705 *(__le32 *)buf = cpu_to_le32(port_status);
3709 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3710 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3712 if (hprt0 & HPRT0_CONNSTS)
3713 port_status |= USB_PORT_STAT_CONNECTION;
3714 if (hprt0 & HPRT0_ENA)
3715 port_status |= USB_PORT_STAT_ENABLE;
3716 if (hprt0 & HPRT0_SUSP)
3717 port_status |= USB_PORT_STAT_SUSPEND;
3718 if (hprt0 & HPRT0_OVRCURRACT)
3719 port_status |= USB_PORT_STAT_OVERCURRENT;
3720 if (hprt0 & HPRT0_RST)
3721 port_status |= USB_PORT_STAT_RESET;
3722 if (hprt0 & HPRT0_PWR)
3723 port_status |= USB_PORT_STAT_POWER;
3725 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3726 if (speed == HPRT0_SPD_HIGH_SPEED)
3727 port_status |= USB_PORT_STAT_HIGH_SPEED;
3728 else if (speed == HPRT0_SPD_LOW_SPEED)
3729 port_status |= USB_PORT_STAT_LOW_SPEED;
3731 if (hprt0 & HPRT0_TSTCTL_MASK)
3732 port_status |= USB_PORT_STAT_TEST;
3733 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3735 if (hsotg->params.dma_desc_fs_enable) {
3737 * Enable descriptor DMA only if a full speed
3738 * device is connected.
3740 if (hsotg->new_connection &&
3742 (USB_PORT_STAT_CONNECTION |
3743 USB_PORT_STAT_HIGH_SPEED |
3744 USB_PORT_STAT_LOW_SPEED)) ==
3745 USB_PORT_STAT_CONNECTION)) {
3748 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3749 hsotg->params.dma_desc_enable = true;
3750 hcfg = dwc2_readl(hsotg->regs + HCFG);
3751 hcfg |= HCFG_DESCDMA;
3752 dwc2_writel(hcfg, hsotg->regs + HCFG);
3753 hsotg->new_connection = false;
3757 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3758 *(__le32 *)buf = cpu_to_le32(port_status);
3762 dev_dbg(hsotg->dev, "SetHubFeature\n");
3763 /* No HUB features supported */
3766 case SetPortFeature:
3767 dev_dbg(hsotg->dev, "SetPortFeature\n");
3768 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3771 if (!hsotg->flags.b.port_connect_status) {
3773 * The port is disconnected, which means the core is
3774 * either in device mode or it soon will be. Just
3775 * return without doing anything since the port
3776 * register can't be written if the core is in device
3783 case USB_PORT_FEAT_SUSPEND:
3785 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3786 if (windex != hsotg->otg_port)
3788 dwc2_port_suspend(hsotg, windex);
3791 case USB_PORT_FEAT_POWER:
3793 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3794 hprt0 = dwc2_read_hprt0(hsotg);
3796 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3799 case USB_PORT_FEAT_RESET:
3800 hprt0 = dwc2_read_hprt0(hsotg);
3802 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3803 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3804 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3805 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3806 /* ??? Original driver does this */
3807 dwc2_writel(0, hsotg->regs + PCGCTL);
3809 hprt0 = dwc2_read_hprt0(hsotg);
3810 /* Clear suspend bit if resetting from suspend state */
3811 hprt0 &= ~HPRT0_SUSP;
3814 * When B-Host the Port reset bit is set in the Start
3815 * HCD Callback function, so that the reset is started
3816 * within 1ms of the HNP success interrupt
3818 if (!dwc2_hcd_is_b_host(hsotg)) {
3819 hprt0 |= HPRT0_PWR | HPRT0_RST;
3821 "In host mode, hprt0=%08x\n", hprt0);
3822 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3825 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3827 hprt0 &= ~HPRT0_RST;
3828 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3829 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3832 case USB_PORT_FEAT_INDICATOR:
3834 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3838 case USB_PORT_FEAT_TEST:
3839 hprt0 = dwc2_read_hprt0(hsotg);
3841 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3842 hprt0 &= ~HPRT0_TSTCTL_MASK;
3843 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3844 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3850 "SetPortFeature %1xh unknown or unsupported\n",
3860 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3861 typereq, windex, wvalue);
3868 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3875 retval = (hsotg->flags.b.port_connect_status_change ||
3876 hsotg->flags.b.port_reset_change ||
3877 hsotg->flags.b.port_enable_change ||
3878 hsotg->flags.b.port_suspend_change ||
3879 hsotg->flags.b.port_over_current_change);
3883 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3884 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3885 hsotg->flags.b.port_connect_status_change);
3886 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3887 hsotg->flags.b.port_reset_change);
3888 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3889 hsotg->flags.b.port_enable_change);
3890 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3891 hsotg->flags.b.port_suspend_change);
3892 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3893 hsotg->flags.b.port_over_current_change);
3899 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3901 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3903 #ifdef DWC2_DEBUG_SOF
3904 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3905 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3907 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3910 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3912 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3913 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3914 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3915 unsigned int us_per_frame;
3916 unsigned int frame_number;
3917 unsigned int remaining;
3918 unsigned int interval;
3919 unsigned int phy_clks;
3921 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3922 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3924 /* Extract fields */
3925 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3926 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3927 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3930 * Number of phy clocks since the last tick of the frame number after
3933 phy_clks = (interval - remaining) +
3934 DIV_ROUND_UP(interval * us, us_per_frame);
3936 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3939 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3941 return hsotg->op_state == OTG_STATE_B_HOST;
3944 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3948 struct dwc2_hcd_urb *urb;
3949 u32 size = sizeof(*urb) + iso_desc_count *
3950 sizeof(struct dwc2_hcd_iso_packet_desc);
3952 urb = kzalloc(size, mem_flags);
3954 urb->packet_count = iso_desc_count;
3958 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3959 struct dwc2_hcd_urb *urb, u8 dev_addr,
3960 u8 ep_num, u8 ep_type, u8 ep_dir,
3961 u16 maxp, u16 maxp_mult)
3964 ep_type == USB_ENDPOINT_XFER_BULK ||
3965 ep_type == USB_ENDPOINT_XFER_CONTROL)
3966 dev_vdbg(hsotg->dev,
3967 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n",
3968 dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult);
3969 urb->pipe_info.dev_addr = dev_addr;
3970 urb->pipe_info.ep_num = ep_num;
3971 urb->pipe_info.pipe_type = ep_type;
3972 urb->pipe_info.pipe_dir = ep_dir;
3973 urb->pipe_info.maxp = maxp;
3974 urb->pipe_info.maxp_mult = maxp_mult;
3978 * NOTE: This function will be removed once the peripheral controller code
3979 * is integrated and the driver is stable
3981 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3984 struct dwc2_host_chan *chan;
3985 struct dwc2_hcd_urb *urb;
3986 struct dwc2_qtd *qtd;
3992 num_channels = hsotg->params.host_channels;
3993 dev_dbg(hsotg->dev, "\n");
3995 "************************************************************\n");
3996 dev_dbg(hsotg->dev, "HCD State:\n");
3997 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3999 for (i = 0; i < num_channels; i++) {
4000 chan = hsotg->hc_ptr_array[i];
4001 dev_dbg(hsotg->dev, " Channel %d:\n", i);
4003 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
4004 chan->dev_addr, chan->ep_num, chan->ep_is_in);
4005 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
4006 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
4007 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
4008 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
4009 chan->data_pid_start);
4010 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
4011 dev_dbg(hsotg->dev, " xfer_started: %d\n",
4012 chan->xfer_started);
4013 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
4014 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
4015 (unsigned long)chan->xfer_dma);
4016 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
4017 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
4018 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
4019 chan->halt_on_queue);
4020 dev_dbg(hsotg->dev, " halt_pending: %d\n",
4021 chan->halt_pending);
4022 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
4023 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
4024 dev_dbg(hsotg->dev, " complete_split: %d\n",
4025 chan->complete_split);
4026 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
4027 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
4028 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
4029 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
4030 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
4032 if (chan->xfer_started) {
4033 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4035 hfnum = dwc2_readl(hsotg->regs + HFNUM);
4036 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
4037 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
4038 hcint = dwc2_readl(hsotg->regs + HCINT(i));
4039 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
4040 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4041 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4042 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4043 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4044 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4047 if (!(chan->xfer_started && chan->qh))
4050 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4051 if (!qtd->in_process)
4054 dev_dbg(hsotg->dev, " URB Info:\n");
4055 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4059 " Dev: %d, EP: %d %s\n",
4060 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4061 dwc2_hcd_get_ep_num(&urb->pipe_info),
4062 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4065 " Max packet size: %d (%d mult)\n",
4066 dwc2_hcd_get_maxp(&urb->pipe_info),
4067 dwc2_hcd_get_maxp_mult(&urb->pipe_info));
4069 " transfer_buffer: %p\n",
4072 " transfer_dma: %08lx\n",
4073 (unsigned long)urb->dma);
4075 " transfer_buffer_length: %d\n",
4077 dev_dbg(hsotg->dev, " actual_length: %d\n",
4078 urb->actual_length);
4083 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4084 hsotg->non_periodic_channels);
4085 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4086 hsotg->periodic_channels);
4087 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4088 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
4089 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4090 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4091 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4092 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4093 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4094 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4095 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4096 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4097 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4098 dwc2_hcd_dump_frrem(hsotg);
4099 dwc2_dump_global_registers(hsotg);
4100 dwc2_dump_host_registers(hsotg);
4102 "************************************************************\n");
4103 dev_dbg(hsotg->dev, "\n");
4108 * NOTE: This function will be removed once the peripheral controller code
4109 * is integrated and the driver is stable
4111 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
4113 #ifdef DWC2_DUMP_FRREM
4114 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
4115 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4116 hsotg->frrem_samples, hsotg->frrem_accum,
4117 hsotg->frrem_samples > 0 ?
4118 hsotg->frrem_accum / hsotg->frrem_samples : 0);
4119 dev_dbg(hsotg->dev, "\n");
4120 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
4121 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4122 hsotg->hfnum_7_samples,
4123 hsotg->hfnum_7_frrem_accum,
4124 hsotg->hfnum_7_samples > 0 ?
4125 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
4126 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
4127 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4128 hsotg->hfnum_0_samples,
4129 hsotg->hfnum_0_frrem_accum,
4130 hsotg->hfnum_0_samples > 0 ?
4131 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
4132 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
4133 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4134 hsotg->hfnum_other_samples,
4135 hsotg->hfnum_other_frrem_accum,
4136 hsotg->hfnum_other_samples > 0 ?
4137 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4139 dev_dbg(hsotg->dev, "\n");
4140 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4141 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4142 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4143 hsotg->hfnum_7_samples_a > 0 ?
4144 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4145 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4146 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4147 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4148 hsotg->hfnum_0_samples_a > 0 ?
4149 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4150 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4151 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4152 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4153 hsotg->hfnum_other_samples_a > 0 ?
4154 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4156 dev_dbg(hsotg->dev, "\n");
4157 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4158 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4159 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4160 hsotg->hfnum_7_samples_b > 0 ?
4161 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4162 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4163 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4164 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4165 (hsotg->hfnum_0_samples_b > 0) ?
4166 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4167 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4168 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4169 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4170 (hsotg->hfnum_other_samples_b > 0) ?
4171 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4176 struct wrapper_priv_data {
4177 struct dwc2_hsotg *hsotg;
4180 /* Gets the dwc2_hsotg from a usb_hcd */
4181 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4183 struct wrapper_priv_data *p;
4185 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4190 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4192 * This will get the dwc2_tt structure (and ttport) associated with the given
4193 * context (which is really just a struct urb pointer).
4195 * The first time this is called for a given TT we allocate memory for our
4196 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4197 * then the refcount for the structure will go to 0 and we'll free it.
4199 * @hsotg: The HCD state structure for the DWC OTG controller.
4200 * @qh: The QH structure.
4201 * @context: The priv pointer from a struct dwc2_hcd_urb.
4202 * @mem_flags: Flags for allocating memory.
4203 * @ttport: We'll return this device's port number here. That's used to
4204 * reference into the bitmap if we're on a multi_tt hub.
4206 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4207 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4210 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4211 gfp_t mem_flags, int *ttport)
4213 struct urb *urb = context;
4214 struct dwc2_tt *dwc_tt = NULL;
4217 *ttport = urb->dev->ttport;
4219 dwc_tt = urb->dev->tt->hcpriv;
4224 * For single_tt we need one schedule. For multi_tt
4225 * we need one per port.
4227 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4228 sizeof(dwc_tt->periodic_bitmaps[0]);
4229 if (urb->dev->tt->multi)
4230 bitmap_size *= urb->dev->tt->hub->maxchild;
4232 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4237 dwc_tt->usb_tt = urb->dev->tt;
4238 dwc_tt->usb_tt->hcpriv = dwc_tt;
4248 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4250 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4251 * of the structure are done.
4253 * It's OK to call this with NULL.
4255 * @hsotg: The HCD state structure for the DWC OTG controller.
4256 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4258 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4260 /* Model kfree and make put of NULL a no-op */
4264 WARN_ON(dwc_tt->refcount < 1);
4267 if (!dwc_tt->refcount) {
4268 dwc_tt->usb_tt->hcpriv = NULL;
4273 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4275 struct urb *urb = context;
4277 return urb->dev->speed;
4280 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4283 struct usb_bus *bus = hcd_to_bus(hcd);
4286 bus->bandwidth_allocated += bw / urb->interval;
4287 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4288 bus->bandwidth_isoc_reqs++;
4290 bus->bandwidth_int_reqs++;
4293 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4296 struct usb_bus *bus = hcd_to_bus(hcd);
4299 bus->bandwidth_allocated -= bw / urb->interval;
4300 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4301 bus->bandwidth_isoc_reqs--;
4303 bus->bandwidth_int_reqs--;
4307 * Sets the final status of an URB and returns it to the upper layer. Any
4308 * required cleanup of the URB is performed.
4310 * Must be called with interrupt disabled and spinlock held
4312 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4319 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4324 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4328 urb = qtd->urb->priv;
4330 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4334 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4337 dev_vdbg(hsotg->dev,
4338 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4339 __func__, urb, usb_pipedevice(urb->pipe),
4340 usb_pipeendpoint(urb->pipe),
4341 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4342 urb->actual_length);
4344 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4345 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4346 for (i = 0; i < urb->number_of_packets; ++i) {
4347 urb->iso_frame_desc[i].actual_length =
4348 dwc2_hcd_urb_get_iso_desc_actual_length(
4350 urb->iso_frame_desc[i].status =
4351 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4355 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4356 for (i = 0; i < urb->number_of_packets; i++)
4357 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4358 i, urb->iso_frame_desc[i].status);
4361 urb->status = status;
4363 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4364 urb->actual_length < urb->transfer_buffer_length)
4365 urb->status = -EREMOTEIO;
4368 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4369 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4370 struct usb_host_endpoint *ep = urb->ep;
4373 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4374 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4378 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4383 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4387 * Work queue function for starting the HCD when A-Cable is connected
4389 static void dwc2_hcd_start_func(struct work_struct *work)
4391 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4394 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4395 dwc2_host_start(hsotg);
4399 * Reset work queue function
4401 static void dwc2_hcd_reset_func(struct work_struct *work)
4403 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4405 unsigned long flags;
4408 dev_dbg(hsotg->dev, "USB RESET function called\n");
4410 spin_lock_irqsave(&hsotg->lock, flags);
4412 hprt0 = dwc2_read_hprt0(hsotg);
4413 hprt0 &= ~HPRT0_RST;
4414 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4415 hsotg->flags.b.port_reset_change = 1;
4417 spin_unlock_irqrestore(&hsotg->lock, flags);
4421 * =========================================================================
4422 * Linux HC Driver Functions
4423 * =========================================================================
4427 * Initializes the DWC_otg controller and its root hub and prepares it for host
4428 * mode operation. Activates the root port. Returns 0 on success and a negative
4429 * error code on failure.
4431 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4433 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4434 struct usb_bus *bus = hcd_to_bus(hcd);
4435 unsigned long flags;
4437 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4439 spin_lock_irqsave(&hsotg->lock, flags);
4440 hsotg->lx_state = DWC2_L0;
4441 hcd->state = HC_STATE_RUNNING;
4442 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4444 if (dwc2_is_device_mode(hsotg)) {
4445 spin_unlock_irqrestore(&hsotg->lock, flags);
4446 return 0; /* why 0 ?? */
4449 dwc2_hcd_reinit(hsotg);
4451 /* Initialize and connect root hub if one is not already attached */
4452 if (bus->root_hub) {
4453 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4454 /* Inform the HUB driver to resume */
4455 usb_hcd_resume_root_hub(hcd);
4458 spin_unlock_irqrestore(&hsotg->lock, flags);
4463 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4466 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4468 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4469 unsigned long flags;
4471 /* Turn off all host-specific interrupts */
4472 dwc2_disable_host_interrupts(hsotg);
4474 /* Wait for interrupt processing to finish */
4475 synchronize_irq(hcd->irq);
4477 spin_lock_irqsave(&hsotg->lock, flags);
4478 /* Ensure hcd is disconnected */
4479 dwc2_hcd_disconnect(hsotg, true);
4480 dwc2_hcd_stop(hsotg);
4481 hsotg->lx_state = DWC2_L3;
4482 hcd->state = HC_STATE_HALT;
4483 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4484 spin_unlock_irqrestore(&hsotg->lock, flags);
4486 usleep_range(1000, 3000);
4489 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4491 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4492 unsigned long flags;
4496 spin_lock_irqsave(&hsotg->lock, flags);
4498 if (dwc2_is_device_mode(hsotg))
4501 if (hsotg->lx_state != DWC2_L0)
4504 if (!HCD_HW_ACCESSIBLE(hcd))
4507 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4510 if (!hsotg->params.hibernation)
4511 goto skip_power_saving;
4514 * Drive USB suspend and disable port Power
4515 * if usb bus is not suspended.
4517 if (!hsotg->bus_suspended) {
4518 hprt0 = dwc2_read_hprt0(hsotg);
4519 hprt0 |= HPRT0_SUSP;
4520 hprt0 &= ~HPRT0_PWR;
4521 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4524 /* Enter hibernation */
4525 ret = dwc2_enter_hibernation(hsotg);
4527 if (ret != -ENOTSUPP)
4529 "enter hibernation failed\n");
4530 goto skip_power_saving;
4533 /* Ask phy to be suspended */
4534 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4535 spin_unlock_irqrestore(&hsotg->lock, flags);
4536 usb_phy_set_suspend(hsotg->uphy, true);
4537 spin_lock_irqsave(&hsotg->lock, flags);
4540 /* After entering hibernation, hardware is no more accessible */
4541 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4544 hsotg->lx_state = DWC2_L2;
4546 spin_unlock_irqrestore(&hsotg->lock, flags);
4551 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4553 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4554 unsigned long flags;
4557 spin_lock_irqsave(&hsotg->lock, flags);
4559 if (dwc2_is_device_mode(hsotg))
4562 if (hsotg->lx_state != DWC2_L2)
4565 if (!hsotg->params.hibernation) {
4566 hsotg->lx_state = DWC2_L0;
4571 * Set HW accessible bit before powering on the controller
4572 * since an interrupt may rise.
4574 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4577 * Enable power if not already done.
4578 * This must not be spinlocked since duration
4579 * of this call is unknown.
4581 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4582 spin_unlock_irqrestore(&hsotg->lock, flags);
4583 usb_phy_set_suspend(hsotg->uphy, false);
4584 spin_lock_irqsave(&hsotg->lock, flags);
4587 /* Exit hibernation */
4588 ret = dwc2_exit_hibernation(hsotg, true);
4589 if (ret && (ret != -ENOTSUPP))
4590 dev_err(hsotg->dev, "exit hibernation failed\n");
4592 hsotg->lx_state = DWC2_L0;
4594 spin_unlock_irqrestore(&hsotg->lock, flags);
4596 if (hsotg->bus_suspended) {
4597 spin_lock_irqsave(&hsotg->lock, flags);
4598 hsotg->flags.b.port_suspend_change = 1;
4599 spin_unlock_irqrestore(&hsotg->lock, flags);
4600 dwc2_port_resume(hsotg);
4602 /* Wait for controller to correctly update D+/D- level */
4603 usleep_range(3000, 5000);
4606 * Clear Port Enable and Port Status changes.
4607 * Enable Port Power.
4609 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4610 HPRT0_ENACHG, hsotg->regs + HPRT0);
4611 /* Wait for controller to detect Port Connect */
4612 usleep_range(5000, 7000);
4617 spin_unlock_irqrestore(&hsotg->lock, flags);
4622 /* Returns the current frame number */
4623 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4625 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4627 return dwc2_hcd_get_frame_number(hsotg);
4630 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4633 #ifdef VERBOSE_DEBUG
4634 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4635 char *pipetype = NULL;
4638 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4639 dev_vdbg(hsotg->dev, " Device address: %d\n",
4640 usb_pipedevice(urb->pipe));
4641 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4642 usb_pipeendpoint(urb->pipe),
4643 usb_pipein(urb->pipe) ? "IN" : "OUT");
4645 switch (usb_pipetype(urb->pipe)) {
4647 pipetype = "CONTROL";
4652 case PIPE_INTERRUPT:
4653 pipetype = "INTERRUPT";
4655 case PIPE_ISOCHRONOUS:
4656 pipetype = "ISOCHRONOUS";
4660 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4661 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4664 switch (urb->dev->speed) {
4665 case USB_SPEED_HIGH:
4668 case USB_SPEED_FULL:
4679 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4680 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
4681 usb_endpoint_maxp(&urb->ep->desc),
4682 usb_endpoint_maxp_mult(&urb->ep->desc));
4684 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4685 urb->transfer_buffer_length);
4686 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4687 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4688 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4689 urb->setup_packet, (unsigned long)urb->setup_dma);
4690 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4692 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4695 for (i = 0; i < urb->number_of_packets; i++) {
4696 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4697 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4698 urb->iso_frame_desc[i].offset,
4699 urb->iso_frame_desc[i].length);
4706 * Starts processing a USB transfer request specified by a USB Request Block
4707 * (URB). mem_flags indicates the type of memory allocation to use while
4708 * processing this URB.
4710 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4713 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4714 struct usb_host_endpoint *ep = urb->ep;
4715 struct dwc2_hcd_urb *dwc2_urb;
4718 int alloc_bandwidth = 0;
4722 unsigned long flags;
4724 bool qh_allocated = false;
4725 struct dwc2_qtd *qtd;
4728 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4729 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4735 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4736 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4737 spin_lock_irqsave(&hsotg->lock, flags);
4738 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4739 alloc_bandwidth = 1;
4740 spin_unlock_irqrestore(&hsotg->lock, flags);
4743 switch (usb_pipetype(urb->pipe)) {
4745 ep_type = USB_ENDPOINT_XFER_CONTROL;
4747 case PIPE_ISOCHRONOUS:
4748 ep_type = USB_ENDPOINT_XFER_ISOC;
4751 ep_type = USB_ENDPOINT_XFER_BULK;
4753 case PIPE_INTERRUPT:
4754 ep_type = USB_ENDPOINT_XFER_INT;
4758 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4763 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4764 usb_pipeendpoint(urb->pipe), ep_type,
4765 usb_pipein(urb->pipe),
4766 usb_endpoint_maxp(&ep->desc),
4767 usb_endpoint_maxp_mult(&ep->desc));
4769 buf = urb->transfer_buffer;
4771 if (hcd->self.uses_dma) {
4772 if (!buf && (urb->transfer_dma & 3)) {
4774 "%s: unaligned transfer with no transfer_buffer",
4781 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4782 tflags |= URB_GIVEBACK_ASAP;
4783 if (urb->transfer_flags & URB_ZERO_PACKET)
4784 tflags |= URB_SEND_ZERO_PACKET;
4786 dwc2_urb->priv = urb;
4787 dwc2_urb->buf = buf;
4788 dwc2_urb->dma = urb->transfer_dma;
4789 dwc2_urb->length = urb->transfer_buffer_length;
4790 dwc2_urb->setup_packet = urb->setup_packet;
4791 dwc2_urb->setup_dma = urb->setup_dma;
4792 dwc2_urb->flags = tflags;
4793 dwc2_urb->interval = urb->interval;
4794 dwc2_urb->status = -EINPROGRESS;
4796 for (i = 0; i < urb->number_of_packets; ++i)
4797 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4798 urb->iso_frame_desc[i].offset,
4799 urb->iso_frame_desc[i].length);
4801 urb->hcpriv = dwc2_urb;
4802 qh = (struct dwc2_qh *)ep->hcpriv;
4803 /* Create QH for the endpoint if it doesn't exist */
4805 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4811 qh_allocated = true;
4814 qtd = kzalloc(sizeof(*qtd), mem_flags);
4820 spin_lock_irqsave(&hsotg->lock, flags);
4821 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4825 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4829 if (alloc_bandwidth) {
4830 dwc2_allocate_bus_bandwidth(hcd,
4831 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4835 spin_unlock_irqrestore(&hsotg->lock, flags);
4840 dwc2_urb->priv = NULL;
4841 usb_hcd_unlink_urb_from_ep(hcd, urb);
4842 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4843 qh->channel->qh = NULL;
4845 spin_unlock_irqrestore(&hsotg->lock, flags);
4851 struct dwc2_qtd *qtd2, *qtd2_tmp;
4854 dwc2_hcd_qh_unlink(hsotg, qh);
4855 /* Free each QTD in the QH's QTD list */
4856 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4858 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4859 dwc2_hcd_qh_free(hsotg, qh);
4868 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4870 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4873 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4875 unsigned long flags;
4877 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4878 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4880 spin_lock_irqsave(&hsotg->lock, flags);
4882 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4887 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4891 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4893 usb_hcd_unlink_urb_from_ep(hcd, urb);
4898 /* Higher layer software sets URB status */
4899 spin_unlock(&hsotg->lock);
4900 usb_hcd_giveback_urb(hcd, urb, status);
4901 spin_lock(&hsotg->lock);
4903 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4904 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4906 spin_unlock_irqrestore(&hsotg->lock, flags);
4912 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4913 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4914 * must already be dequeued.
4916 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4917 struct usb_host_endpoint *ep)
4919 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4922 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4923 ep->desc.bEndpointAddress, ep->hcpriv);
4924 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4928 * Resets endpoint specific parameter values, in current version used to reset
4929 * the data toggle (as a WA). This function can be called from usb_clear_halt
4932 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4933 struct usb_host_endpoint *ep)
4935 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4936 unsigned long flags;
4939 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4940 ep->desc.bEndpointAddress);
4942 spin_lock_irqsave(&hsotg->lock, flags);
4943 dwc2_hcd_endpoint_reset(hsotg, ep);
4944 spin_unlock_irqrestore(&hsotg->lock, flags);
4948 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4949 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4952 * This function is called by the USB core when an interrupt occurs
4954 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4956 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4958 return dwc2_handle_hcd_intr(hsotg);
4962 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4963 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4964 * is the status change indicator for the single root port. Returns 1 if either
4965 * change indicator is 1, otherwise returns 0.
4967 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4969 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4971 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4975 /* Handles hub class-specific requests */
4976 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4977 u16 windex, char *buf, u16 wlength)
4979 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4980 wvalue, windex, buf, wlength);
4984 /* Handles hub TT buffer clear completions */
4985 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4986 struct usb_host_endpoint *ep)
4988 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4990 unsigned long flags;
4996 spin_lock_irqsave(&hsotg->lock, flags);
4997 qh->tt_buffer_dirty = 0;
4999 if (hsotg->flags.b.port_connect_status)
5000 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
5002 spin_unlock_irqrestore(&hsotg->lock, flags);
5006 * HPRT0_SPD_HIGH_SPEED: high speed
5007 * HPRT0_SPD_FULL_SPEED: full speed
5009 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
5011 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5013 if (hsotg->params.speed == speed)
5016 hsotg->params.speed = speed;
5017 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
5020 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
5022 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5024 if (!hsotg->params.change_speed_quirk)
5028 * On removal, set speed to default high-speed.
5030 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
5031 udev->parent->speed < USB_SPEED_HIGH) {
5032 dev_info(hsotg->dev, "Set speed to default high-speed\n");
5033 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5037 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5039 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5041 if (!hsotg->params.change_speed_quirk)
5044 if (udev->speed == USB_SPEED_HIGH) {
5045 dev_info(hsotg->dev, "Set speed to high-speed\n");
5046 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5047 } else if ((udev->speed == USB_SPEED_FULL ||
5048 udev->speed == USB_SPEED_LOW)) {
5050 * Change speed setting to full-speed if there's
5051 * a full-speed or low-speed device plugged in.
5053 dev_info(hsotg->dev, "Set speed to full-speed\n");
5054 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5060 static struct hc_driver dwc2_hc_driver = {
5061 .description = "dwc2_hsotg",
5062 .product_desc = "DWC OTG Controller",
5063 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5065 .irq = _dwc2_hcd_irq,
5066 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5068 .start = _dwc2_hcd_start,
5069 .stop = _dwc2_hcd_stop,
5070 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5071 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5072 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5073 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5074 .get_frame_number = _dwc2_hcd_get_frame_number,
5076 .hub_status_data = _dwc2_hcd_hub_status_data,
5077 .hub_control = _dwc2_hcd_hub_control,
5078 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5080 .bus_suspend = _dwc2_hcd_suspend,
5081 .bus_resume = _dwc2_hcd_resume,
5083 .map_urb_for_dma = dwc2_map_urb_for_dma,
5084 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5088 * Frees secondary storage associated with the dwc2_hsotg structure contained
5089 * in the struct usb_hcd field
5091 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5097 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5099 /* Free memory for QH/QTD lists */
5100 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5101 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5102 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5103 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5104 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5105 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5107 /* Free memory for the host channels */
5108 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5109 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5112 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5114 hsotg->hc_ptr_array[i] = NULL;
5119 if (hsotg->params.host_dma) {
5120 if (hsotg->status_buf) {
5121 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5123 hsotg->status_buf_dma);
5124 hsotg->status_buf = NULL;
5127 kfree(hsotg->status_buf);
5128 hsotg->status_buf = NULL;
5131 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5133 /* Disable all interrupts */
5134 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5135 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5136 dwc2_writel(0, hsotg->regs + GINTMSK);
5138 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5139 dctl = dwc2_readl(hsotg->regs + DCTL);
5140 dctl |= DCTL_SFTDISCON;
5141 dwc2_writel(dctl, hsotg->regs + DCTL);
5144 if (hsotg->wq_otg) {
5145 if (!cancel_work_sync(&hsotg->wf_otg))
5146 flush_workqueue(hsotg->wq_otg);
5147 destroy_workqueue(hsotg->wq_otg);
5150 del_timer(&hsotg->wkp_timer);
5153 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5155 /* Turn off all host-specific interrupts */
5156 dwc2_disable_host_interrupts(hsotg);
5158 dwc2_hcd_free(hsotg);
5162 * Initializes the HCD. This function allocates memory for and initializes the
5163 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5164 * USB bus with the core and calls the hc_driver->start() function. It returns
5165 * a negative error on failure.
5167 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5169 struct platform_device *pdev = to_platform_device(hsotg->dev);
5170 struct resource *res;
5171 struct usb_hcd *hcd;
5172 struct dwc2_host_chan *channel;
5174 int i, num_channels;
5180 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5184 hcfg = dwc2_readl(hsotg->regs + HCFG);
5185 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5187 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5188 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5189 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5190 if (!hsotg->frame_num_array)
5192 hsotg->last_frame_num_array = kzalloc(
5193 sizeof(*hsotg->last_frame_num_array) *
5194 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5195 if (!hsotg->last_frame_num_array)
5198 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5200 /* Check if the bus driver or platform code has setup a dma_mask */
5201 if (hsotg->params.host_dma &&
5202 !hsotg->dev->dma_mask) {
5203 dev_warn(hsotg->dev,
5204 "dma_mask not set, disabling DMA\n");
5205 hsotg->params.host_dma = false;
5206 hsotg->params.dma_desc_enable = false;
5209 /* Set device flags indicating whether the HCD supports DMA */
5210 if (hsotg->params.host_dma) {
5211 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5212 dev_warn(hsotg->dev, "can't set DMA mask\n");
5213 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5214 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5217 if (hsotg->params.change_speed_quirk) {
5218 dwc2_hc_driver.free_dev = dwc2_free_dev;
5219 dwc2_hc_driver.reset_device = dwc2_reset_device;
5222 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5226 if (!hsotg->params.host_dma)
5227 hcd->self.uses_dma = 0;
5231 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5236 hcd->rsrc_start = res->start;
5237 hcd->rsrc_len = resource_size(res);
5239 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5243 * Disable the global interrupt until all the interrupt handlers are
5246 dwc2_disable_global_interrupts(hsotg);
5248 /* Initialize the DWC_otg core, and select the Phy type */
5249 retval = dwc2_core_init(hsotg, true);
5253 /* Create new workqueue and init work */
5255 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5256 if (!hsotg->wq_otg) {
5257 dev_err(hsotg->dev, "Failed to create workqueue\n");
5260 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5262 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5263 (unsigned long)hsotg);
5265 /* Initialize the non-periodic schedule */
5266 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5267 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5269 /* Initialize the periodic schedule */
5270 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5271 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5272 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5273 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5275 INIT_LIST_HEAD(&hsotg->split_order);
5278 * Create a host channel descriptor for each host channel implemented
5279 * in the controller. Initialize the channel descriptor array.
5281 INIT_LIST_HEAD(&hsotg->free_hc_list);
5282 num_channels = hsotg->params.host_channels;
5283 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5285 for (i = 0; i < num_channels; i++) {
5286 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5289 channel->hc_num = i;
5290 INIT_LIST_HEAD(&channel->split_order_list_entry);
5291 hsotg->hc_ptr_array[i] = channel;
5294 /* Initialize hsotg start work */
5295 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5297 /* Initialize port reset work */
5298 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5301 * Allocate space for storing data on status transactions. Normally no
5302 * data is sent, but this space acts as a bit bucket. This must be
5303 * done after usb_add_hcd since that function allocates the DMA buffer
5306 if (hsotg->params.host_dma)
5307 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5308 DWC2_HCD_STATUS_BUF_SIZE,
5309 &hsotg->status_buf_dma, GFP_KERNEL);
5311 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5314 if (!hsotg->status_buf)
5318 * Create kmem caches to handle descriptor buffers in descriptor
5320 * Alignment must be set to 512 bytes.
5322 if (hsotg->params.dma_desc_enable ||
5323 hsotg->params.dma_desc_fs_enable) {
5324 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5325 sizeof(struct dwc2_dma_desc) *
5326 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5328 if (!hsotg->desc_gen_cache) {
5330 "unable to create dwc2 generic desc cache\n");
5333 * Disable descriptor dma mode since it will not be
5336 hsotg->params.dma_desc_enable = false;
5337 hsotg->params.dma_desc_fs_enable = false;
5340 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5341 sizeof(struct dwc2_dma_desc) *
5342 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5343 if (!hsotg->desc_hsisoc_cache) {
5345 "unable to create dwc2 hs isoc desc cache\n");
5347 kmem_cache_destroy(hsotg->desc_gen_cache);
5350 * Disable descriptor dma mode since it will not be
5353 hsotg->params.dma_desc_enable = false;
5354 hsotg->params.dma_desc_fs_enable = false;
5358 if (hsotg->params.host_dma) {
5360 * Create kmem caches to handle non-aligned buffer
5361 * in Buffer DMA mode.
5363 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5364 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5365 SLAB_CACHE_DMA, NULL);
5366 if (!hsotg->unaligned_cache)
5368 "unable to create dwc2 unaligned cache\n");
5371 hsotg->otg_port = 1;
5372 hsotg->frame_list = NULL;
5373 hsotg->frame_list_dma = 0;
5374 hsotg->periodic_qh_count = 0;
5376 /* Initiate lx_state to L3 disconnected state */
5377 hsotg->lx_state = DWC2_L3;
5379 hcd->self.otg_port = hsotg->otg_port;
5381 /* Don't support SG list at this point */
5382 hcd->self.sg_tablesize = 0;
5384 if (!IS_ERR_OR_NULL(hsotg->uphy))
5385 otg_set_host(hsotg->uphy->otg, &hcd->self);
5388 * Finish generic HCD initialization and start the HCD. This function
5389 * allocates the DMA buffer pool, registers the USB bus, requests the
5390 * IRQ line, and calls hcd_start method.
5392 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5396 device_wakeup_enable(hcd->self.controller);
5398 dwc2_hcd_dump_state(hsotg);
5400 dwc2_enable_global_interrupts(hsotg);
5405 kmem_cache_destroy(hsotg->unaligned_cache);
5406 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5407 kmem_cache_destroy(hsotg->desc_gen_cache);
5409 dwc2_hcd_release(hsotg);
5414 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5415 kfree(hsotg->last_frame_num_array);
5416 kfree(hsotg->frame_num_array);
5419 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5425 * Frees memory and resources associated with the HCD and deregisters the bus.
5427 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5429 struct usb_hcd *hcd;
5431 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5433 hcd = dwc2_hsotg_to_hcd(hsotg);
5434 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5437 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5442 if (!IS_ERR_OR_NULL(hsotg->uphy))
5443 otg_set_host(hsotg->uphy->otg, NULL);
5445 usb_remove_hcd(hcd);
5448 kmem_cache_destroy(hsotg->unaligned_cache);
5449 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5450 kmem_cache_destroy(hsotg->desc_gen_cache);
5452 dwc2_hcd_release(hsotg);
5455 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5456 kfree(hsotg->last_frame_num_array);
5457 kfree(hsotg->frame_num_array);
5462 * dwc2_backup_host_registers() - Backup controller host registers.
5463 * When suspending usb bus, registers needs to be backuped
5464 * if controller power is disabled once suspended.
5466 * @hsotg: Programming view of the DWC_otg controller
5468 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5470 struct dwc2_hregs_backup *hr;
5473 dev_dbg(hsotg->dev, "%s\n", __func__);
5475 /* Backup Host regs */
5476 hr = &hsotg->hr_backup;
5477 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5478 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5479 for (i = 0; i < hsotg->params.host_channels; ++i)
5480 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5482 hr->hprt0 = dwc2_read_hprt0(hsotg);
5483 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5490 * dwc2_restore_host_registers() - Restore controller host registers.
5491 * When resuming usb bus, device registers needs to be restored
5492 * if controller power were disabled.
5494 * @hsotg: Programming view of the DWC_otg controller
5496 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5498 struct dwc2_hregs_backup *hr;
5501 dev_dbg(hsotg->dev, "%s\n", __func__);
5503 /* Restore host regs */
5504 hr = &hsotg->hr_backup;
5506 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5512 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5513 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5515 for (i = 0; i < hsotg->params.host_channels; ++i)
5516 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5518 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5519 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5520 hsotg->frame_number = 0;