2 * Copyright © 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/types.h>
22 #include <mach/hardware.h>
23 #include <asm/hardware/iop_adma.h>
25 /* Memory copy units */
26 #define DMA_CCR(chan) (chan->mmr_base + 0x0)
27 #define DMA_CSR(chan) (chan->mmr_base + 0x4)
28 #define DMA_DAR(chan) (chan->mmr_base + 0xc)
29 #define DMA_NDAR(chan) (chan->mmr_base + 0x10)
30 #define DMA_PADR(chan) (chan->mmr_base + 0x14)
31 #define DMA_PUADR(chan) (chan->mmr_base + 0x18)
32 #define DMA_LADR(chan) (chan->mmr_base + 0x1c)
33 #define DMA_BCR(chan) (chan->mmr_base + 0x20)
34 #define DMA_DCR(chan) (chan->mmr_base + 0x24)
36 /* Application accelerator unit */
37 #define AAU_ACR(chan) (chan->mmr_base + 0x0)
38 #define AAU_ASR(chan) (chan->mmr_base + 0x4)
39 #define AAU_ADAR(chan) (chan->mmr_base + 0x8)
40 #define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
41 #define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2)))
42 #define AAU_DAR(chan) (chan->mmr_base + 0x20)
43 #define AAU_ABCR(chan) (chan->mmr_base + 0x24)
44 #define AAU_ADCR(chan) (chan->mmr_base + 0x28)
45 #define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
46 #define AAU_EDCR0_IDX 8
47 #define AAU_EDCR1_IDX 17
48 #define AAU_EDCR2_IDX 26
54 struct iop3xx_aau_desc_ctrl {
55 unsigned int int_en:1;
56 unsigned int blk1_cmd_ctrl:3;
57 unsigned int blk2_cmd_ctrl:3;
58 unsigned int blk3_cmd_ctrl:3;
59 unsigned int blk4_cmd_ctrl:3;
60 unsigned int blk5_cmd_ctrl:3;
61 unsigned int blk6_cmd_ctrl:3;
62 unsigned int blk7_cmd_ctrl:3;
63 unsigned int blk8_cmd_ctrl:3;
64 unsigned int blk_ctrl:2;
65 unsigned int dual_xor_en:1;
66 unsigned int tx_complete:1;
67 unsigned int zero_result_err:1;
68 unsigned int zero_result_en:1;
69 unsigned int dest_write_en:1;
72 struct iop3xx_aau_e_desc_ctrl {
73 unsigned int reserved:1;
74 unsigned int blk1_cmd_ctrl:3;
75 unsigned int blk2_cmd_ctrl:3;
76 unsigned int blk3_cmd_ctrl:3;
77 unsigned int blk4_cmd_ctrl:3;
78 unsigned int blk5_cmd_ctrl:3;
79 unsigned int blk6_cmd_ctrl:3;
80 unsigned int blk7_cmd_ctrl:3;
81 unsigned int blk8_cmd_ctrl:3;
82 unsigned int reserved2:7;
85 struct iop3xx_dma_desc_ctrl {
86 unsigned int pci_transaction:4;
87 unsigned int int_en:1;
88 unsigned int dac_cycle_en:1;
89 unsigned int mem_to_mem_en:1;
90 unsigned int crc_data_tx_en:1;
91 unsigned int crc_gen_en:1;
92 unsigned int crc_seed_dis:1;
93 unsigned int reserved:21;
94 unsigned int crc_tx_complete:1;
97 struct iop3xx_desc_dma {
105 u32 upper_pci_src_addr;
106 u32 upper_pci_dest_addr;
109 u32 local_pci_src_addr;
110 u32 local_pci_dest_addr;
116 struct iop3xx_dma_desc_ctrl desc_ctrl_field;
121 struct iop3xx_desc_aau {
128 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
133 struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
137 struct iop3xx_aau_gfmr {
138 unsigned int gfmr1:8;
139 unsigned int gfmr2:8;
140 unsigned int gfmr3:8;
141 unsigned int gfmr4:8;
144 struct iop3xx_desc_pq_xor {
149 struct iop3xx_aau_gfmr data_mult1_field;
155 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
160 struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
162 struct iop3xx_aau_gfmr data_mult_field;
167 struct iop3xx_desc_dual_xor {
177 struct iop3xx_aau_desc_ctrl desc_ctrl_field;
183 struct iop3xx_desc_aau *aau;
184 struct iop3xx_desc_dma *dma;
185 struct iop3xx_desc_pq_xor *pq_xor;
186 struct iop3xx_desc_dual_xor *dual_xor;
190 /* No support for p+q operations */
192 iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op)
199 iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
206 iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
212 iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
213 dma_addr_t addr, unsigned char coef)
219 iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op)
226 iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
233 iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
238 #define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
241 iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
247 static inline int iop_adma_get_max_xor(void)
252 static inline int iop_adma_get_max_pq(void)
258 static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
260 int id = chan->device->id;
265 return __raw_readl(DMA_DAR(chan));
267 return __raw_readl(AAU_ADAR(chan));
274 static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
277 int id = chan->device->id;
282 __raw_writel(next_desc_addr, DMA_NDAR(chan));
285 __raw_writel(next_desc_addr, AAU_ANDAR(chan));
291 #define IOP_ADMA_STATUS_BUSY (1 << 10)
292 #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024)
293 #define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024)
294 #define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
296 static inline int iop_chan_is_busy(struct iop_adma_chan *chan)
298 u32 status = __raw_readl(DMA_CSR(chan));
299 return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0;
302 static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc,
305 /* num_slots will only ever be 1, 2, 4, or 8 */
306 return (desc->idx & (num_slots - 1)) ? 0 : 1;
309 /* to do: support large (i.e. > hw max) buffer sizes */
310 static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
316 /* to do: support large (i.e. > hw max) buffer sizes */
317 static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
323 static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
326 static const char slot_count_table[] = {
327 1, 1, 1, 1, /* 01 - 04 */
328 2, 2, 2, 2, /* 05 - 08 */
329 4, 4, 4, 4, /* 09 - 12 */
330 4, 4, 4, 4, /* 13 - 16 */
331 8, 8, 8, 8, /* 17 - 20 */
332 8, 8, 8, 8, /* 21 - 24 */
333 8, 8, 8, 8, /* 25 - 28 */
334 8, 8, 8, 8, /* 29 - 32 */
336 *slots_per_op = slot_count_table[src_cnt - 1];
337 return *slots_per_op;
341 iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)
343 switch (chan->device->id) {
346 return iop_chan_memcpy_slot_count(0, slots_per_op);
348 return iop3xx_aau_xor_slot_count(0, 2, slots_per_op);
355 static inline int iop_chan_xor_slot_count(size_t len, int src_cnt,
358 int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
360 if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT)
363 len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
364 while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) {
365 len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
366 slot_cnt += *slots_per_op;
369 slot_cnt += *slots_per_op;
374 /* zero sum on iop3xx is limited to 1k at a time so it requires multiple
377 static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
380 int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
382 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT)
385 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
386 while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
387 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
388 slot_cnt += *slots_per_op;
391 slot_cnt += *slots_per_op;
396 static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
397 struct iop_adma_chan *chan)
399 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
401 switch (chan->device->id) {
404 return hw_desc.dma->byte_count;
406 return hw_desc.aau->byte_count;
413 /* translate the src_idx to a descriptor word index */
414 static inline int __desc_idx(int src_idx)
416 static const int desc_idx_table[] = { 0, 0, 0, 0,
426 return desc_idx_table[src_idx];
429 static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
430 struct iop_adma_chan *chan,
433 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
435 switch (chan->device->id) {
438 return hw_desc.dma->src_addr;
446 return hw_desc.aau->src[src_idx];
448 return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
451 static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
452 int src_idx, dma_addr_t addr)
455 hw_desc->src[src_idx] = addr;
457 hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
461 iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
463 struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
466 struct iop3xx_dma_desc_ctrl field;
469 u_desc_ctrl.value = 0;
470 u_desc_ctrl.field.mem_to_mem_en = 1;
471 u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
472 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
473 hw_desc->desc_ctrl = u_desc_ctrl.value;
474 hw_desc->upper_pci_src_addr = 0;
475 hw_desc->crc_addr = 0;
479 iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
481 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
484 struct iop3xx_aau_desc_ctrl field;
487 u_desc_ctrl.value = 0;
488 u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
489 u_desc_ctrl.field.dest_write_en = 1;
490 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
491 hw_desc->desc_ctrl = u_desc_ctrl.value;
495 iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt,
502 struct iop3xx_aau_desc_ctrl field;
505 u_desc_ctrl.value = 0;
508 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
511 for (i = 24; i < src_cnt; i++) {
512 edcr |= (1 << shift);
515 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
519 if (!u_desc_ctrl.field.blk_ctrl) {
520 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
521 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
525 for (i = 16; i < src_cnt; i++) {
526 edcr |= (1 << shift);
529 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
533 if (!u_desc_ctrl.field.blk_ctrl)
534 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
537 for (i = 8; i < src_cnt; i++) {
538 edcr |= (1 << shift);
541 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
546 for (i = 0; i < src_cnt; i++) {
547 u_desc_ctrl.value |= (1 << shift);
551 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
552 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
555 u_desc_ctrl.field.dest_write_en = 1;
556 u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
557 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
558 hw_desc->desc_ctrl = u_desc_ctrl.value;
560 return u_desc_ctrl.value;
564 iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
567 iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);
570 /* return the number of operations */
572 iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
575 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
576 struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
579 struct iop3xx_aau_desc_ctrl field;
583 hw_desc = desc->hw_desc;
585 for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
586 i += slots_per_op, j++) {
587 iter = iop_hw_desc_slot_idx(hw_desc, i);
588 u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags);
589 u_desc_ctrl.field.dest_write_en = 0;
590 u_desc_ctrl.field.zero_result_en = 1;
591 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
592 iter->desc_ctrl = u_desc_ctrl.value;
594 /* for the subsequent descriptors preserve the store queue
595 * and chain them together
599 iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);
600 prev_hw_desc->next_desc =
601 (u32) (desc->async_tx.phys + (i << 5));
609 iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt,
612 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
615 struct iop3xx_aau_desc_ctrl field;
618 u_desc_ctrl.value = 0;
621 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
622 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
625 if (!u_desc_ctrl.field.blk_ctrl) {
626 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
627 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
629 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
632 if (!u_desc_ctrl.field.blk_ctrl)
633 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
634 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
637 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
638 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
641 u_desc_ctrl.field.dest_write_en = 0;
642 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
643 hw_desc->desc_ctrl = u_desc_ctrl.value;
646 static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
647 struct iop_adma_chan *chan,
650 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
652 switch (chan->device->id) {
655 hw_desc.dma->byte_count = byte_count;
658 hw_desc.aau->byte_count = byte_count;
666 iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
667 struct iop_adma_chan *chan)
669 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
671 switch (chan->device->id) {
674 iop_desc_init_memcpy(desc, 1);
675 hw_desc.dma->byte_count = 0;
676 hw_desc.dma->dest_addr = 0;
677 hw_desc.dma->src_addr = 0;
680 iop_desc_init_null_xor(desc, 2, 1);
681 hw_desc.aau->byte_count = 0;
682 hw_desc.aau->dest_addr = 0;
683 hw_desc.aau->src[0] = 0;
684 hw_desc.aau->src[1] = 0;
692 iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
694 int slots_per_op = desc->slots_per_op;
695 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
698 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
699 hw_desc->byte_count = len;
702 iter = iop_hw_desc_slot_idx(hw_desc, i);
703 iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
704 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
706 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
708 iter = iop_hw_desc_slot_idx(hw_desc, i);
709 iter->byte_count = len;
713 static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
714 struct iop_adma_chan *chan,
717 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
719 switch (chan->device->id) {
722 hw_desc.dma->dest_addr = addr;
725 hw_desc.aau->dest_addr = addr;
732 static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
735 struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
736 hw_desc->src_addr = addr;
740 iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
744 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
745 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
748 for (i = 0; (slot_cnt -= slots_per_op) >= 0;
749 i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
750 iter = iop_hw_desc_slot_idx(hw_desc, i);
751 iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
755 static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
756 int src_idx, dma_addr_t addr)
759 struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
760 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
763 for (i = 0; (slot_cnt -= slots_per_op) >= 0;
764 i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) {
765 iter = iop_hw_desc_slot_idx(hw_desc, i);
766 iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
770 static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
773 /* hw_desc->next_desc is the same location for all channels */
774 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
776 iop_paranoia(hw_desc.dma->next_desc);
777 hw_desc.dma->next_desc = next_desc_addr;
780 static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
782 /* hw_desc->next_desc is the same location for all channels */
783 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
784 return hw_desc.dma->next_desc;
787 static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
789 /* hw_desc->next_desc is the same location for all channels */
790 union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
791 hw_desc.dma->next_desc = 0;
794 static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
797 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
798 hw_desc->src[0] = val;
801 static inline enum sum_check_flags
802 iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
804 struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
805 struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
807 iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
808 return desc_ctrl.zero_result_err << SUM_CHECK_P;
811 static inline void iop_chan_append(struct iop_adma_chan *chan)
815 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
816 dma_chan_ctrl |= 0x2;
817 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
820 static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
822 return __raw_readl(DMA_CSR(chan));
825 static inline void iop_chan_disable(struct iop_adma_chan *chan)
827 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
829 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
832 static inline void iop_chan_enable(struct iop_adma_chan *chan)
834 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
837 __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
840 static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
842 u32 status = __raw_readl(DMA_CSR(chan));
844 __raw_writel(status, DMA_CSR(chan));
847 static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
849 u32 status = __raw_readl(DMA_CSR(chan));
851 __raw_writel(status, DMA_CSR(chan));
854 static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
856 u32 status = __raw_readl(DMA_CSR(chan));
858 switch (chan->device->id) {
861 status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1);
870 __raw_writel(status, DMA_CSR(chan));
874 iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
880 iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
886 iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
892 iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
894 return test_bit(5, &status);
898 iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
900 switch (chan->device->id) {
903 return test_bit(2, &status);
910 iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
912 switch (chan->device->id) {
915 return test_bit(3, &status);
922 iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
924 switch (chan->device->id) {
927 return test_bit(1, &status);