1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hantro VPU codec driver
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
12 #include <linux/interrupt.h>
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
18 #define DEC_8190_ALIGN_MASK 0x07U
21 #define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM)
22 #define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM)
24 #define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1)
29 struct hantro_variant;
32 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
34 * @cpu: CPU pointer to the buffer.
35 * @dma: DMA address of the buffer.
36 * @size: Size of the buffer.
37 * @attrs: Attributes of the DMA mapping.
39 struct hantro_aux_buf {
46 /* Max. number of entries in the DPB (HW limitation). */
47 #define HANTRO_H264_DPB_SIZE 16
50 * struct hantro_h264_dec_ctrls
52 * @decode: Decode params
53 * @scaling: Scaling info
57 struct hantro_h264_dec_ctrls {
58 const struct v4l2_ctrl_h264_decode_params *decode;
59 const struct v4l2_ctrl_h264_scaling_matrix *scaling;
60 const struct v4l2_ctrl_h264_sps *sps;
61 const struct v4l2_ctrl_h264_pps *pps;
65 * struct hantro_h264_dec_reflists
71 struct hantro_h264_dec_reflists {
72 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN];
73 struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN];
74 struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN];
78 * struct hantro_h264_dec_hw_ctx
80 * @priv: Private auxiliary buffer for hardware.
82 * @reflists: P/B0/B1 reflists
83 * @ctrls: V4L2 controls attached to a run
84 * @dpb_longterm: DPB long-term
85 * @dpb_valid: DPB valid
86 * @cur_poc: Current picture order count
88 struct hantro_h264_dec_hw_ctx {
89 struct hantro_aux_buf priv;
90 struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
91 struct hantro_h264_dec_reflists reflists;
92 struct hantro_h264_dec_ctrls ctrls;
99 * struct hantro_hevc_dec_ctrls
100 * @decode_params: Decode params
101 * @scaling: Scaling matrix
104 * @hevc_hdr_skip_length: the number of data (in bits) to skip in the
105 * slice segment header syntax after 'slice type'
108 struct hantro_hevc_dec_ctrls {
109 const struct v4l2_ctrl_hevc_decode_params *decode_params;
110 const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
111 const struct v4l2_ctrl_hevc_sps *sps;
112 const struct v4l2_ctrl_hevc_pps *pps;
113 u32 hevc_hdr_skip_length;
117 * struct hantro_hevc_dec_hw_ctx
118 * @tile_sizes: Tile sizes buffer
119 * @tile_filter: Tile vertical filter buffer
120 * @tile_sao: Tile SAO buffer
121 * @tile_bsd: Tile BSD control buffer
122 * @ref_bufs: Internal reference buffers
123 * @scaling_lists: Scaling lists buffer
124 * @ref_bufs_poc: Internal reference buffers picture order count
125 * @ref_bufs_used: Bitfield of used reference buffers
126 * @ctrls: V4L2 controls attached to a run
127 * @num_tile_cols_allocated: number of allocated tiles
129 struct hantro_hevc_dec_hw_ctx {
130 struct hantro_aux_buf tile_sizes;
131 struct hantro_aux_buf tile_filter;
132 struct hantro_aux_buf tile_sao;
133 struct hantro_aux_buf tile_bsd;
134 struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
135 struct hantro_aux_buf scaling_lists;
136 int ref_bufs_poc[NUM_REF_PICTURES];
138 struct hantro_hevc_dec_ctrls ctrls;
139 unsigned int num_tile_cols_allocated;
143 * struct hantro_mpeg2_dec_hw_ctx
145 * @qtable: Quantization table
147 struct hantro_mpeg2_dec_hw_ctx {
148 struct hantro_aux_buf qtable;
152 * struct hantro_vp8_dec_hw_ctx
154 * @segment_map: Segment map buffer.
155 * @prob_tbl: Probability table buffer.
157 struct hantro_vp8_dec_hw_ctx {
158 struct hantro_aux_buf segment_map;
159 struct hantro_aux_buf prob_tbl;
163 * struct hantro_vp9_frame_info
165 * @valid: frame info valid flag
166 * @frame_context_idx: index of frame context
167 * @reference_mode: inter prediction type
168 * @tx_mode: transform mode
169 * @interpolation_filter: filter selection for inter prediction
170 * @flags: frame flags
171 * @timestamp: frame timestamp
173 struct hantro_vp9_frame_info {
175 u32 frame_context_idx : 2;
176 u32 reference_mode : 2;
178 u32 interpolation_filter : 3;
183 #define MAX_SB_COLS 64
184 #define MAX_SB_ROWS 34
187 * struct hantro_vp9_dec_hw_ctx
189 * @tile_edge: auxiliary DMA buffer for tile edge processing
190 * @segment_map: auxiliary DMA buffer for segment map
191 * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters
192 * @cnts: vp9 library struct for abstracting hw counters access
193 * @probability_tables: VP9 probability tables implied by the spec
194 * @frame_context: VP9 frame contexts
195 * @cur: current frame information
196 * @last: last frame information
197 * @bsd_ctrl_offset: bsd offset into tile_edge
198 * @segment_map_size: size of segment map
199 * @ctx_counters_offset: hw counters offset into misc
200 * @tile_info_offset: tile info offset into misc
201 * @tile_r_info: per-tile information array
202 * @tile_c_info: per-tile information array
203 * @last_tile_r: last number of tile rows
204 * @last_tile_c: last number of tile cols
205 * @last_sbs_r: last number of superblock rows
206 * @last_sbs_c: last number of superblock cols
207 * @active_segment: number of active segment (alternating between 0 and 1)
208 * @feature_enabled: segmentation feature enabled flags
209 * @feature_data: segmentation feature data
211 struct hantro_vp9_dec_hw_ctx {
212 struct hantro_aux_buf tile_edge;
213 struct hantro_aux_buf segment_map;
214 struct hantro_aux_buf misc;
215 struct v4l2_vp9_frame_symbol_counts cnts;
216 struct v4l2_vp9_frame_context probability_tables;
217 struct v4l2_vp9_frame_context frame_context[4];
218 struct hantro_vp9_frame_info cur;
219 struct hantro_vp9_frame_info last;
221 unsigned int bsd_ctrl_offset;
222 unsigned int segment_map_size;
223 unsigned int ctx_counters_offset;
224 unsigned int tile_info_offset;
226 unsigned short tile_r_info[MAX_SB_ROWS];
227 unsigned short tile_c_info[MAX_SB_COLS];
228 unsigned int last_tile_r;
229 unsigned int last_tile_c;
230 unsigned int last_sbs_r;
231 unsigned int last_sbs_c;
233 unsigned int active_segment;
234 u8 feature_enabled[8];
235 s16 feature_data[8][4];
239 * struct hantro_postproc_ctx
241 * @dec_q: References buffers, in decoder format.
243 struct hantro_postproc_ctx {
244 struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
248 * struct hantro_postproc_ops - post-processor operations
250 * @enable: Enable the post-processor block. Optional.
251 * @disable: Disable the post-processor block. Optional.
252 * @enum_framesizes: Enumerate possible scaled output formats.
253 * Returns zero if OK, a negative value in error cases.
256 struct hantro_postproc_ops {
257 void (*enable)(struct hantro_ctx *ctx);
258 void (*disable)(struct hantro_ctx *ctx);
259 int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize);
263 * struct hantro_codec_ops - codec mode specific operations
265 * @init: If needed, can be used for initialization.
266 * Optional and called from process context.
267 * @exit: If needed, can be used to undo the .init phase.
268 * Optional and called from process context.
269 * @run: Start single {en,de)coding job. Called from atomic context
270 * to indicate that a pair of buffers is ready and the hardware
271 * should be programmed and started. Returns zero if OK, a
272 * negative value in error cases.
273 * @done: Read back processing results and additional data from hardware.
274 * @reset: Reset the hardware in case of a timeout.
276 struct hantro_codec_ops {
277 int (*init)(struct hantro_ctx *ctx);
278 void (*exit)(struct hantro_ctx *ctx);
279 int (*run)(struct hantro_ctx *ctx);
280 void (*done)(struct hantro_ctx *ctx);
281 void (*reset)(struct hantro_ctx *ctx);
285 * enum hantro_enc_fmt - source format ID for hardware registers.
287 * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format
288 * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format
289 * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV)
290 * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY)
292 enum hantro_enc_fmt {
293 ROCKCHIP_VPU_ENC_FMT_YUV420P = 0,
294 ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1,
295 ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2,
296 ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
299 extern const struct hantro_variant imx8mm_vpu_g1_variant;
300 extern const struct hantro_variant imx8mq_vpu_g1_variant;
301 extern const struct hantro_variant imx8mq_vpu_g2_variant;
302 extern const struct hantro_variant imx8mq_vpu_variant;
303 extern const struct hantro_variant px30_vpu_variant;
304 extern const struct hantro_variant rk3036_vpu_variant;
305 extern const struct hantro_variant rk3066_vpu_variant;
306 extern const struct hantro_variant rk3288_vpu_variant;
307 extern const struct hantro_variant rk3328_vpu_variant;
308 extern const struct hantro_variant rk3399_vpu_variant;
309 extern const struct hantro_variant rk3568_vpu_variant;
310 extern const struct hantro_variant sama5d4_vdec_variant;
311 extern const struct hantro_variant sunxi_vpu_variant;
313 extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
314 extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
316 extern const u32 hantro_vp8_dec_mc_filter[8][6];
318 void hantro_watchdog(struct work_struct *work);
319 void hantro_run(struct hantro_ctx *ctx);
320 void hantro_irq_done(struct hantro_dev *vpu,
321 enum vb2_buffer_state result);
322 void hantro_start_prepare_run(struct hantro_ctx *ctx);
323 void hantro_end_prepare_run(struct hantro_ctx *ctx);
325 irqreturn_t hantro_g1_irq(int irq, void *dev_id);
326 void hantro_g1_reset(struct hantro_ctx *ctx);
328 int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
329 int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx);
330 void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx);
331 void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx);
333 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
334 unsigned int dpb_idx);
335 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx,
336 unsigned int dpb_idx);
337 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
338 int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx);
339 int hantro_g1_h264_dec_run(struct hantro_ctx *ctx);
340 int hantro_h264_dec_init(struct hantro_ctx *ctx);
341 void hantro_h264_dec_exit(struct hantro_ctx *ctx);
343 int hantro_hevc_dec_init(struct hantro_ctx *ctx);
344 void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
345 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
346 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
347 void hantro_hevc_ref_init(struct hantro_ctx *ctx);
348 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc);
349 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);
351 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)
353 return (dimension + 63) / 64;
357 hantro_vp9_mv_size(unsigned int width, unsigned int height)
362 * There can be up to (CTBs x 64) number of blocks,
363 * and the motion vector for each block needs 16 bytes.
365 num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
366 return (num_ctbs * 64) * 16;
370 hantro_h264_mv_size(unsigned int width, unsigned int height)
373 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
374 * 448 bytes per macroblock with additional 32 bytes on
375 * multi-core variants.
377 * The H264 decoder needs extra space on the output buffers
378 * to store motion vectors. This is needed for reference
379 * frames and only if the format is non-post-processed NV12.
381 * Memory layout is as follow:
383 * +---------------------------+
384 * | Y-plane 256 bytes x MBs |
385 * +---------------------------+
386 * | UV-plane 128 bytes x MBs |
387 * +---------------------------+
388 * | MV buffer 64 bytes x MBs |
389 * +---------------------------+
390 * | MC sync 32 bytes |
391 * +---------------------------+
393 return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
397 hantro_hevc_mv_size(unsigned int width, unsigned int height)
400 * A CTB can be 64x64, 32x32 or 16x16.
401 * Allocated memory for the "worse" case: 16x16
403 return width * height / 16;
406 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
407 int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
408 void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
409 const struct v4l2_ctrl_mpeg2_quantisation *ctrl);
410 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
411 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
413 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);
414 int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx);
415 int hantro_vp8_dec_init(struct hantro_ctx *ctx);
416 void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
417 void hantro_vp8_prob_update(struct hantro_ctx *ctx,
418 const struct v4l2_ctrl_vp8_frame *hdr);
420 int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx);
421 void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx);
422 int hantro_vp9_dec_init(struct hantro_ctx *ctx);
423 void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
424 void hantro_g2_check_idle(struct hantro_dev *vpu);
425 irqreturn_t hantro_g2_irq(int irq, void *dev_id);
427 #endif /* HANTRO_HW_H_ */