1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
27 static u32 array_agc_tab_1t_8188e[] = {
158 static bool set_baseband_agc_config(struct adapter *adapt)
161 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
162 u32 *array = array_agc_tab_1t_8188e;
164 for (i = 0; i < arraylen; i += 2) {
166 u32 v2 = array[i + 1];
168 if (v1 < 0xCDCDCDCD) {
169 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
178 static u32 array_phy_reg_1t_8188e[] = {
372 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
376 } else if (addr == 0xfd) {
378 } else if (addr == 0xfc) {
380 } else if (addr == 0xfb) {
382 } else if (addr == 0xfa) {
384 } else if (addr == 0xf9) {
387 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
388 /* Add 1us delay between BB/RF register setting. */
393 static bool set_baseband_phy_config(struct adapter *adapt)
396 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
397 u32 *array = array_phy_reg_1t_8188e;
399 for (i = 0; i < arraylen; i += 2) {
401 u32 v2 = array[i + 1];
404 rtl_bb_delay(adapt, v1, v2);
411 static u32 array_phy_reg_pg_8188e[] = {
412 0xE00, 0xFFFFFFFF, 0x06070809,
413 0xE04, 0xFFFFFFFF, 0x02020405,
414 0xE08, 0x0000FF00, 0x00000006,
415 0x86C, 0xFFFFFF00, 0x00020400,
416 0xE10, 0xFFFFFFFF, 0x08090A0B,
417 0xE14, 0xFFFFFFFF, 0x01030607,
418 0xE18, 0xFFFFFFFF, 0x08090A0B,
419 0xE1C, 0xFFFFFFFF, 0x01030607,
420 0xE00, 0xFFFFFFFF, 0x00000000,
421 0xE04, 0xFFFFFFFF, 0x00000000,
422 0xE08, 0x0000FF00, 0x00000000,
423 0x86C, 0xFFFFFF00, 0x00000000,
424 0xE10, 0xFFFFFFFF, 0x00000000,
425 0xE14, 0xFFFFFFFF, 0x00000000,
426 0xE18, 0xFFFFFFFF, 0x00000000,
427 0xE1C, 0xFFFFFFFF, 0x00000000,
428 0xE00, 0xFFFFFFFF, 0x02020202,
429 0xE04, 0xFFFFFFFF, 0x00020202,
430 0xE08, 0x0000FF00, 0x00000000,
431 0x86C, 0xFFFFFF00, 0x00000000,
432 0xE10, 0xFFFFFFFF, 0x04040404,
433 0xE14, 0xFFFFFFFF, 0x00020404,
434 0xE18, 0xFFFFFFFF, 0x00000000,
435 0xE1C, 0xFFFFFFFF, 0x00000000,
436 0xE00, 0xFFFFFFFF, 0x02020202,
437 0xE04, 0xFFFFFFFF, 0x00020202,
438 0xE08, 0x0000FF00, 0x00000000,
439 0x86C, 0xFFFFFF00, 0x00000000,
440 0xE10, 0xFFFFFFFF, 0x04040404,
441 0xE14, 0xFFFFFFFF, 0x00020404,
442 0xE18, 0xFFFFFFFF, 0x00000000,
443 0xE1C, 0xFFFFFFFF, 0x00000000,
444 0xE00, 0xFFFFFFFF, 0x00000000,
445 0xE04, 0xFFFFFFFF, 0x00000000,
446 0xE08, 0x0000FF00, 0x00000000,
447 0x86C, 0xFFFFFF00, 0x00000000,
448 0xE10, 0xFFFFFFFF, 0x00000000,
449 0xE14, 0xFFFFFFFF, 0x00000000,
450 0xE18, 0xFFFFFFFF, 0x00000000,
451 0xE1C, 0xFFFFFFFF, 0x00000000,
452 0xE00, 0xFFFFFFFF, 0x02020202,
453 0xE04, 0xFFFFFFFF, 0x00020202,
454 0xE08, 0x0000FF00, 0x00000000,
455 0x86C, 0xFFFFFF00, 0x00000000,
456 0xE10, 0xFFFFFFFF, 0x04040404,
457 0xE14, 0xFFFFFFFF, 0x00020404,
458 0xE18, 0xFFFFFFFF, 0x00000000,
459 0xE1C, 0xFFFFFFFF, 0x00000000,
460 0xE00, 0xFFFFFFFF, 0x00000000,
461 0xE04, 0xFFFFFFFF, 0x00000000,
462 0xE08, 0x0000FF00, 0x00000000,
463 0x86C, 0xFFFFFF00, 0x00000000,
464 0xE10, 0xFFFFFFFF, 0x00000000,
465 0xE14, 0xFFFFFFFF, 0x00000000,
466 0xE18, 0xFFFFFFFF, 0x00000000,
467 0xE1C, 0xFFFFFFFF, 0x00000000,
468 0xE00, 0xFFFFFFFF, 0x00000000,
469 0xE04, 0xFFFFFFFF, 0x00000000,
470 0xE08, 0x0000FF00, 0x00000000,
471 0x86C, 0xFFFFFF00, 0x00000000,
472 0xE10, 0xFFFFFFFF, 0x00000000,
473 0xE14, 0xFFFFFFFF, 0x00000000,
474 0xE18, 0xFFFFFFFF, 0x00000000,
475 0xE1C, 0xFFFFFFFF, 0x00000000,
476 0xE00, 0xFFFFFFFF, 0x00000000,
477 0xE04, 0xFFFFFFFF, 0x00000000,
478 0xE08, 0x0000FF00, 0x00000000,
479 0x86C, 0xFFFFFF00, 0x00000000,
480 0xE10, 0xFFFFFFFF, 0x00000000,
481 0xE14, 0xFFFFFFFF, 0x00000000,
482 0xE18, 0xFFFFFFFF, 0x00000000,
483 0xE1C, 0xFFFFFFFF, 0x00000000,
484 0xE00, 0xFFFFFFFF, 0x00000000,
485 0xE04, 0xFFFFFFFF, 0x00000000,
486 0xE08, 0x0000FF00, 0x00000000,
487 0x86C, 0xFFFFFF00, 0x00000000,
488 0xE10, 0xFFFFFFFF, 0x00000000,
489 0xE14, 0xFFFFFFFF, 0x00000000,
490 0xE18, 0xFFFFFFFF, 0x00000000,
491 0xE1C, 0xFFFFFFFF, 0x00000000,
492 0xE00, 0xFFFFFFFF, 0x00000000,
493 0xE04, 0xFFFFFFFF, 0x00000000,
494 0xE08, 0x0000FF00, 0x00000000,
495 0x86C, 0xFFFFFF00, 0x00000000,
496 0xE10, 0xFFFFFFFF, 0x00000000,
497 0xE14, 0xFFFFFFFF, 0x00000000,
498 0xE18, 0xFFFFFFFF, 0x00000000,
499 0xE1C, 0xFFFFFFFF, 0x00000000,
503 static void store_pwrindex_offset(struct adapter *adapter,
504 u32 regaddr, u32 bitmask, u32 data)
506 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
507 u32 * const power_level_offset =
508 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
510 if (regaddr == rTxAGC_A_Rate18_06)
511 power_level_offset[0] = data;
512 if (regaddr == rTxAGC_A_Rate54_24)
513 power_level_offset[1] = data;
514 if (regaddr == rTxAGC_A_CCK1_Mcs32)
515 power_level_offset[6] = data;
516 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
517 power_level_offset[7] = data;
518 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
519 power_level_offset[2] = data;
520 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
521 power_level_offset[3] = data;
522 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
523 power_level_offset[4] = data;
524 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
525 power_level_offset[5] = data;
526 if (hal_data->rf_type == RF_1T1R)
527 hal_data->pwrGroupCnt++;
529 if (regaddr == rTxAGC_B_Rate18_06)
530 power_level_offset[8] = data;
531 if (regaddr == rTxAGC_B_Rate54_24)
532 power_level_offset[9] = data;
533 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
534 power_level_offset[14] = data;
535 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
536 power_level_offset[15] = data;
537 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
538 power_level_offset[10] = data;
539 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
540 power_level_offset[11] = data;
541 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
542 power_level_offset[12] = data;
543 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
544 power_level_offset[13] = data;
545 if (hal_data->rf_type != RF_1T1R)
546 hal_data->pwrGroupCnt++;
550 static void rtl_addr_delay(struct adapter *adapt,
551 u32 addr, u32 bit_mask, u32 data)
573 store_pwrindex_offset(adapt, addr, bit_mask, data);
577 static bool config_bb_with_pgheader(struct adapter *adapt)
580 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
581 u32 *array = array_phy_reg_pg_8188e;
583 for (i = 0; i < arraylen; i += 3) {
585 u32 v2 = array[i + 1];
586 u32 v3 = array[i + 2];
589 rtl_addr_delay(adapt, v1, v2, v3);
594 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
596 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
597 struct bb_reg_def *reg[4];
599 reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A];
600 reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B];
601 reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C];
602 reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D];
604 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
605 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
606 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
607 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
609 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
610 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
611 reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
612 reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
614 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
615 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
617 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
618 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
620 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
621 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
623 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
624 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
625 reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
626 reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
628 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
629 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
630 reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage;
631 reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage;
633 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
634 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
636 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
637 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
639 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
640 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
641 reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
642 reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
644 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
645 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
646 reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1;
647 reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1;
649 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
650 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
651 reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2;
652 reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2;
654 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
655 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
656 reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
657 reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
659 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
660 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
661 reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE;
662 reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE;
664 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
665 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
666 reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
667 reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
669 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
670 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
671 reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE;
672 reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE;
674 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
675 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
676 reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
677 reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
679 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
680 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
683 static bool config_parafile(struct adapter *adapt)
685 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
686 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
688 set_baseband_phy_config(adapt);
690 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
691 if (!eeprom->bautoload_fail_flag) {
692 hal_data->pwrGroupCnt = 0;
693 config_bb_with_pgheader(adapt);
695 set_baseband_agc_config(adapt);
699 bool rtl88eu_phy_bb_config(struct adapter *adapt)
702 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
706 rtl88e_phy_init_bb_rf_register_definition(adapt);
708 /* Enable BB and RF */
709 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
710 usb_write16(adapt, REG_SYS_FUNC_EN,
711 (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
713 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
715 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
716 FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
718 /* Config BB and AGC */
719 rtstatus = config_parafile(adapt);
721 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
722 crystal_cap = hal_data->CrystalCap & 0x3F;
723 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
724 (crystal_cap | (crystal_cap << 6)));