gt/uc/intel_uc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #include "gt/intel_gt.h"
   7 #include "gt/intel_reset.h"
   8 #include "intel_guc.h"
   9 #include "intel_guc_ads.h"
  10 #include "intel_guc_submission.h"
  11 #include "intel_uc.h"
  12
  13 #include "i915_drv.h"
  14
  15 static const struct intel_uc_ops uc_ops_off;
  16 static const struct intel_uc_ops uc_ops_on;
  17
  18 /* Reset GuC providing us with fresh state for both GuC and HuC.
  19  */
  20 static int __intel_uc_reset_hw(struct intel_uc *uc)
  21 {
  22         struct intel_gt *gt = uc_to_gt(uc);
  23         int ret;
  24         u32 guc_status;
  25
  26         ret = i915_inject_probe_error(gt->i915, -ENXIO);
  27         if (ret)
  28                 return ret;
  29
  30         ret = intel_reset_guc(gt);
  31         if (ret) {
  32                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  33                 return ret;
  34         }
  35
  36         guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
  37         WARN(!(guc_status & GS_MIA_IN_RESET),
  38              "GuC status: 0x%x, MIA core expected to be in reset\n",
  39              guc_status);
  40
  41         return ret;
  42 }
  43
  44 static void __confirm_options(struct intel_uc *uc)
  45 {
  46         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  47
  48         drm_dbg(&i915->drm,
  49                 "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
  50                 i915->params.enable_guc,
  51                 yesno(intel_uc_wants_guc(uc)),
  52                 yesno(intel_uc_wants_guc_submission(uc)),
  53                 yesno(intel_uc_wants_huc(uc)));
  54
  55         if (i915->params.enable_guc == -1)
  56                 return;
  57
  58         if (i915->params.enable_guc == 0) {
  59                 GEM_BUG_ON(intel_uc_wants_guc(uc));
  60                 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
  61                 GEM_BUG_ON(intel_uc_wants_huc(uc));
  62                 return;
  63         }
  64
  65         if (!intel_uc_supports_guc(uc))
  66                 drm_info(&i915->drm,
  67                          "Incompatible option enable_guc=%d - %s\n",
  68                          i915->params.enable_guc, "GuC is not supported!");
  69
  70         if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
  71             !intel_uc_supports_huc(uc))
  72                 drm_info(&i915->drm,
  73                          "Incompatible option enable_guc=%d - %s\n",
  74                          i915->params.enable_guc, "HuC is not supported!");
  75
  76         if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
  77             !intel_uc_supports_guc_submission(uc))
  78                 drm_info(&i915->drm,
  79                          "Incompatible option enable_guc=%d - %s\n",
  80                          i915->params.enable_guc, "GuC submission is N/A");
  81
  82         if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION |
  83                                           ENABLE_GUC_LOAD_HUC))
  84                 drm_info(&i915->drm,
  85                          "Incompatible option enable_guc=%d - %s\n",
  86                          i915->params.enable_guc, "undocumented flag");
  87 }
  88
  89 void intel_uc_init_early(struct intel_uc *uc)
  90 {
  91         intel_guc_init_early(&uc->guc);
  92         intel_huc_init_early(&uc->huc);
  93
  94         __confirm_options(uc);
  95
  96         if (intel_uc_wants_guc(uc))
  97                 uc->ops = &uc_ops_on;
  98         else
  99                 uc->ops = &uc_ops_off;
 100 }
 101
 102 void intel_uc_driver_late_release(struct intel_uc *uc)
 103 {
 104 }
 105
 106 /**
 107  * intel_uc_init_mmio - setup uC MMIO access
 108  * @uc: the intel_uc structure
 109  *
 110  * Setup minimal state necessary for MMIO accesses later in the
 111  * initialization sequence.
 112  */
 113 void intel_uc_init_mmio(struct intel_uc *uc)
 114 {
 115         intel_guc_init_send_regs(&uc->guc);
 116 }
 117
 118 static void __uc_capture_load_err_log(struct intel_uc *uc)
 119 {
 120         struct intel_guc *guc = &uc->guc;
 121
 122         if (guc->log.vma && !uc->load_err_log)
 123                 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 124 }
 125
 126 static void __uc_free_load_err_log(struct intel_uc *uc)
 127 {
 128         struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
 129
 130         if (log)
 131                 i915_gem_object_put(log);
 132 }
 133
 134 void intel_uc_driver_remove(struct intel_uc *uc)
 135 {
 136         intel_uc_fini_hw(uc);
 137         intel_uc_fini(uc);
 138         __uc_free_load_err_log(uc);
 139 }
 140
 141 static inline bool guc_communication_enabled(struct intel_guc *guc)
 142 {
 143         return intel_guc_ct_enabled(&guc->ct);
 144 }
 145
 146 /*
 147  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
 148  * register using the same bits used in the CT message payload. Since our
 149  * communication channel with guc is turned off at this point, we can save the
 150  * message and handle it after we turn it back on.
 151  */
 152 static void guc_clear_mmio_msg(struct intel_guc *guc)
 153 {
 154         intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
 155 }
 156
 157 static void guc_get_mmio_msg(struct intel_guc *guc)
 158 {
 159         u32 val;
 160
 161         spin_lock_irq(&guc->irq_lock);
 162
 163         val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
 164         guc->mmio_msg |= val & guc->msg_enabled_mask;
 165
 166         /*
 167          * clear all events, including the ones we're not currently servicing,
 168          * to make sure we don't try to process a stale message if we enable
 169          * handling of more events later.
 170          */
 171         guc_clear_mmio_msg(guc);
 172
 173         spin_unlock_irq(&guc->irq_lock);
 174 }
 175
 176 static void guc_handle_mmio_msg(struct intel_guc *guc)
 177 {
 178         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 179
 180         /* we need communication to be enabled to reply to GuC */
 181         GEM_BUG_ON(!guc_communication_enabled(guc));
 182
 183         if (!guc->mmio_msg)
 184                 return;
 185
 186         spin_lock_irq(&i915->irq_lock);
 187         intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
 188         spin_unlock_irq(&i915->irq_lock);
 189
 190         guc->mmio_msg = 0;
 191 }
 192
 193 static void guc_reset_interrupts(struct intel_guc *guc)
 194 {
 195         guc->interrupts.reset(guc);
 196 }
 197
 198 static void guc_enable_interrupts(struct intel_guc *guc)
 199 {
 200         guc->interrupts.enable(guc);
 201 }
 202
 203 static void guc_disable_interrupts(struct intel_guc *guc)
 204 {
 205         guc->interrupts.disable(guc);
 206 }
 207
 208 static int guc_enable_communication(struct intel_guc *guc)
 209 {
 210         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 211         int ret;
 212
 213         GEM_BUG_ON(guc_communication_enabled(guc));
 214
 215         ret = i915_inject_probe_error(i915, -ENXIO);
 216         if (ret)
 217                 return ret;
 218
 219         ret = intel_guc_ct_enable(&guc->ct);
 220         if (ret)
 221                 return ret;
 222
 223         /* check for mmio messages received before/during the CT enable */
 224         guc_get_mmio_msg(guc);
 225         guc_handle_mmio_msg(guc);
 226
 227         guc_enable_interrupts(guc);
 228
 229         /* check for CT messages received before we enabled interrupts */
 230         spin_lock_irq(&i915->irq_lock);
 231         intel_guc_ct_event_handler(&guc->ct);
 232         spin_unlock_irq(&i915->irq_lock);
 233
 234         DRM_INFO("GuC communication enabled\n");
 235
 236         return 0;
 237 }
 238
 239 static void guc_disable_communication(struct intel_guc *guc)
 240 {
 241         /*
 242          * Events generated during or after CT disable are logged by guc in
 243          * via mmio. Make sure the register is clear before disabling CT since
 244          * all events we cared about have already been processed via CT.
 245          */
 246         guc_clear_mmio_msg(guc);
 247
 248         guc_disable_interrupts(guc);
 249
 250         intel_guc_ct_disable(&guc->ct);
 251
 252         /*
 253          * Check for messages received during/after the CT disable. We do not
 254          * expect any messages to have arrived via CT between the interrupt
 255          * disable and the CT disable because GuC should've been idle until we
 256          * triggered the CT disable protocol.
 257          */
 258         guc_get_mmio_msg(guc);
 259
 260         DRM_INFO("GuC communication disabled\n");
 261 }
 262
 263 static void __uc_fetch_firmwares(struct intel_uc *uc)
 264 {
 265         int err;
 266
 267         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 268
 269         err = intel_uc_fw_fetch(&uc->guc.fw);
 270         if (err) {
 271                 /* Make sure we transition out of transient "SELECTED" state */
 272                 if (intel_uc_wants_huc(uc)) {
 273                         drm_dbg(&uc_to_gt(uc)->i915->drm,
 274                                 "Failed to fetch GuC: %d disabling HuC\n", err);
 275                         intel_uc_fw_change_status(&uc->huc.fw,
 276                                                   INTEL_UC_FIRMWARE_ERROR);
 277                 }
 278
 279                 return;
 280         }
 281
 282         if (intel_uc_wants_huc(uc))
 283                 intel_uc_fw_fetch(&uc->huc.fw);
 284 }
 285
 286 static void __uc_cleanup_firmwares(struct intel_uc *uc)
 287 {
 288         intel_uc_fw_cleanup_fetch(&uc->huc.fw);
 289         intel_uc_fw_cleanup_fetch(&uc->guc.fw);
 290 }
 291
 292 static int __uc_init(struct intel_uc *uc)
 293 {
 294         struct intel_guc *guc = &uc->guc;
 295         struct intel_huc *huc = &uc->huc;
 296         int ret;
 297
 298         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 299
 300         if (!intel_uc_uses_guc(uc))
 301                 return 0;
 302
 303         if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
 304                 return -ENOMEM;
 305
 306         /* XXX: GuC submission is unavailable for now */
 307         GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
 308
 309         ret = intel_guc_init(guc);
 310         if (ret)
 311                 return ret;
 312
 313         if (intel_uc_uses_huc(uc)) {
 314                 ret = intel_huc_init(huc);
 315                 if (ret)
 316                         goto out_guc;
 317         }
 318
 319         return 0;
 320
 321 out_guc:
 322         intel_guc_fini(guc);
 323         return ret;
 324 }
 325
 326 static void __uc_fini(struct intel_uc *uc)
 327 {
 328         intel_huc_fini(&uc->huc);
 329         intel_guc_fini(&uc->guc);
 330 }
 331
 332 static int __uc_sanitize(struct intel_uc *uc)
 333 {
 334         struct intel_guc *guc = &uc->guc;
 335         struct intel_huc *huc = &uc->huc;
 336
 337         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 338
 339         intel_huc_sanitize(huc);
 340         intel_guc_sanitize(guc);
 341
 342         return __intel_uc_reset_hw(uc);
 343 }
 344
 345 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
 346 static int uc_init_wopcm(struct intel_uc *uc)
 347 {
 348         struct intel_gt *gt = uc_to_gt(uc);
 349         struct intel_uncore *uncore = gt->uncore;
 350         u32 base = intel_wopcm_guc_base(&gt->i915->wopcm);
 351         u32 size = intel_wopcm_guc_size(&gt->i915->wopcm);
 352         u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
 353         u32 mask;
 354         int err;
 355
 356         if (unlikely(!base || !size)) {
 357                 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
 358                 return -E2BIG;
 359         }
 360
 361         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 362         GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
 363         GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
 364         GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
 365         GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
 366
 367         err = i915_inject_probe_error(gt->i915, -ENXIO);
 368         if (err)
 369                 return err;
 370
 371         mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
 372         err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
 373                                             size | GUC_WOPCM_SIZE_LOCKED);
 374         if (err)
 375                 goto err_out;
 376
 377         mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
 378         err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
 379                                             base | huc_agent, mask,
 380                                             base | huc_agent |
 381                                             GUC_WOPCM_OFFSET_VALID);
 382         if (err)
 383                 goto err_out;
 384
 385         return 0;
 386
 387 err_out:
 388         i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
 389         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
 390                          i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
 391                          intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
 392         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
 393                          i915_mmio_reg_offset(GUC_WOPCM_SIZE),
 394                          intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 395
 396         return err;
 397 }
 398
 399 static bool uc_is_wopcm_locked(struct intel_uc *uc)
 400 {
 401         struct intel_gt *gt = uc_to_gt(uc);
 402         struct intel_uncore *uncore = gt->uncore;
 403
 404         return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
 405                (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
 406 }
 407
 408 static int __uc_check_hw(struct intel_uc *uc)
 409 {
 410         if (!intel_uc_supports_guc(uc))
 411                 return 0;
 412
 413         /*
 414          * We can silently continue without GuC only if it was never enabled
 415          * before on this system after reboot, otherwise we risk GPU hangs.
 416          * To check if GuC was loaded before we look at WOPCM registers.
 417          */
 418         if (uc_is_wopcm_locked(uc))
 419                 return -EIO;
 420
 421         return 0;
 422 }
 423
 424 static int __uc_init_hw(struct intel_uc *uc)
 425 {
 426         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
 427         struct intel_guc *guc = &uc->guc;
 428         struct intel_huc *huc = &uc->huc;
 429         int ret, attempts;
 430
 431         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 432         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 433
 434         if (!intel_uc_fw_is_loadable(&guc->fw)) {
 435                 ret = __uc_check_hw(uc) ||
 436                       intel_uc_fw_is_overridden(&guc->fw) ||
 437                       intel_uc_wants_guc_submission(uc) ?
 438                       intel_uc_fw_status_to_error(guc->fw.status) : 0;
 439                 goto err_out;
 440         }
 441
 442         ret = uc_init_wopcm(uc);
 443         if (ret)
 444                 goto err_out;
 445
 446         guc_reset_interrupts(guc);
 447
 448         /* WaEnableuKernelHeaderValidFix:skl */
 449         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 450         if (IS_GEN(i915, 9))
 451                 attempts = 3;
 452         else
 453                 attempts = 1;
 454
 455         while (attempts--) {
 456                 /*
 457                  * Always reset the GuC just before (re)loading, so
 458                  * that the state and timing are fairly predictable
 459                  */
 460                 ret = __uc_sanitize(uc);
 461                 if (ret)
 462                         goto err_out;
 463
 464                 intel_huc_fw_upload(huc);
 465                 intel_guc_ads_reset(guc);
 466                 intel_guc_write_params(guc);
 467                 ret = intel_guc_fw_upload(guc);
 468                 if (ret == 0)
 469                         break;
 470
 471                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 472                                  "retry %d more time(s)\n", ret, attempts);
 473         }
 474
 475         /* Did we succeded or run out of retries? */
 476         if (ret)
 477                 goto err_log_capture;
 478
 479         ret = guc_enable_communication(guc);
 480         if (ret)
 481                 goto err_log_capture;
 482
 483         intel_huc_auth(huc);
 484
 485         ret = intel_guc_sample_forcewake(guc);
 486         if (ret)
 487                 goto err_communication;
 488
 489         if (intel_uc_uses_guc_submission(uc))
 490                 intel_guc_submission_enable(guc);
 491
 492         drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
 493                  intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
 494                  guc->fw.major_ver_found, guc->fw.minor_ver_found,
 495                  "submission",
 496                  enableddisabled(intel_uc_uses_guc_submission(uc)));
 497
 498         if (intel_uc_uses_huc(uc)) {
 499                 drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
 500                          intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
 501                          huc->fw.path,
 502                          huc->fw.major_ver_found, huc->fw.minor_ver_found,
 503                          "authenticated",
 504                          yesno(intel_huc_is_authenticated(huc)));
 505         }
 506
 507         return 0;
 508
 509         /*
 510          * We've failed to load the firmware :(
 511          */
 512 err_communication:
 513         guc_disable_communication(guc);
 514 err_log_capture:
 515         __uc_capture_load_err_log(uc);
 516 err_out:
 517         __uc_sanitize(uc);
 518
 519         if (!ret) {
 520                 drm_notice(&i915->drm, "GuC is uninitialized\n");
 521                 /* We want to run without GuC submission */
 522                 return 0;
 523         }
 524
 525         i915_probe_error(i915, "GuC initialization failed %d\n", ret);
 526
 527         /* We want to keep KMS alive */
 528         return -EIO;
 529 }
 530
 531 static void __uc_fini_hw(struct intel_uc *uc)
 532 {
 533         struct intel_guc *guc = &uc->guc;
 534
 535         if (!intel_guc_is_fw_running(guc))
 536                 return;
 537
 538         if (intel_uc_uses_guc_submission(uc))
 539                 intel_guc_submission_disable(guc);
 540
 541         if (guc_communication_enabled(guc))
 542                 guc_disable_communication(guc);
 543
 544         __uc_sanitize(uc);
 545 }
 546
 547 /**
 548  * intel_uc_reset_prepare - Prepare for reset
 549  * @uc: the intel_uc structure
 550  *
 551  * Preparing for full gpu reset.
 552  */
 553 void intel_uc_reset_prepare(struct intel_uc *uc)
 554 {
 555         struct intel_guc *guc = &uc->guc;
 556
 557         if (!intel_guc_is_ready(guc))
 558                 return;
 559
 560         guc_disable_communication(guc);
 561         __uc_sanitize(uc);
 562 }
 563
 564 void intel_uc_runtime_suspend(struct intel_uc *uc)
 565 {
 566         struct intel_guc *guc = &uc->guc;
 567         int err;
 568
 569         if (!intel_guc_is_ready(guc))
 570                 return;
 571
 572         err = intel_guc_suspend(guc);
 573         if (err)
 574                 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 575
 576         guc_disable_communication(guc);
 577 }
 578
 579 void intel_uc_suspend(struct intel_uc *uc)
 580 {
 581         struct intel_guc *guc = &uc->guc;
 582         intel_wakeref_t wakeref;
 583
 584         if (!intel_guc_is_ready(guc))
 585                 return;
 586
 587         with_intel_runtime_pm(uc_to_gt(uc)->uncore->rpm, wakeref)
 588                 intel_uc_runtime_suspend(uc);
 589 }
 590
 591 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
 592 {
 593         struct intel_guc *guc = &uc->guc;
 594         int err;
 595
 596         if (!intel_guc_is_fw_running(guc))
 597                 return 0;
 598
 599         /* Make sure we enable communication if and only if it's disabled */
 600         GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
 601
 602         if (enable_communication)
 603                 guc_enable_communication(guc);
 604
 605         err = intel_guc_resume(guc);
 606         if (err) {
 607                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 608                 return err;
 609         }
 610
 611         return 0;
 612 }
 613
 614 int intel_uc_resume(struct intel_uc *uc)
 615 {
 616         /*
 617          * When coming out of S3/S4 we sanitize and re-init the HW, so
 618          * communication is already re-enabled at this point.
 619          */
 620         return __uc_resume(uc, false);
 621 }
 622
 623 int intel_uc_runtime_resume(struct intel_uc *uc)
 624 {
 625         /*
 626          * During runtime resume we don't sanitize, so we need to re-init
 627          * communication as well.
 628          */
 629         return __uc_resume(uc, true);
 630 }
 631
 632 static const struct intel_uc_ops uc_ops_off = {
 633         .init_hw = __uc_check_hw,
 634 };
 635
 636 static const struct intel_uc_ops uc_ops_on = {
 637         .sanitize = __uc_sanitize,
 638
 639         .init_fw = __uc_fetch_firmwares,
 640         .fini_fw = __uc_cleanup_firmwares,
 641
 642         .init = __uc_init,
 643         .fini = __uc_fini,
 644
 645         .init_hw = __uc_init_hw,
 646         .fini_hw = __uc_fini_hw,
 647 };