1 // SPDX-License-Identifier: MIT
3 * Copyright © 2016-2019 Intel Corporation
6 #include "gt/intel_gt.h"
7 #include "gt/intel_reset.h"
9 #include "intel_guc_ads.h"
10 #include "intel_guc_submission.h"
15 static const struct intel_uc_ops uc_ops_off;
16 static const struct intel_uc_ops uc_ops_on;
18 /* Reset GuC providing us with fresh state for both GuC and HuC.
20 static int __intel_uc_reset_hw(struct intel_uc *uc)
22 struct intel_gt *gt = uc_to_gt(uc);
26 ret = i915_inject_probe_error(gt->i915, -ENXIO);
30 ret = intel_reset_guc(gt);
32 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
36 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
37 WARN(!(guc_status & GS_MIA_IN_RESET),
38 "GuC status: 0x%x, MIA core expected to be in reset\n",
44 static void __confirm_options(struct intel_uc *uc)
46 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
49 "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
50 i915->params.enable_guc,
51 yesno(intel_uc_wants_guc(uc)),
52 yesno(intel_uc_wants_guc_submission(uc)),
53 yesno(intel_uc_wants_huc(uc)));
55 if (i915->params.enable_guc == -1)
58 if (i915->params.enable_guc == 0) {
59 GEM_BUG_ON(intel_uc_wants_guc(uc));
60 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
61 GEM_BUG_ON(intel_uc_wants_huc(uc));
65 if (!intel_uc_supports_guc(uc))
67 "Incompatible option enable_guc=%d - %s\n",
68 i915->params.enable_guc, "GuC is not supported!");
70 if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
71 !intel_uc_supports_huc(uc))
73 "Incompatible option enable_guc=%d - %s\n",
74 i915->params.enable_guc, "HuC is not supported!");
76 if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
77 !intel_uc_supports_guc_submission(uc))
79 "Incompatible option enable_guc=%d - %s\n",
80 i915->params.enable_guc, "GuC submission is N/A");
82 if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION |
85 "Incompatible option enable_guc=%d - %s\n",
86 i915->params.enable_guc, "undocumented flag");
89 void intel_uc_init_early(struct intel_uc *uc)
91 intel_guc_init_early(&uc->guc);
92 intel_huc_init_early(&uc->huc);
94 __confirm_options(uc);
96 if (intel_uc_wants_guc(uc))
99 uc->ops = &uc_ops_off;
102 void intel_uc_driver_late_release(struct intel_uc *uc)
107 * intel_uc_init_mmio - setup uC MMIO access
108 * @uc: the intel_uc structure
110 * Setup minimal state necessary for MMIO accesses later in the
111 * initialization sequence.
113 void intel_uc_init_mmio(struct intel_uc *uc)
115 intel_guc_init_send_regs(&uc->guc);
118 static void __uc_capture_load_err_log(struct intel_uc *uc)
120 struct intel_guc *guc = &uc->guc;
122 if (guc->log.vma && !uc->load_err_log)
123 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
126 static void __uc_free_load_err_log(struct intel_uc *uc)
128 struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
131 i915_gem_object_put(log);
134 void intel_uc_driver_remove(struct intel_uc *uc)
136 intel_uc_fini_hw(uc);
138 __uc_free_load_err_log(uc);
141 static inline bool guc_communication_enabled(struct intel_guc *guc)
143 return intel_guc_ct_enabled(&guc->ct);
147 * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
148 * register using the same bits used in the CT message payload. Since our
149 * communication channel with guc is turned off at this point, we can save the
150 * message and handle it after we turn it back on.
152 static void guc_clear_mmio_msg(struct intel_guc *guc)
154 intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
157 static void guc_get_mmio_msg(struct intel_guc *guc)
161 spin_lock_irq(&guc->irq_lock);
163 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
164 guc->mmio_msg |= val & guc->msg_enabled_mask;
167 * clear all events, including the ones we're not currently servicing,
168 * to make sure we don't try to process a stale message if we enable
169 * handling of more events later.
171 guc_clear_mmio_msg(guc);
173 spin_unlock_irq(&guc->irq_lock);
176 static void guc_handle_mmio_msg(struct intel_guc *guc)
178 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
180 /* we need communication to be enabled to reply to GuC */
181 GEM_BUG_ON(!guc_communication_enabled(guc));
186 spin_lock_irq(&i915->irq_lock);
187 intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
188 spin_unlock_irq(&i915->irq_lock);
193 static void guc_reset_interrupts(struct intel_guc *guc)
195 guc->interrupts.reset(guc);
198 static void guc_enable_interrupts(struct intel_guc *guc)
200 guc->interrupts.enable(guc);
203 static void guc_disable_interrupts(struct intel_guc *guc)
205 guc->interrupts.disable(guc);
208 static int guc_enable_communication(struct intel_guc *guc)
210 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
213 GEM_BUG_ON(guc_communication_enabled(guc));
215 ret = i915_inject_probe_error(i915, -ENXIO);
219 ret = intel_guc_ct_enable(&guc->ct);
223 /* check for mmio messages received before/during the CT enable */
224 guc_get_mmio_msg(guc);
225 guc_handle_mmio_msg(guc);
227 guc_enable_interrupts(guc);
229 /* check for CT messages received before we enabled interrupts */
230 spin_lock_irq(&i915->irq_lock);
231 intel_guc_ct_event_handler(&guc->ct);
232 spin_unlock_irq(&i915->irq_lock);
234 DRM_INFO("GuC communication enabled\n");
239 static void guc_disable_communication(struct intel_guc *guc)
242 * Events generated during or after CT disable are logged by guc in
243 * via mmio. Make sure the register is clear before disabling CT since
244 * all events we cared about have already been processed via CT.
246 guc_clear_mmio_msg(guc);
248 guc_disable_interrupts(guc);
250 intel_guc_ct_disable(&guc->ct);
253 * Check for messages received during/after the CT disable. We do not
254 * expect any messages to have arrived via CT between the interrupt
255 * disable and the CT disable because GuC should've been idle until we
256 * triggered the CT disable protocol.
258 guc_get_mmio_msg(guc);
260 DRM_INFO("GuC communication disabled\n");
263 static void __uc_fetch_firmwares(struct intel_uc *uc)
267 GEM_BUG_ON(!intel_uc_wants_guc(uc));
269 err = intel_uc_fw_fetch(&uc->guc.fw);
271 /* Make sure we transition out of transient "SELECTED" state */
272 if (intel_uc_wants_huc(uc)) {
273 drm_dbg(&uc_to_gt(uc)->i915->drm,
274 "Failed to fetch GuC: %d disabling HuC\n", err);
275 intel_uc_fw_change_status(&uc->huc.fw,
276 INTEL_UC_FIRMWARE_ERROR);
282 if (intel_uc_wants_huc(uc))
283 intel_uc_fw_fetch(&uc->huc.fw);
286 static void __uc_cleanup_firmwares(struct intel_uc *uc)
288 intel_uc_fw_cleanup_fetch(&uc->huc.fw);
289 intel_uc_fw_cleanup_fetch(&uc->guc.fw);
292 static int __uc_init(struct intel_uc *uc)
294 struct intel_guc *guc = &uc->guc;
295 struct intel_huc *huc = &uc->huc;
298 GEM_BUG_ON(!intel_uc_wants_guc(uc));
300 if (!intel_uc_uses_guc(uc))
303 if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
306 /* XXX: GuC submission is unavailable for now */
307 GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
309 ret = intel_guc_init(guc);
313 if (intel_uc_uses_huc(uc)) {
314 ret = intel_huc_init(huc);
326 static void __uc_fini(struct intel_uc *uc)
328 intel_huc_fini(&uc->huc);
329 intel_guc_fini(&uc->guc);
332 static int __uc_sanitize(struct intel_uc *uc)
334 struct intel_guc *guc = &uc->guc;
335 struct intel_huc *huc = &uc->huc;
337 GEM_BUG_ON(!intel_uc_supports_guc(uc));
339 intel_huc_sanitize(huc);
340 intel_guc_sanitize(guc);
342 return __intel_uc_reset_hw(uc);
345 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
346 static int uc_init_wopcm(struct intel_uc *uc)
348 struct intel_gt *gt = uc_to_gt(uc);
349 struct intel_uncore *uncore = gt->uncore;
350 u32 base = intel_wopcm_guc_base(>->i915->wopcm);
351 u32 size = intel_wopcm_guc_size(>->i915->wopcm);
352 u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
356 if (unlikely(!base || !size)) {
357 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
361 GEM_BUG_ON(!intel_uc_supports_guc(uc));
362 GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
363 GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
364 GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
365 GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
367 err = i915_inject_probe_error(gt->i915, -ENXIO);
371 mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
372 err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
373 size | GUC_WOPCM_SIZE_LOCKED);
377 mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
378 err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
379 base | huc_agent, mask,
381 GUC_WOPCM_OFFSET_VALID);
388 i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
389 i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
390 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
391 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
392 i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
393 i915_mmio_reg_offset(GUC_WOPCM_SIZE),
394 intel_uncore_read(uncore, GUC_WOPCM_SIZE));
399 static bool uc_is_wopcm_locked(struct intel_uc *uc)
401 struct intel_gt *gt = uc_to_gt(uc);
402 struct intel_uncore *uncore = gt->uncore;
404 return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
405 (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
408 static int __uc_check_hw(struct intel_uc *uc)
410 if (!intel_uc_supports_guc(uc))
414 * We can silently continue without GuC only if it was never enabled
415 * before on this system after reboot, otherwise we risk GPU hangs.
416 * To check if GuC was loaded before we look at WOPCM registers.
418 if (uc_is_wopcm_locked(uc))
424 static int __uc_init_hw(struct intel_uc *uc)
426 struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
427 struct intel_guc *guc = &uc->guc;
428 struct intel_huc *huc = &uc->huc;
431 GEM_BUG_ON(!intel_uc_supports_guc(uc));
432 GEM_BUG_ON(!intel_uc_wants_guc(uc));
434 if (!intel_uc_fw_is_loadable(&guc->fw)) {
435 ret = __uc_check_hw(uc) ||
436 intel_uc_fw_is_overridden(&guc->fw) ||
437 intel_uc_wants_guc_submission(uc) ?
438 intel_uc_fw_status_to_error(guc->fw.status) : 0;
442 ret = uc_init_wopcm(uc);
446 guc_reset_interrupts(guc);
448 /* WaEnableuKernelHeaderValidFix:skl */
449 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
457 * Always reset the GuC just before (re)loading, so
458 * that the state and timing are fairly predictable
460 ret = __uc_sanitize(uc);
464 intel_huc_fw_upload(huc);
465 intel_guc_ads_reset(guc);
466 intel_guc_write_params(guc);
467 ret = intel_guc_fw_upload(guc);
471 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
472 "retry %d more time(s)\n", ret, attempts);
475 /* Did we succeded or run out of retries? */
477 goto err_log_capture;
479 ret = guc_enable_communication(guc);
481 goto err_log_capture;
485 ret = intel_guc_sample_forcewake(guc);
487 goto err_communication;
489 if (intel_uc_uses_guc_submission(uc))
490 intel_guc_submission_enable(guc);
492 drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
493 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
494 guc->fw.major_ver_found, guc->fw.minor_ver_found,
496 enableddisabled(intel_uc_uses_guc_submission(uc)));
498 if (intel_uc_uses_huc(uc)) {
499 drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
500 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
502 huc->fw.major_ver_found, huc->fw.minor_ver_found,
504 yesno(intel_huc_is_authenticated(huc)));
510 * We've failed to load the firmware :(
513 guc_disable_communication(guc);
515 __uc_capture_load_err_log(uc);
520 drm_notice(&i915->drm, "GuC is uninitialized\n");
521 /* We want to run without GuC submission */
525 i915_probe_error(i915, "GuC initialization failed %d\n", ret);
527 /* We want to keep KMS alive */
531 static void __uc_fini_hw(struct intel_uc *uc)
533 struct intel_guc *guc = &uc->guc;
535 if (!intel_guc_is_fw_running(guc))
538 if (intel_uc_uses_guc_submission(uc))
539 intel_guc_submission_disable(guc);
541 if (guc_communication_enabled(guc))
542 guc_disable_communication(guc);
548 * intel_uc_reset_prepare - Prepare for reset
549 * @uc: the intel_uc structure
551 * Preparing for full gpu reset.
553 void intel_uc_reset_prepare(struct intel_uc *uc)
555 struct intel_guc *guc = &uc->guc;
557 if (!intel_guc_is_ready(guc))
560 guc_disable_communication(guc);
564 void intel_uc_runtime_suspend(struct intel_uc *uc)
566 struct intel_guc *guc = &uc->guc;
569 if (!intel_guc_is_ready(guc))
572 err = intel_guc_suspend(guc);
574 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
576 guc_disable_communication(guc);
579 void intel_uc_suspend(struct intel_uc *uc)
581 struct intel_guc *guc = &uc->guc;
582 intel_wakeref_t wakeref;
584 if (!intel_guc_is_ready(guc))
587 with_intel_runtime_pm(uc_to_gt(uc)->uncore->rpm, wakeref)
588 intel_uc_runtime_suspend(uc);
591 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
593 struct intel_guc *guc = &uc->guc;
596 if (!intel_guc_is_fw_running(guc))
599 /* Make sure we enable communication if and only if it's disabled */
600 GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
602 if (enable_communication)
603 guc_enable_communication(guc);
605 err = intel_guc_resume(guc);
607 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
614 int intel_uc_resume(struct intel_uc *uc)
617 * When coming out of S3/S4 we sanitize and re-init the HW, so
618 * communication is already re-enabled at this point.
620 return __uc_resume(uc, false);
623 int intel_uc_runtime_resume(struct intel_uc *uc)
626 * During runtime resume we don't sanitize, so we need to re-init
627 * communication as well.
629 return __uc_resume(uc, true);
632 static const struct intel_uc_ops uc_ops_off = {
633 .init_hw = __uc_check_hw,
636 static const struct intel_uc_ops uc_ops_on = {
637 .sanitize = __uc_sanitize,
639 .init_fw = __uc_fetch_firmwares,
640 .fini_fw = __uc_cleanup_firmwares,
645 .init_hw = __uc_init_hw,
646 .fini_hw = __uc_fini_hw,