2 * Copyright (c) 2015 Intel Corporation
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25 #include "intel_engine.h"
27 #include "intel_mocs.h"
28 #include "intel_lrc.h"
29 #include "intel_ring.h"
31 /* structures required */
32 struct drm_i915_mocs_entry {
38 struct drm_i915_mocs_table {
40 unsigned int n_entries;
41 const struct drm_i915_mocs_entry *table;
44 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
45 #define _LE_CACHEABILITY(value) ((value) << 0)
46 #define _LE_TGT_CACHE(value) ((value) << 2)
47 #define LE_LRUM(value) ((value) << 4)
48 #define LE_AOM(value) ((value) << 6)
49 #define LE_RSC(value) ((value) << 7)
50 #define LE_SCC(value) ((value) << 8)
51 #define LE_PFM(value) ((value) << 11)
52 #define LE_SCF(value) ((value) << 14)
53 #define LE_COS(value) ((value) << 15)
54 #define LE_SSE(value) ((value) << 17)
56 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
57 #define L3_ESC(value) ((value) << 0)
58 #define L3_SCC(value) ((value) << 1)
59 #define _L3_CACHEABILITY(value) ((value) << 4)
62 #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
64 /* (e)LLC caching options */
66 * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
69 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
70 #define LE_1_UC _LE_CACHEABILITY(1)
71 #define LE_2_WT _LE_CACHEABILITY(2)
72 #define LE_3_WB _LE_CACHEABILITY(3)
75 #define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
76 #define LE_TC_1_LLC _LE_TGT_CACHE(1)
77 #define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
78 #define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
80 /* L3 caching options */
81 #define L3_0_DIRECT _L3_CACHEABILITY(0)
82 #define L3_1_UC _L3_CACHEABILITY(1)
83 #define L3_2_RESERVED _L3_CACHEABILITY(2)
84 #define L3_3_WB _L3_CACHEABILITY(3)
86 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
88 .control_value = __control_value, \
89 .l3cc_value = __l3cc_value, \
96 * These are the MOCS tables that are programmed across all the rings.
97 * The control value is programmed to all the rings that support the
98 * MOCS registers. While the l3cc_values are only programmed to the
99 * LNCFCMOCS0 - LNCFCMOCS32 registers.
101 * These tables are intended to be kept reasonably consistent across
102 * HW platforms, and for ICL+, be identical across OSes. To achieve
103 * that, for Icelake and above, list of entries is published as part
106 * Entries not part of the following tables are undefined as far as
107 * userspace is concerned and shouldn't be relied upon. For Gen < 12
108 * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
109 * PTE and will be initialized to an invalid value.
111 * The last two entries are reserved by the hardware. For ICL+ they
112 * should be initialized according to bspec and never used, for older
113 * platforms they should never be written to.
115 * NOTE: These tables are part of bspec and defined as part of hardware
116 * interface for ICL+. For older platforms, they are part of kernel
117 * ABI. It is expected that, for specific hardware platform, existing
118 * entries will remain constant and the table will only be updated by
119 * adding new entries, filling unused positions.
121 #define GEN9_MOCS_ENTRIES \
122 MOCS_ENTRY(I915_MOCS_UNCACHED, \
123 LE_1_UC | LE_TC_2_LLC_ELLC, \
125 MOCS_ENTRY(I915_MOCS_PTE, \
126 LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
129 static const struct drm_i915_mocs_entry skl_mocs_table[] = {
131 MOCS_ENTRY(I915_MOCS_CACHED,
132 LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
137 * - used by the L3 for all of its evictions.
138 * Thus it is expected to allow LLC cacheability to enable coherent
139 * flows to be maintained.
140 * - used to force L3 uncachable cycles.
141 * Thus it is expected to make the surface L3 uncacheable.
144 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
148 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
149 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
151 MOCS_ENTRY(I915_MOCS_CACHED,
152 LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
156 #define GEN11_MOCS_ENTRIES \
157 /* Entries 0 and 1 are defined per-platform */ \
158 /* Base - L3 + LLC */ \
160 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
162 /* Base - Uncached */ \
164 LE_1_UC | LE_TC_1_LLC, \
168 LE_1_UC | LE_TC_1_LLC, \
172 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
176 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
178 /* Age 0 - L3 + LLC */ \
180 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
182 /* Age: Don't Chg. - LLC */ \
184 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
186 /* Age: Don't Chg. - L3 + LLC */ \
188 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
192 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
194 /* No AOM - L3 + LLC */ \
196 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
198 /* No AOM; Age 0 - LLC */ \
200 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
202 /* No AOM; Age 0 - L3 + LLC */ \
204 LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
206 /* No AOM; Age:DC - LLC */ \
208 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
210 /* No AOM; Age:DC - L3 + LLC */ \
212 LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
214 /* Self-Snoop - L3 + LLC */ \
216 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
218 /* Skip Caching - L3 + LLC(12.5%) */ \
220 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
222 /* Skip Caching - L3 + LLC(25%) */ \
224 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
226 /* Skip Caching - L3 + LLC(50%) */ \
228 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
230 /* Skip Caching - L3 + LLC(75%) */ \
232 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
234 /* Skip Caching - L3 + LLC(87.5%) */ \
236 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
238 /* HW Reserved - SW program but never use */ \
240 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
242 /* HW Reserved - SW program but never use */ \
244 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
247 static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
250 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
251 * These reserved entries should never be used, they may be changed
252 * to low performant variants with better coherency in the future if
253 * more entries are needed. We are programming index I915_MOCS_PTE(1)
254 * only, __init_mocs_table() take care to program unused index with
257 MOCS_ENTRY(I915_MOCS_PTE,
258 LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
262 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
264 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
266 /* Implicitly enable L1 - HDC:L1 + L3 */
268 LE_1_UC | LE_TC_1_LLC,
270 /* Implicitly enable L1 - HDC:L1 + LLC */
272 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
274 /* Implicitly enable L1 - HDC:L1 */
276 LE_1_UC | LE_TC_1_LLC,
278 /* HW Special Case (CCS) */
280 LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
282 /* HW Special Case (Displayable) */
284 LE_1_UC | LE_TC_1_LLC,
288 static const struct drm_i915_mocs_entry icl_mocs_table[] = {
289 /* Base - Uncached (Deprecated) */
290 MOCS_ENTRY(I915_MOCS_UNCACHED,
291 LE_1_UC | LE_TC_1_LLC,
293 /* Base - L3 + LeCC:PAT (Deprecated) */
294 MOCS_ENTRY(I915_MOCS_PTE,
295 LE_0_PAGETABLE | LE_TC_1_LLC,
302 HAS_GLOBAL_MOCS = BIT(0),
303 HAS_ENGINE_MOCS = BIT(1),
304 HAS_RENDER_L3CC = BIT(2),
307 static bool has_l3cc(const struct drm_i915_private *i915)
312 static bool has_global_mocs(const struct drm_i915_private *i915)
314 return HAS_GLOBAL_MOCS_REGISTERS(i915);
317 static bool has_mocs(const struct drm_i915_private *i915)
319 return !IS_DGFX(i915);
322 static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
323 struct drm_i915_mocs_table *table)
327 if (INTEL_GEN(i915) >= 12) {
328 table->size = ARRAY_SIZE(tgl_mocs_table);
329 table->table = tgl_mocs_table;
330 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
331 } else if (IS_GEN(i915, 11)) {
332 table->size = ARRAY_SIZE(icl_mocs_table);
333 table->table = icl_mocs_table;
334 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
335 } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
336 table->size = ARRAY_SIZE(skl_mocs_table);
337 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
338 table->table = skl_mocs_table;
339 } else if (IS_GEN9_LP(i915)) {
340 table->size = ARRAY_SIZE(broxton_mocs_table);
341 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
342 table->table = broxton_mocs_table;
344 drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
345 "Platform that should have a MOCS table does not.\n");
349 if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
352 /* WaDisableSkipCaching:skl,bxt,kbl,glk */
353 if (IS_GEN(i915, 9)) {
356 for (i = 0; i < table->size; i++)
357 if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
358 (L3_ESC(1) | L3_SCC(0x7))))
363 if (has_mocs(i915)) {
364 if (has_global_mocs(i915))
365 flags |= HAS_GLOBAL_MOCS;
367 flags |= HAS_ENGINE_MOCS;
370 flags |= HAS_RENDER_L3CC;
376 * Get control_value from MOCS entry taking into account when it's not used:
377 * I915_MOCS_PTE's value is returned in this case.
379 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
382 if (index < table->size && table->table[index].used)
383 return table->table[index].control_value;
385 return table->table[I915_MOCS_PTE].control_value;
388 #define for_each_mocs(mocs, t, i) \
390 i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
393 static void __init_mocs_table(struct intel_uncore *uncore,
394 const struct drm_i915_mocs_table *table,
400 for_each_mocs(mocs, table, i)
401 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
404 static u32 mocs_offset(const struct intel_engine_cs *engine)
406 static const u32 offset[] = {
407 [RCS0] = __GEN9_RCS0_MOCS0,
408 [VCS0] = __GEN9_VCS0_MOCS0,
409 [VCS1] = __GEN9_VCS1_MOCS0,
410 [VECS0] = __GEN9_VECS0_MOCS0,
411 [BCS0] = __GEN9_BCS0_MOCS0,
412 [VCS2] = __GEN11_VCS2_MOCS0,
415 GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
416 return offset[engine->id];
419 static void init_mocs_table(struct intel_engine_cs *engine,
420 const struct drm_i915_mocs_table *table)
422 __init_mocs_table(engine->uncore, table, mocs_offset(engine));
426 * Get l3cc_value from MOCS entry taking into account when it's not used:
427 * I915_MOCS_PTE's value is returned in this case.
429 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
432 if (index < table->size && table->table[index].used)
433 return table->table[index].l3cc_value;
435 return table->table[I915_MOCS_PTE].l3cc_value;
438 static inline u32 l3cc_combine(u16 low, u16 high)
440 return low | (u32)high << 16;
443 #define for_each_l3cc(l3cc, t, i) \
445 i < ((t)->n_entries + 1) / 2 ? \
446 (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
447 get_entry_l3cc((t), 2 * i + 1))), 1 : \
451 static void init_l3cc_table(struct intel_engine_cs *engine,
452 const struct drm_i915_mocs_table *table)
454 struct intel_uncore *uncore = engine->uncore;
458 for_each_l3cc(l3cc, table, i)
459 intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
462 void intel_mocs_init_engine(struct intel_engine_cs *engine)
464 struct drm_i915_mocs_table table;
467 /* Called under a blanket forcewake */
468 assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
470 flags = get_mocs_settings(engine->i915, &table);
474 /* Platforms with global MOCS do not need per-engine initialization. */
475 if (flags & HAS_ENGINE_MOCS)
476 init_mocs_table(engine, &table);
478 if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
479 init_l3cc_table(engine, &table);
482 static u32 global_mocs_offset(void)
484 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
487 void intel_mocs_init(struct intel_gt *gt)
489 struct drm_i915_mocs_table table;
493 * LLC and eDRAM control values are not applicable to dgfx
495 flags = get_mocs_settings(gt->i915, &table);
496 if (flags & HAS_GLOBAL_MOCS)
497 __init_mocs_table(gt->uncore, &table, global_mocs_offset());
500 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
501 #include "selftest_mocs.c"