2 * SPDX-License-Identifier: MIT
4 * Copyright © 2019 Intel Corporation
10 #include "intel_gt_irq.h"
11 #include "intel_gt_pm_irq.h"
13 static void write_pm_imr(struct intel_gt *gt)
15 struct drm_i915_private *i915 = gt->i915;
16 struct intel_uncore *uncore = gt->uncore;
17 u32 mask = gt->pm_imr;
20 if (INTEL_GEN(i915) >= 11) {
21 reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
22 mask <<= 16; /* pm is in upper half */
23 } else if (INTEL_GEN(i915) >= 8) {
29 intel_uncore_write(uncore, reg, mask);
32 static void gen6_gt_pm_update_irq(struct intel_gt *gt,
38 WARN_ON(enabled_irq_mask & ~interrupt_mask);
40 lockdep_assert_held(>->irq_lock);
43 new_val &= ~interrupt_mask;
44 new_val |= ~enabled_irq_mask & interrupt_mask;
46 if (new_val != gt->pm_imr) {
52 void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)
54 gen6_gt_pm_update_irq(gt, mask, mask);
57 void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
59 gen6_gt_pm_update_irq(gt, mask, 0);
62 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
64 struct intel_uncore *uncore = gt->uncore;
65 i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
67 lockdep_assert_held(>->irq_lock);
69 intel_uncore_write(uncore, reg, reset_mask);
70 intel_uncore_write(uncore, reg, reset_mask);
71 intel_uncore_posting_read(uncore, reg);
74 static void write_pm_ier(struct intel_gt *gt)
76 struct drm_i915_private *i915 = gt->i915;
77 struct intel_uncore *uncore = gt->uncore;
78 u32 mask = gt->pm_ier;
81 if (INTEL_GEN(i915) >= 11) {
82 reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
83 mask <<= 16; /* pm is in upper half */
84 } else if (INTEL_GEN(i915) >= 8) {
90 intel_uncore_write(uncore, reg, mask);
93 void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
95 lockdep_assert_held(>->irq_lock);
97 gt->pm_ier |= enable_mask;
99 gen6_gt_pm_unmask_irq(gt, enable_mask);
102 void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
104 lockdep_assert_held(>->irq_lock);
106 gt->pm_ier &= ~disable_mask;
107 gen6_gt_pm_mask_irq(gt, disable_mask);