gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/gpio.h>
  13 #include <linux/io.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19
  20 #include <soc/tegra/pmc.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_dp_helper.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_scdc_helper.h>
  26
  27 #include "dc.h"
  28 #include "drm.h"
  29 #include "sor.h"
  30 #include "trace.h"
  31
  32 /*
  33  * XXX Remove this after the commit adding it to soc/tegra/pmc.h has been
  34  * merged. Having this around after the commit is merged should be safe since
  35  * the preprocessor will effectively replace all occurrences and therefore no
  36  * duplicate will be defined.
  37  */
  38 #define TEGRA_IO_PAD_HDMI_DP0 26
  39
  40 #define SOR_REKEY 0x38
  41
  42 struct tegra_sor_hdmi_settings {
  43         unsigned long frequency;
  44
  45         u8 vcocap;
  46         u8 filter;
  47         u8 ichpmp;
  48         u8 loadadj;
  49         u8 tmds_termadj;
  50         u8 tx_pu_value;
  51         u8 bg_temp_coef;
  52         u8 bg_vref_level;
  53         u8 avdd10_level;
  54         u8 avdd14_level;
  55         u8 sparepll;
  56
  57         u8 drive_current[4];
  58         u8 preemphasis[4];
  59 };
  60
  61 #if 1
  62 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  63         {
  64                 .frequency = 54000000,
  65                 .vcocap = 0x0,
  66                 .filter = 0x0,
  67                 .ichpmp = 0x1,
  68                 .loadadj = 0x3,
  69                 .tmds_termadj = 0x9,
  70                 .tx_pu_value = 0x10,
  71                 .bg_temp_coef = 0x3,
  72                 .bg_vref_level = 0x8,
  73                 .avdd10_level = 0x4,
  74                 .avdd14_level = 0x4,
  75                 .sparepll = 0x0,
  76                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  77                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  78         }, {
  79                 .frequency = 75000000,
  80                 .vcocap = 0x3,
  81                 .filter = 0x0,
  82                 .ichpmp = 0x1,
  83                 .loadadj = 0x3,
  84                 .tmds_termadj = 0x9,
  85                 .tx_pu_value = 0x40,
  86                 .bg_temp_coef = 0x3,
  87                 .bg_vref_level = 0x8,
  88                 .avdd10_level = 0x4,
  89                 .avdd14_level = 0x4,
  90                 .sparepll = 0x0,
  91                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  92                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  93         }, {
  94                 .frequency = 150000000,
  95                 .vcocap = 0x3,
  96                 .filter = 0x0,
  97                 .ichpmp = 0x1,
  98                 .loadadj = 0x3,
  99                 .tmds_termadj = 0x9,
 100                 .tx_pu_value = 0x66,
 101                 .bg_temp_coef = 0x3,
 102                 .bg_vref_level = 0x8,
 103                 .avdd10_level = 0x4,
 104                 .avdd14_level = 0x4,
 105                 .sparepll = 0x0,
 106                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 107                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 108         }, {
 109                 .frequency = 300000000,
 110                 .vcocap = 0x3,
 111                 .filter = 0x0,
 112                 .ichpmp = 0x1,
 113                 .loadadj = 0x3,
 114                 .tmds_termadj = 0x9,
 115                 .tx_pu_value = 0x66,
 116                 .bg_temp_coef = 0x3,
 117                 .bg_vref_level = 0xa,
 118                 .avdd10_level = 0x4,
 119                 .avdd14_level = 0x4,
 120                 .sparepll = 0x0,
 121                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 122                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 123         }, {
 124                 .frequency = 600000000,
 125                 .vcocap = 0x3,
 126                 .filter = 0x0,
 127                 .ichpmp = 0x1,
 128                 .loadadj = 0x3,
 129                 .tmds_termadj = 0x9,
 130                 .tx_pu_value = 0x66,
 131                 .bg_temp_coef = 0x3,
 132                 .bg_vref_level = 0x8,
 133                 .avdd10_level = 0x4,
 134                 .avdd14_level = 0x4,
 135                 .sparepll = 0x0,
 136                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 137                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 138         },
 139 };
 140 #else
 141 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 142         {
 143                 .frequency = 75000000,
 144                 .vcocap = 0x3,
 145                 .filter = 0x0,
 146                 .ichpmp = 0x1,
 147                 .loadadj = 0x3,
 148                 .tmds_termadj = 0x9,
 149                 .tx_pu_value = 0x40,
 150                 .bg_temp_coef = 0x3,
 151                 .bg_vref_level = 0x8,
 152                 .avdd10_level = 0x4,
 153                 .avdd14_level = 0x4,
 154                 .sparepll = 0x0,
 155                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 156                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 157         }, {
 158                 .frequency = 150000000,
 159                 .vcocap = 0x3,
 160                 .filter = 0x0,
 161                 .ichpmp = 0x1,
 162                 .loadadj = 0x3,
 163                 .tmds_termadj = 0x9,
 164                 .tx_pu_value = 0x66,
 165                 .bg_temp_coef = 0x3,
 166                 .bg_vref_level = 0x8,
 167                 .avdd10_level = 0x4,
 168                 .avdd14_level = 0x4,
 169                 .sparepll = 0x0,
 170                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 171                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 172         }, {
 173                 .frequency = 300000000,
 174                 .vcocap = 0x3,
 175                 .filter = 0x0,
 176                 .ichpmp = 0x6,
 177                 .loadadj = 0x3,
 178                 .tmds_termadj = 0x9,
 179                 .tx_pu_value = 0x66,
 180                 .bg_temp_coef = 0x3,
 181                 .bg_vref_level = 0xf,
 182                 .avdd10_level = 0x4,
 183                 .avdd14_level = 0x4,
 184                 .sparepll = 0x0,
 185                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 186                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 187         }, {
 188                 .frequency = 600000000,
 189                 .vcocap = 0x3,
 190                 .filter = 0x0,
 191                 .ichpmp = 0xa,
 192                 .loadadj = 0x3,
 193                 .tmds_termadj = 0xb,
 194                 .tx_pu_value = 0x66,
 195                 .bg_temp_coef = 0x3,
 196                 .bg_vref_level = 0xe,
 197                 .avdd10_level = 0x4,
 198                 .avdd14_level = 0x4,
 199                 .sparepll = 0x0,
 200                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 201                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 202         },
 203 };
 204 #endif
 205
 206 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 207         {
 208                 .frequency = 54000000,
 209                 .vcocap = 0,
 210                 .filter = 5,
 211                 .ichpmp = 5,
 212                 .loadadj = 3,
 213                 .tmds_termadj = 0xf,
 214                 .tx_pu_value = 0,
 215                 .bg_temp_coef = 3,
 216                 .bg_vref_level = 8,
 217                 .avdd10_level = 4,
 218                 .avdd14_level = 4,
 219                 .sparepll = 0x54,
 220                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 221                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 222         }, {
 223                 .frequency = 75000000,
 224                 .vcocap = 1,
 225                 .filter = 5,
 226                 .ichpmp = 5,
 227                 .loadadj = 3,
 228                 .tmds_termadj = 0xf,
 229                 .tx_pu_value = 0,
 230                 .bg_temp_coef = 3,
 231                 .bg_vref_level = 8,
 232                 .avdd10_level = 4,
 233                 .avdd14_level = 4,
 234                 .sparepll = 0x44,
 235                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 236                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 237         }, {
 238                 .frequency = 150000000,
 239                 .vcocap = 3,
 240                 .filter = 5,
 241                 .ichpmp = 5,
 242                 .loadadj = 3,
 243                 .tmds_termadj = 15,
 244                 .tx_pu_value = 0x66 /* 0 */,
 245                 .bg_temp_coef = 3,
 246                 .bg_vref_level = 8,
 247                 .avdd10_level = 4,
 248                 .avdd14_level = 4,
 249                 .sparepll = 0x00, /* 0x34 */
 250                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 251                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 252         }, {
 253                 .frequency = 300000000,
 254                 .vcocap = 3,
 255                 .filter = 5,
 256                 .ichpmp = 5,
 257                 .loadadj = 3,
 258                 .tmds_termadj = 15,
 259                 .tx_pu_value = 64,
 260                 .bg_temp_coef = 3,
 261                 .bg_vref_level = 8,
 262                 .avdd10_level = 4,
 263                 .avdd14_level = 4,
 264                 .sparepll = 0x34,
 265                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 266                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 267         }, {
 268                 .frequency = 600000000,
 269                 .vcocap = 3,
 270                 .filter = 5,
 271                 .ichpmp = 5,
 272                 .loadadj = 3,
 273                 .tmds_termadj = 12,
 274                 .tx_pu_value = 96,
 275                 .bg_temp_coef = 3,
 276                 .bg_vref_level = 8,
 277                 .avdd10_level = 4,
 278                 .avdd14_level = 4,
 279                 .sparepll = 0x34,
 280                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 281                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 282         }
 283 };
 284
 285 struct tegra_sor_regs {
 286         unsigned int head_state0;
 287         unsigned int head_state1;
 288         unsigned int head_state2;
 289         unsigned int head_state3;
 290         unsigned int head_state4;
 291         unsigned int head_state5;
 292         unsigned int pll0;
 293         unsigned int pll1;
 294         unsigned int pll2;
 295         unsigned int pll3;
 296         unsigned int dp_padctl0;
 297         unsigned int dp_padctl2;
 298 };
 299
 300 struct tegra_sor_soc {
 301         bool supports_edp;
 302         bool supports_lvds;
 303         bool supports_hdmi;
 304         bool supports_dp;
 305
 306         const struct tegra_sor_regs *regs;
 307         bool has_nvdisplay;
 308
 309         const struct tegra_sor_hdmi_settings *settings;
 310         unsigned int num_settings;
 311
 312         const u8 *xbar_cfg;
 313 };
 314
 315 struct tegra_sor;
 316
 317 struct tegra_sor_ops {
 318         const char *name;
 319         int (*probe)(struct tegra_sor *sor);
 320         int (*remove)(struct tegra_sor *sor);
 321 };
 322
 323 struct tegra_sor {
 324         struct host1x_client client;
 325         struct tegra_output output;
 326         struct device *dev;
 327
 328         const struct tegra_sor_soc *soc;
 329         void __iomem *regs;
 330         unsigned int index;
 331
 332         struct reset_control *rst;
 333         struct clk *clk_parent;
 334         struct clk *clk_safe;
 335         struct clk *clk_out;
 336         struct clk *clk_pad;
 337         struct clk *clk_dp;
 338         struct clk *clk;
 339
 340         struct drm_dp_aux *aux;
 341
 342         struct drm_info_list *debugfs_files;
 343
 344         const struct tegra_sor_ops *ops;
 345         enum tegra_io_pad pad;
 346
 347         /* for HDMI 2.0 */
 348         struct tegra_sor_hdmi_settings *settings;
 349         unsigned int num_settings;
 350
 351         struct regulator *avdd_io_supply;
 352         struct regulator *vdd_pll_supply;
 353         struct regulator *hdmi_supply;
 354
 355         struct delayed_work scdc;
 356         bool scdc_enabled;
 357 };
 358
 359 struct tegra_sor_state {
 360         struct drm_connector_state base;
 361
 362         unsigned int link_speed;
 363         unsigned long pclk;
 364         unsigned int bpc;
 365 };
 366
 367 static inline struct tegra_sor_state *
 368 to_sor_state(struct drm_connector_state *state)
 369 {
 370         return container_of(state, struct tegra_sor_state, base);
 371 }
 372
 373 struct tegra_sor_config {
 374         u32 bits_per_pixel;
 375
 376         u32 active_polarity;
 377         u32 active_count;
 378         u32 tu_size;
 379         u32 active_frac;
 380         u32 watermark;
 381
 382         u32 hblank_symbols;
 383         u32 vblank_symbols;
 384 };
 385
 386 static inline struct tegra_sor *
 387 host1x_client_to_sor(struct host1x_client *client)
 388 {
 389         return container_of(client, struct tegra_sor, client);
 390 }
 391
 392 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 393 {
 394         return container_of(output, struct tegra_sor, output);
 395 }
 396
 397 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 398 {
 399         u32 value = readl(sor->regs + (offset << 2));
 400
 401         trace_sor_readl(sor->dev, offset, value);
 402
 403         return value;
 404 }
 405
 406 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 407                                     unsigned int offset)
 408 {
 409         trace_sor_writel(sor->dev, offset, value);
 410         writel(value, sor->regs + (offset << 2));
 411 }
 412
 413 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 414 {
 415         int err;
 416
 417         clk_disable_unprepare(sor->clk);
 418
 419         err = clk_set_parent(sor->clk_out, parent);
 420         if (err < 0)
 421                 return err;
 422
 423         err = clk_prepare_enable(sor->clk);
 424         if (err < 0)
 425                 return err;
 426
 427         return 0;
 428 }
 429
 430 struct tegra_clk_sor_pad {
 431         struct clk_hw hw;
 432         struct tegra_sor *sor;
 433 };
 434
 435 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 436 {
 437         return container_of(hw, struct tegra_clk_sor_pad, hw);
 438 }
 439
 440 static const char * const tegra_clk_sor_pad_parents[] = {
 441         "pll_d2_out0", "pll_dp"
 442 };
 443
 444 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 445 {
 446         struct tegra_clk_sor_pad *pad = to_pad(hw);
 447         struct tegra_sor *sor = pad->sor;
 448         u32 value;
 449
 450         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 451         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 452
 453         switch (index) {
 454         case 0:
 455                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 456                 break;
 457
 458         case 1:
 459                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 460                 break;
 461         }
 462
 463         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 464
 465         return 0;
 466 }
 467
 468 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 469 {
 470         struct tegra_clk_sor_pad *pad = to_pad(hw);
 471         struct tegra_sor *sor = pad->sor;
 472         u8 parent = U8_MAX;
 473         u32 value;
 474
 475         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 476
 477         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 478         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 479         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 480                 parent = 0;
 481                 break;
 482
 483         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 484         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 485                 parent = 1;
 486                 break;
 487         }
 488
 489         return parent;
 490 }
 491
 492 static const struct clk_ops tegra_clk_sor_pad_ops = {
 493         .set_parent = tegra_clk_sor_pad_set_parent,
 494         .get_parent = tegra_clk_sor_pad_get_parent,
 495 };
 496
 497 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 498                                               const char *name)
 499 {
 500         struct tegra_clk_sor_pad *pad;
 501         struct clk_init_data init;
 502         struct clk *clk;
 503
 504         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 505         if (!pad)
 506                 return ERR_PTR(-ENOMEM);
 507
 508         pad->sor = sor;
 509
 510         init.name = name;
 511         init.flags = 0;
 512         init.parent_names = tegra_clk_sor_pad_parents;
 513         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
 514         init.ops = &tegra_clk_sor_pad_ops;
 515
 516         pad->hw.init = &init;
 517
 518         clk = devm_clk_register(sor->dev, &pad->hw);
 519
 520         return clk;
 521 }
 522
 523 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 524                                    struct drm_dp_link *link)
 525 {
 526         unsigned int i;
 527         u8 pattern;
 528         u32 value;
 529         int err;
 530
 531         /* setup lane parameters */
 532         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 533                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 534                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 535                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 536         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 537
 538         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 539                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 540                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 541                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 542         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 543
 544         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 545                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 546                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 547                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 548         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 549
 550         /* disable LVDS mode */
 551         tegra_sor_writel(sor, 0, SOR_LVDS);
 552
 553         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 554         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 555         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 556         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 557         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 558
 559         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 560         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 561                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 562         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 563
 564         usleep_range(10, 100);
 565
 566         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 567         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 568                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 569         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 570
 571         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 572         if (err < 0)
 573                 return err;
 574
 575         for (i = 0, value = 0; i < link->num_lanes; i++) {
 576                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 577                                      SOR_DP_TPG_SCRAMBLER_NONE |
 578                                      SOR_DP_TPG_PATTERN_TRAIN1;
 579                 value = (value << 8) | lane;
 580         }
 581
 582         tegra_sor_writel(sor, value, SOR_DP_TPG);
 583
 584         pattern = DP_TRAINING_PATTERN_1;
 585
 586         err = drm_dp_aux_train(sor->aux, link, pattern);
 587         if (err < 0)
 588                 return err;
 589
 590         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 591         value |= SOR_DP_SPARE_SEQ_ENABLE;
 592         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 593         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 594         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 595
 596         for (i = 0, value = 0; i < link->num_lanes; i++) {
 597                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 598                                      SOR_DP_TPG_SCRAMBLER_NONE |
 599                                      SOR_DP_TPG_PATTERN_TRAIN2;
 600                 value = (value << 8) | lane;
 601         }
 602
 603         tegra_sor_writel(sor, value, SOR_DP_TPG);
 604
 605         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 606
 607         err = drm_dp_aux_train(sor->aux, link, pattern);
 608         if (err < 0)
 609                 return err;
 610
 611         for (i = 0, value = 0; i < link->num_lanes; i++) {
 612                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 613                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 614                                      SOR_DP_TPG_PATTERN_NONE;
 615                 value = (value << 8) | lane;
 616         }
 617
 618         tegra_sor_writel(sor, value, SOR_DP_TPG);
 619
 620         pattern = DP_TRAINING_PATTERN_DISABLE;
 621
 622         err = drm_dp_aux_train(sor->aux, link, pattern);
 623         if (err < 0)
 624                 return err;
 625
 626         return 0;
 627 }
 628
 629 static void tegra_sor_super_update(struct tegra_sor *sor)
 630 {
 631         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 632         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 633         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 634 }
 635
 636 static void tegra_sor_update(struct tegra_sor *sor)
 637 {
 638         tegra_sor_writel(sor, 0, SOR_STATE0);
 639         tegra_sor_writel(sor, 1, SOR_STATE0);
 640         tegra_sor_writel(sor, 0, SOR_STATE0);
 641 }
 642
 643 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 644 {
 645         u32 value;
 646
 647         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 648         value &= ~SOR_PWM_DIV_MASK;
 649         value |= 0x400; /* period */
 650         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 651
 652         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 653         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 654         value |= 0x400; /* duty cycle */
 655         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 656         value |= SOR_PWM_CTL_TRIGGER;
 657         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 658
 659         timeout = jiffies + msecs_to_jiffies(timeout);
 660
 661         while (time_before(jiffies, timeout)) {
 662                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 663                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 664                         return 0;
 665
 666                 usleep_range(25, 100);
 667         }
 668
 669         return -ETIMEDOUT;
 670 }
 671
 672 static int tegra_sor_attach(struct tegra_sor *sor)
 673 {
 674         unsigned long value, timeout;
 675
 676         /* wake up in normal mode */
 677         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 678         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 679         value |= SOR_SUPER_STATE_MODE_NORMAL;
 680         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 681         tegra_sor_super_update(sor);
 682
 683         /* attach */
 684         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 685         value |= SOR_SUPER_STATE_ATTACHED;
 686         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 687         tegra_sor_super_update(sor);
 688
 689         timeout = jiffies + msecs_to_jiffies(250);
 690
 691         while (time_before(jiffies, timeout)) {
 692                 value = tegra_sor_readl(sor, SOR_TEST);
 693                 if ((value & SOR_TEST_ATTACHED) != 0)
 694                         return 0;
 695
 696                 usleep_range(25, 100);
 697         }
 698
 699         return -ETIMEDOUT;
 700 }
 701
 702 static int tegra_sor_wakeup(struct tegra_sor *sor)
 703 {
 704         unsigned long value, timeout;
 705
 706         timeout = jiffies + msecs_to_jiffies(250);
 707
 708         /* wait for head to wake up */
 709         while (time_before(jiffies, timeout)) {
 710                 value = tegra_sor_readl(sor, SOR_TEST);
 711                 value &= SOR_TEST_HEAD_MODE_MASK;
 712
 713                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 714                         return 0;
 715
 716                 usleep_range(25, 100);
 717         }
 718
 719         return -ETIMEDOUT;
 720 }
 721
 722 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 723 {
 724         u32 value;
 725
 726         value = tegra_sor_readl(sor, SOR_PWR);
 727         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 728         tegra_sor_writel(sor, value, SOR_PWR);
 729
 730         timeout = jiffies + msecs_to_jiffies(timeout);
 731
 732         while (time_before(jiffies, timeout)) {
 733                 value = tegra_sor_readl(sor, SOR_PWR);
 734                 if ((value & SOR_PWR_TRIGGER) == 0)
 735                         return 0;
 736
 737                 usleep_range(25, 100);
 738         }
 739
 740         return -ETIMEDOUT;
 741 }
 742
 743 struct tegra_sor_params {
 744         /* number of link clocks per line */
 745         unsigned int num_clocks;
 746         /* ratio between input and output */
 747         u64 ratio;
 748         /* precision factor */
 749         u64 precision;
 750
 751         unsigned int active_polarity;
 752         unsigned int active_count;
 753         unsigned int active_frac;
 754         unsigned int tu_size;
 755         unsigned int error;
 756 };
 757
 758 static int tegra_sor_compute_params(struct tegra_sor *sor,
 759                                     struct tegra_sor_params *params,
 760                                     unsigned int tu_size)
 761 {
 762         u64 active_sym, active_count, frac, approx;
 763         u32 active_polarity, active_frac = 0;
 764         const u64 f = params->precision;
 765         s64 error;
 766
 767         active_sym = params->ratio * tu_size;
 768         active_count = div_u64(active_sym, f) * f;
 769         frac = active_sym - active_count;
 770
 771         /* fraction < 0.5 */
 772         if (frac >= (f / 2)) {
 773                 active_polarity = 1;
 774                 frac = f - frac;
 775         } else {
 776                 active_polarity = 0;
 777         }
 778
 779         if (frac != 0) {
 780                 frac = div_u64(f * f,  frac); /* 1/fraction */
 781                 if (frac <= (15 * f)) {
 782                         active_frac = div_u64(frac, f);
 783
 784                         /* round up */
 785                         if (active_polarity)
 786                                 active_frac++;
 787                 } else {
 788                         active_frac = active_polarity ? 1 : 15;
 789                 }
 790         }
 791
 792         if (active_frac == 1)
 793                 active_polarity = 0;
 794
 795         if (active_polarity == 1) {
 796                 if (active_frac) {
 797                         approx = active_count + (active_frac * (f - 1)) * f;
 798                         approx = div_u64(approx, active_frac * f);
 799                 } else {
 800                         approx = active_count + f;
 801                 }
 802         } else {
 803                 if (active_frac)
 804                         approx = active_count + div_u64(f, active_frac);
 805                 else
 806                         approx = active_count;
 807         }
 808
 809         error = div_s64(active_sym - approx, tu_size);
 810         error *= params->num_clocks;
 811
 812         if (error <= 0 && abs(error) < params->error) {
 813                 params->active_count = div_u64(active_count, f);
 814                 params->active_polarity = active_polarity;
 815                 params->active_frac = active_frac;
 816                 params->error = abs(error);
 817                 params->tu_size = tu_size;
 818
 819                 if (error == 0)
 820                         return true;
 821         }
 822
 823         return false;
 824 }
 825
 826 static int tegra_sor_compute_config(struct tegra_sor *sor,
 827                                     const struct drm_display_mode *mode,
 828                                     struct tegra_sor_config *config,
 829                                     struct drm_dp_link *link)
 830 {
 831         const u64 f = 100000, link_rate = link->rate * 1000;
 832         const u64 pclk = mode->clock * 1000;
 833         u64 input, output, watermark, num;
 834         struct tegra_sor_params params;
 835         u32 num_syms_per_line;
 836         unsigned int i;
 837
 838         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 839                 return -EINVAL;
 840
 841         output = link_rate * 8 * link->num_lanes;
 842         input = pclk * config->bits_per_pixel;
 843
 844         if (input >= output)
 845                 return -ERANGE;
 846
 847         memset(&params, 0, sizeof(params));
 848         params.ratio = div64_u64(input * f, output);
 849         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 850         params.precision = f;
 851         params.error = 64 * f;
 852         params.tu_size = 64;
 853
 854         for (i = params.tu_size; i >= 32; i--)
 855                 if (tegra_sor_compute_params(sor, &params, i))
 856                         break;
 857
 858         if (params.active_frac == 0) {
 859                 config->active_polarity = 0;
 860                 config->active_count = params.active_count;
 861
 862                 if (!params.active_polarity)
 863                         config->active_count--;
 864
 865                 config->tu_size = params.tu_size;
 866                 config->active_frac = 1;
 867         } else {
 868                 config->active_polarity = params.active_polarity;
 869                 config->active_count = params.active_count;
 870                 config->active_frac = params.active_frac;
 871                 config->tu_size = params.tu_size;
 872         }
 873
 874         dev_dbg(sor->dev,
 875                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 876                 config->active_polarity, config->active_count,
 877                 config->tu_size, config->active_frac);
 878
 879         watermark = params.ratio * config->tu_size * (f - params.ratio);
 880         watermark = div_u64(watermark, f);
 881
 882         watermark = div_u64(watermark + params.error, f);
 883         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 884         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 885                             (link->num_lanes * 8);
 886
 887         if (config->watermark > 30) {
 888                 config->watermark = 30;
 889                 dev_err(sor->dev,
 890                         "unable to compute TU size, forcing watermark to %u\n",
 891                         config->watermark);
 892         } else if (config->watermark > num_syms_per_line) {
 893                 config->watermark = num_syms_per_line;
 894                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 895                         config->watermark);
 896         }
 897
 898         /* compute the number of symbols per horizontal blanking interval */
 899         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 900         config->hblank_symbols = div_u64(num, pclk);
 901
 902         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 903                 config->hblank_symbols -= 3;
 904
 905         config->hblank_symbols -= 12 / link->num_lanes;
 906
 907         /* compute the number of symbols per vertical blanking interval */
 908         num = (mode->hdisplay - 25) * link_rate;
 909         config->vblank_symbols = div_u64(num, pclk);
 910         config->vblank_symbols -= 36 / link->num_lanes + 4;
 911
 912         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 913                 config->vblank_symbols);
 914
 915         return 0;
 916 }
 917
 918 static void tegra_sor_apply_config(struct tegra_sor *sor,
 919                                    const struct tegra_sor_config *config)
 920 {
 921         u32 value;
 922
 923         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 924         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 925         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
 926         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 927
 928         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
 929         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
 930         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
 931
 932         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
 933         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
 934
 935         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
 936         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
 937
 938         if (config->active_polarity)
 939                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 940         else
 941                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 942
 943         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
 944         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
 945         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
 946
 947         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 948         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
 949         value |= config->hblank_symbols & 0xffff;
 950         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 951
 952         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 953         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
 954         value |= config->vblank_symbols & 0xffff;
 955         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 956 }
 957
 958 static void tegra_sor_mode_set(struct tegra_sor *sor,
 959                                const struct drm_display_mode *mode,
 960                                struct tegra_sor_state *state)
 961 {
 962         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
 963         unsigned int vbe, vse, hbe, hse, vbs, hbs;
 964         u32 value;
 965
 966         value = tegra_sor_readl(sor, SOR_STATE1);
 967         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
 968         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 969         value &= ~SOR_STATE_ASY_OWNER_MASK;
 970
 971         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
 972                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
 973
 974         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 975                 value &= ~SOR_STATE_ASY_HSYNCPOL;
 976
 977         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 978                 value |= SOR_STATE_ASY_HSYNCPOL;
 979
 980         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 981                 value &= ~SOR_STATE_ASY_VSYNCPOL;
 982
 983         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 984                 value |= SOR_STATE_ASY_VSYNCPOL;
 985
 986         switch (state->bpc) {
 987         case 16:
 988                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
 989                 break;
 990
 991         case 12:
 992                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
 993                 break;
 994
 995         case 10:
 996                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
 997                 break;
 998
 999         case 8:
1000                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1001                 break;
1002
1003         case 6:
1004                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1005                 break;
1006
1007         default:
1008                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1009                 break;
1010         }
1011
1012         tegra_sor_writel(sor, value, SOR_STATE1);
1013
1014         /*
1015          * TODO: The video timing programming below doesn't seem to match the
1016          * register definitions.
1017          */
1018
1019         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1020         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1021
1022         /* sync end = sync width - 1 */
1023         vse = mode->vsync_end - mode->vsync_start - 1;
1024         hse = mode->hsync_end - mode->hsync_start - 1;
1025
1026         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1027         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1028
1029         /* blank end = sync end + back porch */
1030         vbe = vse + (mode->vtotal - mode->vsync_end);
1031         hbe = hse + (mode->htotal - mode->hsync_end);
1032
1033         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1034         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1035
1036         /* blank start = blank end + active */
1037         vbs = vbe + mode->vdisplay;
1038         hbs = hbe + mode->hdisplay;
1039
1040         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1041         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1042
1043         /* XXX interlacing support */
1044         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1045 }
1046
1047 static int tegra_sor_detach(struct tegra_sor *sor)
1048 {
1049         unsigned long value, timeout;
1050
1051         /* switch to safe mode */
1052         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1053         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1054         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1055         tegra_sor_super_update(sor);
1056
1057         timeout = jiffies + msecs_to_jiffies(250);
1058
1059         while (time_before(jiffies, timeout)) {
1060                 value = tegra_sor_readl(sor, SOR_PWR);
1061                 if (value & SOR_PWR_MODE_SAFE)
1062                         break;
1063         }
1064
1065         if ((value & SOR_PWR_MODE_SAFE) == 0)
1066                 return -ETIMEDOUT;
1067
1068         /* go to sleep */
1069         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1070         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1071         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1072         tegra_sor_super_update(sor);
1073
1074         /* detach */
1075         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1076         value &= ~SOR_SUPER_STATE_ATTACHED;
1077         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1078         tegra_sor_super_update(sor);
1079
1080         timeout = jiffies + msecs_to_jiffies(250);
1081
1082         while (time_before(jiffies, timeout)) {
1083                 value = tegra_sor_readl(sor, SOR_TEST);
1084                 if ((value & SOR_TEST_ATTACHED) == 0)
1085                         break;
1086
1087                 usleep_range(25, 100);
1088         }
1089
1090         if ((value & SOR_TEST_ATTACHED) != 0)
1091                 return -ETIMEDOUT;
1092
1093         return 0;
1094 }
1095
1096 static int tegra_sor_power_down(struct tegra_sor *sor)
1097 {
1098         unsigned long value, timeout;
1099         int err;
1100
1101         value = tegra_sor_readl(sor, SOR_PWR);
1102         value &= ~SOR_PWR_NORMAL_STATE_PU;
1103         value |= SOR_PWR_TRIGGER;
1104         tegra_sor_writel(sor, value, SOR_PWR);
1105
1106         timeout = jiffies + msecs_to_jiffies(250);
1107
1108         while (time_before(jiffies, timeout)) {
1109                 value = tegra_sor_readl(sor, SOR_PWR);
1110                 if ((value & SOR_PWR_TRIGGER) == 0)
1111                         return 0;
1112
1113                 usleep_range(25, 100);
1114         }
1115
1116         if ((value & SOR_PWR_TRIGGER) != 0)
1117                 return -ETIMEDOUT;
1118
1119         /* switch to safe parent clock */
1120         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1121         if (err < 0) {
1122                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1123                 return err;
1124         }
1125
1126         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1127         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1128                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1129         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1130
1131         /* stop lane sequencer */
1132         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1133                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1134         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1135
1136         timeout = jiffies + msecs_to_jiffies(250);
1137
1138         while (time_before(jiffies, timeout)) {
1139                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1140                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1141                         break;
1142
1143                 usleep_range(25, 100);
1144         }
1145
1146         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1147                 return -ETIMEDOUT;
1148
1149         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1150         value |= SOR_PLL2_PORT_POWERDOWN;
1151         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1152
1153         usleep_range(20, 100);
1154
1155         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1156         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1157         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1158
1159         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1160         value |= SOR_PLL2_SEQ_PLLCAPPD;
1161         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1162         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1163
1164         usleep_range(20, 100);
1165
1166         return 0;
1167 }
1168
1169 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1170 {
1171         u32 value;
1172
1173         timeout = jiffies + msecs_to_jiffies(timeout);
1174
1175         while (time_before(jiffies, timeout)) {
1176                 value = tegra_sor_readl(sor, SOR_CRCA);
1177                 if (value & SOR_CRCA_VALID)
1178                         return 0;
1179
1180                 usleep_range(100, 200);
1181         }
1182
1183         return -ETIMEDOUT;
1184 }
1185
1186 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1187 {
1188         struct drm_info_node *node = s->private;
1189         struct tegra_sor *sor = node->info_ent->data;
1190         struct drm_crtc *crtc = sor->output.encoder.crtc;
1191         struct drm_device *drm = node->minor->dev;
1192         int err = 0;
1193         u32 value;
1194
1195         drm_modeset_lock_all(drm);
1196
1197         if (!crtc || !crtc->state->active) {
1198                 err = -EBUSY;
1199                 goto unlock;
1200         }
1201
1202         value = tegra_sor_readl(sor, SOR_STATE1);
1203         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1204         tegra_sor_writel(sor, value, SOR_STATE1);
1205
1206         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1207         value |= SOR_CRC_CNTRL_ENABLE;
1208         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1209
1210         value = tegra_sor_readl(sor, SOR_TEST);
1211         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1212         tegra_sor_writel(sor, value, SOR_TEST);
1213
1214         err = tegra_sor_crc_wait(sor, 100);
1215         if (err < 0)
1216                 goto unlock;
1217
1218         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1219         value = tegra_sor_readl(sor, SOR_CRCB);
1220
1221         seq_printf(s, "%08x\n", value);
1222
1223 unlock:
1224         drm_modeset_unlock_all(drm);
1225         return err;
1226 }
1227
1228 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1229
1230 static const struct debugfs_reg32 tegra_sor_regs[] = {
1231         DEBUGFS_REG32(SOR_CTXSW),
1232         DEBUGFS_REG32(SOR_SUPER_STATE0),
1233         DEBUGFS_REG32(SOR_SUPER_STATE1),
1234         DEBUGFS_REG32(SOR_STATE0),
1235         DEBUGFS_REG32(SOR_STATE1),
1236         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1237         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1238         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1239         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1240         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1241         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1242         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1243         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1244         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1245         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1246         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1247         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1248         DEBUGFS_REG32(SOR_CRC_CNTRL),
1249         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1250         DEBUGFS_REG32(SOR_CLK_CNTRL),
1251         DEBUGFS_REG32(SOR_CAP),
1252         DEBUGFS_REG32(SOR_PWR),
1253         DEBUGFS_REG32(SOR_TEST),
1254         DEBUGFS_REG32(SOR_PLL0),
1255         DEBUGFS_REG32(SOR_PLL1),
1256         DEBUGFS_REG32(SOR_PLL2),
1257         DEBUGFS_REG32(SOR_PLL3),
1258         DEBUGFS_REG32(SOR_CSTM),
1259         DEBUGFS_REG32(SOR_LVDS),
1260         DEBUGFS_REG32(SOR_CRCA),
1261         DEBUGFS_REG32(SOR_CRCB),
1262         DEBUGFS_REG32(SOR_BLANK),
1263         DEBUGFS_REG32(SOR_SEQ_CTL),
1264         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1265         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1266         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1267         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1268         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1269         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1270         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1271         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1272         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1273         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1274         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1275         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1276         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1277         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1278         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1279         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1280         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1281         DEBUGFS_REG32(SOR_PWM_DIV),
1282         DEBUGFS_REG32(SOR_PWM_CTL),
1283         DEBUGFS_REG32(SOR_VCRC_A0),
1284         DEBUGFS_REG32(SOR_VCRC_A1),
1285         DEBUGFS_REG32(SOR_VCRC_B0),
1286         DEBUGFS_REG32(SOR_VCRC_B1),
1287         DEBUGFS_REG32(SOR_CCRC_A0),
1288         DEBUGFS_REG32(SOR_CCRC_A1),
1289         DEBUGFS_REG32(SOR_CCRC_B0),
1290         DEBUGFS_REG32(SOR_CCRC_B1),
1291         DEBUGFS_REG32(SOR_EDATA_A0),
1292         DEBUGFS_REG32(SOR_EDATA_A1),
1293         DEBUGFS_REG32(SOR_EDATA_B0),
1294         DEBUGFS_REG32(SOR_EDATA_B1),
1295         DEBUGFS_REG32(SOR_COUNT_A0),
1296         DEBUGFS_REG32(SOR_COUNT_A1),
1297         DEBUGFS_REG32(SOR_COUNT_B0),
1298         DEBUGFS_REG32(SOR_COUNT_B1),
1299         DEBUGFS_REG32(SOR_DEBUG_A0),
1300         DEBUGFS_REG32(SOR_DEBUG_A1),
1301         DEBUGFS_REG32(SOR_DEBUG_B0),
1302         DEBUGFS_REG32(SOR_DEBUG_B1),
1303         DEBUGFS_REG32(SOR_TRIG),
1304         DEBUGFS_REG32(SOR_MSCHECK),
1305         DEBUGFS_REG32(SOR_XBAR_CTRL),
1306         DEBUGFS_REG32(SOR_XBAR_POL),
1307         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1308         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1309         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1310         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1311         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1312         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1313         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1314         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1315         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1316         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1317         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1318         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1319         DEBUGFS_REG32(SOR_DP_CONFIG0),
1320         DEBUGFS_REG32(SOR_DP_CONFIG1),
1321         DEBUGFS_REG32(SOR_DP_MN0),
1322         DEBUGFS_REG32(SOR_DP_MN1),
1323         DEBUGFS_REG32(SOR_DP_PADCTL0),
1324         DEBUGFS_REG32(SOR_DP_PADCTL1),
1325         DEBUGFS_REG32(SOR_DP_PADCTL2),
1326         DEBUGFS_REG32(SOR_DP_DEBUG0),
1327         DEBUGFS_REG32(SOR_DP_DEBUG1),
1328         DEBUGFS_REG32(SOR_DP_SPARE0),
1329         DEBUGFS_REG32(SOR_DP_SPARE1),
1330         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1331         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1332         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1333         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1334         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1335         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1336         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1337         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1338         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1339         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1340         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1341         DEBUGFS_REG32(SOR_DP_TPG),
1342         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1343         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1344         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1345         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1346 };
1347
1348 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1349 {
1350         struct drm_info_node *node = s->private;
1351         struct tegra_sor *sor = node->info_ent->data;
1352         struct drm_crtc *crtc = sor->output.encoder.crtc;
1353         struct drm_device *drm = node->minor->dev;
1354         unsigned int i;
1355         int err = 0;
1356
1357         drm_modeset_lock_all(drm);
1358
1359         if (!crtc || !crtc->state->active) {
1360                 err = -EBUSY;
1361                 goto unlock;
1362         }
1363
1364         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1365                 unsigned int offset = tegra_sor_regs[i].offset;
1366
1367                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1368                            offset, tegra_sor_readl(sor, offset));
1369         }
1370
1371 unlock:
1372         drm_modeset_unlock_all(drm);
1373         return err;
1374 }
1375
1376 static const struct drm_info_list debugfs_files[] = {
1377         { "crc", tegra_sor_show_crc, 0, NULL },
1378         { "regs", tegra_sor_show_regs, 0, NULL },
1379 };
1380
1381 static int tegra_sor_late_register(struct drm_connector *connector)
1382 {
1383         struct tegra_output *output = connector_to_output(connector);
1384         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1385         struct drm_minor *minor = connector->dev->primary;
1386         struct dentry *root = connector->debugfs_entry;
1387         struct tegra_sor *sor = to_sor(output);
1388         int err;
1389
1390         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1391                                      GFP_KERNEL);
1392         if (!sor->debugfs_files)
1393                 return -ENOMEM;
1394
1395         for (i = 0; i < count; i++)
1396                 sor->debugfs_files[i].data = sor;
1397
1398         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1399         if (err < 0)
1400                 goto free;
1401
1402         return 0;
1403
1404 free:
1405         kfree(sor->debugfs_files);
1406         sor->debugfs_files = NULL;
1407
1408         return err;
1409 }
1410
1411 static void tegra_sor_early_unregister(struct drm_connector *connector)
1412 {
1413         struct tegra_output *output = connector_to_output(connector);
1414         unsigned int count = ARRAY_SIZE(debugfs_files);
1415         struct tegra_sor *sor = to_sor(output);
1416
1417         drm_debugfs_remove_files(sor->debugfs_files, count,
1418                                  connector->dev->primary);
1419         kfree(sor->debugfs_files);
1420         sor->debugfs_files = NULL;
1421 }
1422
1423 static void tegra_sor_connector_reset(struct drm_connector *connector)
1424 {
1425         struct tegra_sor_state *state;
1426
1427         state = kzalloc(sizeof(*state), GFP_KERNEL);
1428         if (!state)
1429                 return;
1430
1431         if (connector->state) {
1432                 __drm_atomic_helper_connector_destroy_state(connector->state);
1433                 kfree(connector->state);
1434         }
1435
1436         __drm_atomic_helper_connector_reset(connector, &state->base);
1437 }
1438
1439 static enum drm_connector_status
1440 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1441 {
1442         struct tegra_output *output = connector_to_output(connector);
1443         struct tegra_sor *sor = to_sor(output);
1444
1445         if (sor->aux)
1446                 return drm_dp_aux_detect(sor->aux);
1447
1448         return tegra_output_connector_detect(connector, force);
1449 }
1450
1451 static struct drm_connector_state *
1452 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1453 {
1454         struct tegra_sor_state *state = to_sor_state(connector->state);
1455         struct tegra_sor_state *copy;
1456
1457         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1458         if (!copy)
1459                 return NULL;
1460
1461         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1462
1463         return &copy->base;
1464 }
1465
1466 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1467         .reset = tegra_sor_connector_reset,
1468         .detect = tegra_sor_connector_detect,
1469         .fill_modes = drm_helper_probe_single_connector_modes,
1470         .destroy = tegra_output_connector_destroy,
1471         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1472         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1473         .late_register = tegra_sor_late_register,
1474         .early_unregister = tegra_sor_early_unregister,
1475 };
1476
1477 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1478 {
1479         struct tegra_output *output = connector_to_output(connector);
1480         struct tegra_sor *sor = to_sor(output);
1481         int err;
1482
1483         if (sor->aux)
1484                 drm_dp_aux_enable(sor->aux);
1485
1486         err = tegra_output_connector_get_modes(connector);
1487
1488         if (sor->aux)
1489                 drm_dp_aux_disable(sor->aux);
1490
1491         return err;
1492 }
1493
1494 static enum drm_mode_status
1495 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1496                                struct drm_display_mode *mode)
1497 {
1498         return MODE_OK;
1499 }
1500
1501 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1502         .get_modes = tegra_sor_connector_get_modes,
1503         .mode_valid = tegra_sor_connector_mode_valid,
1504 };
1505
1506 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1507         .destroy = tegra_output_encoder_destroy,
1508 };
1509
1510 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1511 {
1512         struct tegra_output *output = encoder_to_output(encoder);
1513         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1514         struct tegra_sor *sor = to_sor(output);
1515         u32 value;
1516         int err;
1517
1518         if (output->panel)
1519                 drm_panel_disable(output->panel);
1520
1521         err = tegra_sor_detach(sor);
1522         if (err < 0)
1523                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1524
1525         tegra_sor_writel(sor, 0, SOR_STATE1);
1526         tegra_sor_update(sor);
1527
1528         /*
1529          * The following accesses registers of the display controller, so make
1530          * sure it's only executed when the output is attached to one.
1531          */
1532         if (dc) {
1533                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1534                 value &= ~SOR_ENABLE(0);
1535                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1536
1537                 tegra_dc_commit(dc);
1538         }
1539
1540         err = tegra_sor_power_down(sor);
1541         if (err < 0)
1542                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1543
1544         if (sor->aux) {
1545                 err = drm_dp_aux_disable(sor->aux);
1546                 if (err < 0)
1547                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1548         }
1549
1550         err = tegra_io_pad_power_disable(sor->pad);
1551         if (err < 0)
1552                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1553
1554         if (output->panel)
1555                 drm_panel_unprepare(output->panel);
1556
1557         pm_runtime_put(sor->dev);
1558 }
1559
1560 #if 0
1561 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1562                               unsigned int *value)
1563 {
1564         unsigned int hfp, hsw, hbp, a = 0, b;
1565
1566         hfp = mode->hsync_start - mode->hdisplay;
1567         hsw = mode->hsync_end - mode->hsync_start;
1568         hbp = mode->htotal - mode->hsync_end;
1569
1570         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1571
1572         b = hfp - 1;
1573
1574         pr_info("a: %u, b: %u\n", a, b);
1575         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1576
1577         if (a + hsw + hbp <= 11) {
1578                 a = 1 + 11 - hsw - hbp;
1579                 pr_info("a: %u\n", a);
1580         }
1581
1582         if (a > b)
1583                 return -EINVAL;
1584
1585         if (hsw < 1)
1586                 return -EINVAL;
1587
1588         if (mode->hdisplay < 16)
1589                 return -EINVAL;
1590
1591         if (value) {
1592                 if (b > a && a % 2)
1593                         *value = a + 1;
1594                 else
1595                         *value = a;
1596         }
1597
1598         return 0;
1599 }
1600 #endif
1601
1602 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1603 {
1604         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1605         struct tegra_output *output = encoder_to_output(encoder);
1606         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1607         struct tegra_sor *sor = to_sor(output);
1608         struct tegra_sor_config config;
1609         struct tegra_sor_state *state;
1610         struct drm_dp_link link;
1611         u8 rate, lanes;
1612         unsigned int i;
1613         int err = 0;
1614         u32 value;
1615
1616         state = to_sor_state(output->connector.state);
1617
1618         pm_runtime_get_sync(sor->dev);
1619
1620         if (output->panel)
1621                 drm_panel_prepare(output->panel);
1622
1623         err = drm_dp_aux_enable(sor->aux);
1624         if (err < 0)
1625                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1626
1627         err = drm_dp_link_probe(sor->aux, &link);
1628         if (err < 0) {
1629                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1630                 return;
1631         }
1632
1633         /* switch to safe parent clock */
1634         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1635         if (err < 0)
1636                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1637
1638         memset(&config, 0, sizeof(config));
1639         config.bits_per_pixel = state->bpc * 3;
1640
1641         err = tegra_sor_compute_config(sor, mode, &config, &link);
1642         if (err < 0)
1643                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1644
1645         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1646         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1647         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1648         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1649
1650         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1651         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1652         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1653         usleep_range(20, 100);
1654
1655         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1656         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1657         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1658
1659         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1660                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1661         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1662
1663         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1664         value |= SOR_PLL2_SEQ_PLLCAPPD;
1665         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1666         value |= SOR_PLL2_LVDS_ENABLE;
1667         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1668
1669         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1670         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1671
1672         while (true) {
1673                 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1674                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1675                         break;
1676
1677                 usleep_range(250, 1000);
1678         }
1679
1680         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1681         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1682         value &= ~SOR_PLL2_PORT_POWERDOWN;
1683         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1684
1685         /*
1686          * power up
1687          */
1688
1689         /* set safe link bandwidth (1.62 Gbps) */
1690         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1691         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1692         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1693         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1694
1695         /* step 1 */
1696         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1697         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1698                  SOR_PLL2_BANDGAP_POWERDOWN;
1699         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1700
1701         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1702         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1703         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1704
1705         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1706         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1707         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1708
1709         /* step 2 */
1710         err = tegra_io_pad_power_enable(sor->pad);
1711         if (err < 0)
1712                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1713
1714         usleep_range(5, 100);
1715
1716         /* step 3 */
1717         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1718         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1719         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1720
1721         usleep_range(20, 100);
1722
1723         /* step 4 */
1724         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1725         value &= ~SOR_PLL0_VCOPD;
1726         value &= ~SOR_PLL0_PWR;
1727         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1728
1729         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1730         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1731         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1732
1733         usleep_range(200, 1000);
1734
1735         /* step 5 */
1736         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1737         value &= ~SOR_PLL2_PORT_POWERDOWN;
1738         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1739
1740         /* XXX not in TRM */
1741         for (value = 0, i = 0; i < 5; i++)
1742                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1743                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1744
1745         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1746         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1747
1748         /* switch to DP parent clock */
1749         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1750         if (err < 0)
1751                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1752
1753         /* power DP lanes */
1754         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1755
1756         if (link.num_lanes <= 2)
1757                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1758         else
1759                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1760
1761         if (link.num_lanes <= 1)
1762                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1763         else
1764                 value |= SOR_DP_PADCTL_PD_TXD_1;
1765
1766         if (link.num_lanes == 0)
1767                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1768         else
1769                 value |= SOR_DP_PADCTL_PD_TXD_0;
1770
1771         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1772
1773         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1774         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1775         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1776         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1777
1778         /* start lane sequencer */
1779         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1780                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1781         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1782
1783         while (true) {
1784                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1785                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1786                         break;
1787
1788                 usleep_range(250, 1000);
1789         }
1790
1791         /* set link bandwidth */
1792         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1793         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1794         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1795         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1796
1797         tegra_sor_apply_config(sor, &config);
1798
1799         /* enable link */
1800         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1801         value |= SOR_DP_LINKCTL_ENABLE;
1802         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1803         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1804
1805         for (i = 0, value = 0; i < 4; i++) {
1806                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1807                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1808                                      SOR_DP_TPG_PATTERN_NONE;
1809                 value = (value << 8) | lane;
1810         }
1811
1812         tegra_sor_writel(sor, value, SOR_DP_TPG);
1813
1814         /* enable pad calibration logic */
1815         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1816         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1817         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1818
1819         err = drm_dp_link_probe(sor->aux, &link);
1820         if (err < 0)
1821                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1822
1823         err = drm_dp_link_power_up(sor->aux, &link);
1824         if (err < 0)
1825                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1826
1827         err = drm_dp_link_configure(sor->aux, &link);
1828         if (err < 0)
1829                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1830
1831         rate = drm_dp_link_rate_to_bw_code(link.rate);
1832         lanes = link.num_lanes;
1833
1834         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1835         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1836         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1837         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1838
1839         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1840         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1841         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1842
1843         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1844                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1845
1846         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1847
1848         /* disable training pattern generator */
1849
1850         for (i = 0; i < link.num_lanes; i++) {
1851                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1852                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1853                                      SOR_DP_TPG_PATTERN_NONE;
1854                 value = (value << 8) | lane;
1855         }
1856
1857         tegra_sor_writel(sor, value, SOR_DP_TPG);
1858
1859         err = tegra_sor_dp_train_fast(sor, &link);
1860         if (err < 0)
1861                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1862
1863         dev_dbg(sor->dev, "fast link training succeeded\n");
1864
1865         err = tegra_sor_power_up(sor, 250);
1866         if (err < 0)
1867                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1868
1869         /* CSTM (LVDS, link A/B, upper) */
1870         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1871                 SOR_CSTM_UPPER;
1872         tegra_sor_writel(sor, value, SOR_CSTM);
1873
1874         /* use DP-A protocol */
1875         value = tegra_sor_readl(sor, SOR_STATE1);
1876         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1877         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1878         tegra_sor_writel(sor, value, SOR_STATE1);
1879
1880         tegra_sor_mode_set(sor, mode, state);
1881
1882         /* PWM setup */
1883         err = tegra_sor_setup_pwm(sor, 250);
1884         if (err < 0)
1885                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1886
1887         tegra_sor_update(sor);
1888
1889         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1890         value |= SOR_ENABLE(0);
1891         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1892
1893         tegra_dc_commit(dc);
1894
1895         err = tegra_sor_attach(sor);
1896         if (err < 0)
1897                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1898
1899         err = tegra_sor_wakeup(sor);
1900         if (err < 0)
1901                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1902
1903         if (output->panel)
1904                 drm_panel_enable(output->panel);
1905 }
1906
1907 static int
1908 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1909                                struct drm_crtc_state *crtc_state,
1910                                struct drm_connector_state *conn_state)
1911 {
1912         struct tegra_output *output = encoder_to_output(encoder);
1913         struct tegra_sor_state *state = to_sor_state(conn_state);
1914         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1915         unsigned long pclk = crtc_state->mode.clock * 1000;
1916         struct tegra_sor *sor = to_sor(output);
1917         struct drm_display_info *info;
1918         int err;
1919
1920         info = &output->connector.display_info;
1921
1922         /*
1923          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1924          * the pixel clock must be corrected accordingly.
1925          */
1926         if (pclk >= 340000000) {
1927                 state->link_speed = 20;
1928                 state->pclk = pclk / 2;
1929         } else {
1930                 state->link_speed = 10;
1931                 state->pclk = pclk;
1932         }
1933
1934         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1935                                          pclk, 0);
1936         if (err < 0) {
1937                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1938                 return err;
1939         }
1940
1941         switch (info->bpc) {
1942         case 8:
1943         case 6:
1944                 state->bpc = info->bpc;
1945                 break;
1946
1947         default:
1948                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1949                 state->bpc = 8;
1950                 break;
1951         }
1952
1953         return 0;
1954 }
1955
1956 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1957         .disable = tegra_sor_edp_disable,
1958         .enable = tegra_sor_edp_enable,
1959         .atomic_check = tegra_sor_encoder_atomic_check,
1960 };
1961
1962 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1963 {
1964         u32 value = 0;
1965         size_t i;
1966
1967         for (i = size; i > 0; i--)
1968                 value = (value << 8) | ptr[i - 1];
1969
1970         return value;
1971 }
1972
1973 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1974                                           const void *data, size_t size)
1975 {
1976         const u8 *ptr = data;
1977         unsigned long offset;
1978         size_t i, j;
1979         u32 value;
1980
1981         switch (ptr[0]) {
1982         case HDMI_INFOFRAME_TYPE_AVI:
1983                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1984                 break;
1985
1986         case HDMI_INFOFRAME_TYPE_AUDIO:
1987                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1988                 break;
1989
1990         case HDMI_INFOFRAME_TYPE_VENDOR:
1991                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1992                 break;
1993
1994         default:
1995                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1996                         ptr[0]);
1997                 return;
1998         }
1999
2000         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2001                 INFOFRAME_HEADER_VERSION(ptr[1]) |
2002                 INFOFRAME_HEADER_LEN(ptr[2]);
2003         tegra_sor_writel(sor, value, offset);
2004         offset++;
2005
2006         /*
2007          * Each subpack contains 7 bytes, divided into:
2008          * - subpack_low: bytes 0 - 3
2009          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2010          */
2011         for (i = 3, j = 0; i < size; i += 7, j += 8) {
2012                 size_t rem = size - i, num = min_t(size_t, rem, 4);
2013
2014                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2015                 tegra_sor_writel(sor, value, offset++);
2016
2017                 num = min_t(size_t, rem - num, 3);
2018
2019                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2020                 tegra_sor_writel(sor, value, offset++);
2021         }
2022 }
2023
2024 static int
2025 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2026                                    const struct drm_display_mode *mode)
2027 {
2028         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2029         struct hdmi_avi_infoframe frame;
2030         u32 value;
2031         int err;
2032
2033         /* disable AVI infoframe */
2034         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2035         value &= ~INFOFRAME_CTRL_SINGLE;
2036         value &= ~INFOFRAME_CTRL_OTHER;
2037         value &= ~INFOFRAME_CTRL_ENABLE;
2038         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2039
2040         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
2041         if (err < 0) {
2042                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2043                 return err;
2044         }
2045
2046         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2047         if (err < 0) {
2048                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2049                 return err;
2050         }
2051
2052         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2053
2054         /* enable AVI infoframe */
2055         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2056         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2057         value |= INFOFRAME_CTRL_ENABLE;
2058         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2059
2060         return 0;
2061 }
2062
2063 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2064 {
2065         u32 value;
2066
2067         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2068         value &= ~INFOFRAME_CTRL_ENABLE;
2069         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2070 }
2071
2072 static struct tegra_sor_hdmi_settings *
2073 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2074 {
2075         unsigned int i;
2076
2077         for (i = 0; i < sor->num_settings; i++)
2078                 if (frequency <= sor->settings[i].frequency)
2079                         return &sor->settings[i];
2080
2081         return NULL;
2082 }
2083
2084 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2085 {
2086         u32 value;
2087
2088         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2089         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2090         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2091         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2092 }
2093
2094 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2095 {
2096         struct i2c_adapter *ddc = sor->output.ddc;
2097
2098         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2099         drm_scdc_set_scrambling(ddc, false);
2100
2101         tegra_sor_hdmi_disable_scrambling(sor);
2102 }
2103
2104 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2105 {
2106         if (sor->scdc_enabled) {
2107                 cancel_delayed_work_sync(&sor->scdc);
2108                 tegra_sor_hdmi_scdc_disable(sor);
2109         }
2110 }
2111
2112 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2113 {
2114         u32 value;
2115
2116         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2117         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2118         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2119         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2120 }
2121
2122 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2123 {
2124         struct i2c_adapter *ddc = sor->output.ddc;
2125
2126         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2127         drm_scdc_set_scrambling(ddc, true);
2128
2129         tegra_sor_hdmi_enable_scrambling(sor);
2130 }
2131
2132 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2133 {
2134         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2135         struct i2c_adapter *ddc = sor->output.ddc;
2136
2137         if (!drm_scdc_get_scrambling_status(ddc)) {
2138                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2139                 tegra_sor_hdmi_scdc_enable(sor);
2140         }
2141
2142         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2143 }
2144
2145 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2146 {
2147         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2148         struct drm_display_mode *mode;
2149
2150         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2151
2152         if (mode->clock >= 340000 && scdc->supported) {
2153                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2154                 tegra_sor_hdmi_scdc_enable(sor);
2155                 sor->scdc_enabled = true;
2156         }
2157 }
2158
2159 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2160 {
2161         struct tegra_output *output = encoder_to_output(encoder);
2162         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2163         struct tegra_sor *sor = to_sor(output);
2164         u32 value;
2165         int err;
2166
2167         tegra_sor_hdmi_scdc_stop(sor);
2168
2169         err = tegra_sor_detach(sor);
2170         if (err < 0)
2171                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2172
2173         tegra_sor_writel(sor, 0, SOR_STATE1);
2174         tegra_sor_update(sor);
2175
2176         /* disable display to SOR clock */
2177         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2178
2179         if (!sor->soc->has_nvdisplay)
2180                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2181         else
2182                 value &= ~SOR_ENABLE(sor->index);
2183
2184         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2185
2186         tegra_dc_commit(dc);
2187
2188         err = tegra_sor_power_down(sor);
2189         if (err < 0)
2190                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2191
2192         err = tegra_io_pad_power_disable(sor->pad);
2193         if (err < 0)
2194                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2195
2196         pm_runtime_put(sor->dev);
2197 }
2198
2199 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2200 {
2201         struct tegra_output *output = encoder_to_output(encoder);
2202         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2203         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2204         struct tegra_sor_hdmi_settings *settings;
2205         struct tegra_sor *sor = to_sor(output);
2206         struct tegra_sor_state *state;
2207         struct drm_display_mode *mode;
2208         unsigned long rate, pclk;
2209         unsigned int div, i;
2210         u32 value;
2211         int err;
2212
2213         state = to_sor_state(output->connector.state);
2214         mode = &encoder->crtc->state->adjusted_mode;
2215         pclk = mode->clock * 1000;
2216
2217         pm_runtime_get_sync(sor->dev);
2218
2219         /* switch to safe parent clock */
2220         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2221         if (err < 0) {
2222                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2223                 return;
2224         }
2225
2226         div = clk_get_rate(sor->clk) / 1000000 * 4;
2227
2228         err = tegra_io_pad_power_enable(sor->pad);
2229         if (err < 0)
2230                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2231
2232         usleep_range(20, 100);
2233
2234         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2235         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2236         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2237
2238         usleep_range(20, 100);
2239
2240         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2241         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2242         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2243
2244         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2245         value &= ~SOR_PLL0_VCOPD;
2246         value &= ~SOR_PLL0_PWR;
2247         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2248
2249         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2250         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2251         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2252
2253         usleep_range(200, 400);
2254
2255         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2256         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2257         value &= ~SOR_PLL2_PORT_POWERDOWN;
2258         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2259
2260         usleep_range(20, 100);
2261
2262         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2263         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2264                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2265         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2266
2267         while (true) {
2268                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2269                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2270                         break;
2271
2272                 usleep_range(250, 1000);
2273         }
2274
2275         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2276                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2277         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2278
2279         while (true) {
2280                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2281                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2282                         break;
2283
2284                 usleep_range(250, 1000);
2285         }
2286
2287         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2288         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2289         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2290
2291         if (mode->clock < 340000) {
2292                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2293                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2294         } else {
2295                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2296                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2297         }
2298
2299         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2300         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2301
2302         /* SOR pad PLL stabilization time */
2303         usleep_range(250, 1000);
2304
2305         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2306         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2307         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2308         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2309
2310         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2311         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2312         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2313         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2314         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2315         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2316
2317         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2318                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2319         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2320
2321         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2322                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2323         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2324         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2325
2326         if (!sor->soc->has_nvdisplay) {
2327                 /* program the reference clock */
2328                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2329                 tegra_sor_writel(sor, value, SOR_REFCLK);
2330         }
2331
2332         /* XXX not in TRM */
2333         for (value = 0, i = 0; i < 5; i++)
2334                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2335                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2336
2337         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2338         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2339
2340         /* switch to parent clock */
2341         err = clk_set_parent(sor->clk, sor->clk_parent);
2342         if (err < 0) {
2343                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2344                 return;
2345         }
2346
2347         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2348         if (err < 0) {
2349                 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2350                 return;
2351         }
2352
2353         /* adjust clock rate for HDMI 2.0 modes */
2354         rate = clk_get_rate(sor->clk_parent);
2355
2356         if (mode->clock >= 340000)
2357                 rate /= 2;
2358
2359         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2360
2361         clk_set_rate(sor->clk, rate);
2362
2363         if (!sor->soc->has_nvdisplay) {
2364                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2365
2366                 /* XXX is this the proper check? */
2367                 if (mode->clock < 75000)
2368                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2369
2370                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2371         }
2372
2373         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2374
2375         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2376                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2377         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2378
2379         if (!dc->soc->has_nvdisplay) {
2380                 /* H_PULSE2 setup */
2381                 pulse_start = h_ref_to_sync +
2382                               (mode->hsync_end - mode->hsync_start) +
2383                               (mode->htotal - mode->hsync_end) - 10;
2384
2385                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2386                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2387                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2388
2389                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2390                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2391
2392                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2393                 value |= H_PULSE2_ENABLE;
2394                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2395         }
2396
2397         /* infoframe setup */
2398         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2399         if (err < 0)
2400                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2401
2402         /* XXX HDMI audio support not implemented yet */
2403         tegra_sor_hdmi_disable_audio_infoframe(sor);
2404
2405         /* use single TMDS protocol */
2406         value = tegra_sor_readl(sor, SOR_STATE1);
2407         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2408         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2409         tegra_sor_writel(sor, value, SOR_STATE1);
2410
2411         /* power up pad calibration */
2412         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2413         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2414         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2415
2416         /* production settings */
2417         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2418         if (!settings) {
2419                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2420                         mode->clock * 1000);
2421                 return;
2422         }
2423
2424         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2425         value &= ~SOR_PLL0_ICHPMP_MASK;
2426         value &= ~SOR_PLL0_FILTER_MASK;
2427         value &= ~SOR_PLL0_VCOCAP_MASK;
2428         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2429         value |= SOR_PLL0_FILTER(settings->filter);
2430         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2431         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2432
2433         /* XXX not in TRM */
2434         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2435         value &= ~SOR_PLL1_LOADADJ_MASK;
2436         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2437         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2438         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2439         value |= SOR_PLL1_TMDS_TERM;
2440         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2441
2442         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2443         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2444         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2445         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2446         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2447         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2448         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2449         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2450         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2451         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2452
2453         value = settings->drive_current[3] << 24 |
2454                 settings->drive_current[2] << 16 |
2455                 settings->drive_current[1] <<  8 |
2456                 settings->drive_current[0] <<  0;
2457         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2458
2459         value = settings->preemphasis[3] << 24 |
2460                 settings->preemphasis[2] << 16 |
2461                 settings->preemphasis[1] <<  8 |
2462                 settings->preemphasis[0] <<  0;
2463         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2464
2465         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2466         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2467         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2468         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2469         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2470
2471         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2472         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2473         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2474         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2475
2476         /* power down pad calibration */
2477         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2478         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2479         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2480
2481         if (!dc->soc->has_nvdisplay) {
2482                 /* miscellaneous display controller settings */
2483                 value = VSYNC_H_POSITION(1);
2484                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2485         }
2486
2487         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2488         value &= ~DITHER_CONTROL_MASK;
2489         value &= ~BASE_COLOR_SIZE_MASK;
2490
2491         switch (state->bpc) {
2492         case 6:
2493                 value |= BASE_COLOR_SIZE_666;
2494                 break;
2495
2496         case 8:
2497                 value |= BASE_COLOR_SIZE_888;
2498                 break;
2499
2500         case 10:
2501                 value |= BASE_COLOR_SIZE_101010;
2502                 break;
2503
2504         case 12:
2505                 value |= BASE_COLOR_SIZE_121212;
2506                 break;
2507
2508         default:
2509                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2510                 value |= BASE_COLOR_SIZE_888;
2511                 break;
2512         }
2513
2514         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2515
2516         /* XXX set display head owner */
2517         value = tegra_sor_readl(sor, SOR_STATE1);
2518         value &= ~SOR_STATE_ASY_OWNER_MASK;
2519         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2520         tegra_sor_writel(sor, value, SOR_STATE1);
2521
2522         err = tegra_sor_power_up(sor, 250);
2523         if (err < 0)
2524                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2525
2526         /* configure dynamic range of output */
2527         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2528         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2529         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2530         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2531
2532         /* configure colorspace */
2533         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2534         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2535         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2536         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2537
2538         tegra_sor_mode_set(sor, mode, state);
2539
2540         tegra_sor_update(sor);
2541
2542         /* program preamble timing in SOR (XXX) */
2543         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2544         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2545         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2546
2547         err = tegra_sor_attach(sor);
2548         if (err < 0)
2549                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2550
2551         /* enable display to SOR clock and generate HDMI preamble */
2552         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2553
2554         if (!sor->soc->has_nvdisplay)
2555                 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2556         else
2557                 value |= SOR_ENABLE(sor->index);
2558
2559         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2560
2561         if (dc->soc->has_nvdisplay) {
2562                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2563                 value &= ~PROTOCOL_MASK;
2564                 value |= PROTOCOL_SINGLE_TMDS_A;
2565                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2566         }
2567
2568         tegra_dc_commit(dc);
2569
2570         err = tegra_sor_wakeup(sor);
2571         if (err < 0)
2572                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2573
2574         tegra_sor_hdmi_scdc_start(sor);
2575 }
2576
2577 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2578         .disable = tegra_sor_hdmi_disable,
2579         .enable = tegra_sor_hdmi_enable,
2580         .atomic_check = tegra_sor_encoder_atomic_check,
2581 };
2582
2583 static int tegra_sor_init(struct host1x_client *client)
2584 {
2585         struct drm_device *drm = dev_get_drvdata(client->parent);
2586         const struct drm_encoder_helper_funcs *helpers = NULL;
2587         struct tegra_sor *sor = host1x_client_to_sor(client);
2588         int connector = DRM_MODE_CONNECTOR_Unknown;
2589         int encoder = DRM_MODE_ENCODER_NONE;
2590         int err;
2591
2592         if (!sor->aux) {
2593                 if (sor->soc->supports_hdmi) {
2594                         connector = DRM_MODE_CONNECTOR_HDMIA;
2595                         encoder = DRM_MODE_ENCODER_TMDS;
2596                         helpers = &tegra_sor_hdmi_helpers;
2597                 } else if (sor->soc->supports_lvds) {
2598                         connector = DRM_MODE_CONNECTOR_LVDS;
2599                         encoder = DRM_MODE_ENCODER_LVDS;
2600                 }
2601         } else {
2602                 if (sor->soc->supports_edp) {
2603                         connector = DRM_MODE_CONNECTOR_eDP;
2604                         encoder = DRM_MODE_ENCODER_TMDS;
2605                         helpers = &tegra_sor_edp_helpers;
2606                 } else if (sor->soc->supports_dp) {
2607                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2608                         encoder = DRM_MODE_ENCODER_TMDS;
2609                 }
2610         }
2611
2612         sor->output.dev = sor->dev;
2613
2614         drm_connector_init(drm, &sor->output.connector,
2615                            &tegra_sor_connector_funcs,
2616                            connector);
2617         drm_connector_helper_add(&sor->output.connector,
2618                                  &tegra_sor_connector_helper_funcs);
2619         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2620
2621         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2622                          encoder, NULL);
2623         drm_encoder_helper_add(&sor->output.encoder, helpers);
2624
2625         drm_connector_attach_encoder(&sor->output.connector,
2626                                           &sor->output.encoder);
2627         drm_connector_register(&sor->output.connector);
2628
2629         err = tegra_output_init(drm, &sor->output);
2630         if (err < 0) {
2631                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2632                 return err;
2633         }
2634
2635         tegra_output_find_possible_crtcs(&sor->output, drm);
2636
2637         if (sor->aux) {
2638                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2639                 if (err < 0) {
2640                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2641                         return err;
2642                 }
2643         }
2644
2645         /*
2646          * XXX: Remove this reset once proper hand-over from firmware to
2647          * kernel is possible.
2648          */
2649         if (sor->rst) {
2650                 err = reset_control_assert(sor->rst);
2651                 if (err < 0) {
2652                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2653                                 err);
2654                         return err;
2655                 }
2656         }
2657
2658         err = clk_prepare_enable(sor->clk);
2659         if (err < 0) {
2660                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2661                 return err;
2662         }
2663
2664         usleep_range(1000, 3000);
2665
2666         if (sor->rst) {
2667                 err = reset_control_deassert(sor->rst);
2668                 if (err < 0) {
2669                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2670                                 err);
2671                         clk_disable_unprepare(sor->clk);
2672                         return err;
2673                 }
2674         }
2675
2676         err = clk_prepare_enable(sor->clk_safe);
2677         if (err < 0) {
2678                 clk_disable_unprepare(sor->clk);
2679                 return err;
2680         }
2681
2682         err = clk_prepare_enable(sor->clk_dp);
2683         if (err < 0) {
2684                 clk_disable_unprepare(sor->clk_safe);
2685                 clk_disable_unprepare(sor->clk);
2686                 return err;
2687         }
2688
2689         return 0;
2690 }
2691
2692 static int tegra_sor_exit(struct host1x_client *client)
2693 {
2694         struct tegra_sor *sor = host1x_client_to_sor(client);
2695         int err;
2696
2697         tegra_output_exit(&sor->output);
2698
2699         if (sor->aux) {
2700                 err = drm_dp_aux_detach(sor->aux);
2701                 if (err < 0) {
2702                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2703                         return err;
2704                 }
2705         }
2706
2707         clk_disable_unprepare(sor->clk_safe);
2708         clk_disable_unprepare(sor->clk_dp);
2709         clk_disable_unprepare(sor->clk);
2710
2711         return 0;
2712 }
2713
2714 static const struct host1x_client_ops sor_client_ops = {
2715         .init = tegra_sor_init,
2716         .exit = tegra_sor_exit,
2717 };
2718
2719 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2720         .name = "eDP",
2721 };
2722
2723 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2724 {
2725         int err;
2726
2727         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2728         if (IS_ERR(sor->avdd_io_supply)) {
2729                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2730                         PTR_ERR(sor->avdd_io_supply));
2731                 return PTR_ERR(sor->avdd_io_supply);
2732         }
2733
2734         err = regulator_enable(sor->avdd_io_supply);
2735         if (err < 0) {
2736                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2737                         err);
2738                 return err;
2739         }
2740
2741         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2742         if (IS_ERR(sor->vdd_pll_supply)) {
2743                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2744                         PTR_ERR(sor->vdd_pll_supply));
2745                 return PTR_ERR(sor->vdd_pll_supply);
2746         }
2747
2748         err = regulator_enable(sor->vdd_pll_supply);
2749         if (err < 0) {
2750                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2751                         err);
2752                 return err;
2753         }
2754
2755         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2756         if (IS_ERR(sor->hdmi_supply)) {
2757                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2758                         PTR_ERR(sor->hdmi_supply));
2759                 return PTR_ERR(sor->hdmi_supply);
2760         }
2761
2762         err = regulator_enable(sor->hdmi_supply);
2763         if (err < 0) {
2764                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2765                 return err;
2766         }
2767
2768         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
2769
2770         return 0;
2771 }
2772
2773 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2774 {
2775         regulator_disable(sor->hdmi_supply);
2776         regulator_disable(sor->vdd_pll_supply);
2777         regulator_disable(sor->avdd_io_supply);
2778
2779         return 0;
2780 }
2781
2782 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2783         .name = "HDMI",
2784         .probe = tegra_sor_hdmi_probe,
2785         .remove = tegra_sor_hdmi_remove,
2786 };
2787
2788 static const u8 tegra124_sor_xbar_cfg[5] = {
2789         0, 1, 2, 3, 4
2790 };
2791
2792 static const struct tegra_sor_regs tegra124_sor_regs = {
2793         .head_state0 = 0x05,
2794         .head_state1 = 0x07,
2795         .head_state2 = 0x09,
2796         .head_state3 = 0x0b,
2797         .head_state4 = 0x0d,
2798         .head_state5 = 0x0f,
2799         .pll0 = 0x17,
2800         .pll1 = 0x18,
2801         .pll2 = 0x19,
2802         .pll3 = 0x1a,
2803         .dp_padctl0 = 0x5c,
2804         .dp_padctl2 = 0x73,
2805 };
2806
2807 static const struct tegra_sor_soc tegra124_sor = {
2808         .supports_edp = true,
2809         .supports_lvds = true,
2810         .supports_hdmi = false,
2811         .supports_dp = false,
2812         .regs = &tegra124_sor_regs,
2813         .has_nvdisplay = false,
2814         .xbar_cfg = tegra124_sor_xbar_cfg,
2815 };
2816
2817 static const struct tegra_sor_regs tegra210_sor_regs = {
2818         .head_state0 = 0x05,
2819         .head_state1 = 0x07,
2820         .head_state2 = 0x09,
2821         .head_state3 = 0x0b,
2822         .head_state4 = 0x0d,
2823         .head_state5 = 0x0f,
2824         .pll0 = 0x17,
2825         .pll1 = 0x18,
2826         .pll2 = 0x19,
2827         .pll3 = 0x1a,
2828         .dp_padctl0 = 0x5c,
2829         .dp_padctl2 = 0x73,
2830 };
2831
2832 static const struct tegra_sor_soc tegra210_sor = {
2833         .supports_edp = true,
2834         .supports_lvds = false,
2835         .supports_hdmi = false,
2836         .supports_dp = false,
2837         .regs = &tegra210_sor_regs,
2838         .has_nvdisplay = false,
2839         .xbar_cfg = tegra124_sor_xbar_cfg,
2840 };
2841
2842 static const u8 tegra210_sor_xbar_cfg[5] = {
2843         2, 1, 0, 3, 4
2844 };
2845
2846 static const struct tegra_sor_soc tegra210_sor1 = {
2847         .supports_edp = false,
2848         .supports_lvds = false,
2849         .supports_hdmi = true,
2850         .supports_dp = true,
2851
2852         .regs = &tegra210_sor_regs,
2853         .has_nvdisplay = false,
2854
2855         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2856         .settings = tegra210_sor_hdmi_defaults,
2857
2858         .xbar_cfg = tegra210_sor_xbar_cfg,
2859 };
2860
2861 static const struct tegra_sor_regs tegra186_sor_regs = {
2862         .head_state0 = 0x151,
2863         .head_state1 = 0x154,
2864         .head_state2 = 0x157,
2865         .head_state3 = 0x15a,
2866         .head_state4 = 0x15d,
2867         .head_state5 = 0x160,
2868         .pll0 = 0x163,
2869         .pll1 = 0x164,
2870         .pll2 = 0x165,
2871         .pll3 = 0x166,
2872         .dp_padctl0 = 0x168,
2873         .dp_padctl2 = 0x16a,
2874 };
2875
2876 static const struct tegra_sor_soc tegra186_sor = {
2877         .supports_edp = false,
2878         .supports_lvds = false,
2879         .supports_hdmi = false,
2880         .supports_dp = true,
2881
2882         .regs = &tegra186_sor_regs,
2883         .has_nvdisplay = true,
2884
2885         .xbar_cfg = tegra124_sor_xbar_cfg,
2886 };
2887
2888 static const struct tegra_sor_soc tegra186_sor1 = {
2889         .supports_edp = false,
2890         .supports_lvds = false,
2891         .supports_hdmi = true,
2892         .supports_dp = true,
2893
2894         .regs = &tegra186_sor_regs,
2895         .has_nvdisplay = true,
2896
2897         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
2898         .settings = tegra186_sor_hdmi_defaults,
2899
2900         .xbar_cfg = tegra124_sor_xbar_cfg,
2901 };
2902
2903 static const struct of_device_id tegra_sor_of_match[] = {
2904         { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
2905         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
2906         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2907         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2908         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2909         { },
2910 };
2911 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2912
2913 static int tegra_sor_parse_dt(struct tegra_sor *sor)
2914 {
2915         struct device_node *np = sor->dev->of_node;
2916         u32 value;
2917         int err;
2918
2919         if (sor->soc->has_nvdisplay) {
2920                 err = of_property_read_u32(np, "nvidia,interface", &value);
2921                 if (err < 0)
2922                         return err;
2923
2924                 sor->index = value;
2925
2926                 /*
2927                  * override the default that we already set for Tegra210 and
2928                  * earlier
2929                  */
2930                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
2931         } else {
2932                 if (sor->soc->supports_edp)
2933                         sor->index = 0;
2934                 else
2935                         sor->index = 1;
2936         }
2937
2938         return 0;
2939 }
2940
2941 static int tegra_sor_probe(struct platform_device *pdev)
2942 {
2943         struct device_node *np;
2944         struct tegra_sor *sor;
2945         struct resource *regs;
2946         int err;
2947
2948         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2949         if (!sor)
2950                 return -ENOMEM;
2951
2952         sor->soc = of_device_get_match_data(&pdev->dev);
2953         sor->output.dev = sor->dev = &pdev->dev;
2954
2955         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2956                                      sor->soc->num_settings *
2957                                         sizeof(*sor->settings),
2958                                      GFP_KERNEL);
2959         if (!sor->settings)
2960                 return -ENOMEM;
2961
2962         sor->num_settings = sor->soc->num_settings;
2963
2964         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2965         if (np) {
2966                 sor->aux = drm_dp_aux_find_by_of_node(np);
2967                 of_node_put(np);
2968
2969                 if (!sor->aux)
2970                         return -EPROBE_DEFER;
2971         }
2972
2973         if (!sor->aux) {
2974                 if (sor->soc->supports_hdmi) {
2975                         sor->ops = &tegra_sor_hdmi_ops;
2976                         sor->pad = TEGRA_IO_PAD_HDMI;
2977                 } else if (sor->soc->supports_lvds) {
2978                         dev_err(&pdev->dev, "LVDS not supported yet\n");
2979                         return -ENODEV;
2980                 } else {
2981                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
2982                         return -ENODEV;
2983                 }
2984         } else {
2985                 if (sor->soc->supports_edp) {
2986                         sor->ops = &tegra_sor_edp_ops;
2987                         sor->pad = TEGRA_IO_PAD_LVDS;
2988                 } else if (sor->soc->supports_dp) {
2989                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2990                         return -ENODEV;
2991                 } else {
2992                         dev_err(&pdev->dev, "unknown (DP) support\n");
2993                         return -ENODEV;
2994                 }
2995         }
2996
2997         err = tegra_sor_parse_dt(sor);
2998         if (err < 0)
2999                 return err;
3000
3001         err = tegra_output_probe(&sor->output);
3002         if (err < 0) {
3003                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3004                 return err;
3005         }
3006
3007         if (sor->ops && sor->ops->probe) {
3008                 err = sor->ops->probe(sor);
3009                 if (err < 0) {
3010                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3011                                 sor->ops->name, err);
3012                         goto output;
3013                 }
3014         }
3015
3016         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3017         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3018         if (IS_ERR(sor->regs)) {
3019                 err = PTR_ERR(sor->regs);
3020                 goto remove;
3021         }
3022
3023         if (!pdev->dev.pm_domain) {
3024                 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
3025                 if (IS_ERR(sor->rst)) {
3026                         err = PTR_ERR(sor->rst);
3027                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3028                                 err);
3029                         goto remove;
3030                 }
3031         }
3032
3033         sor->clk = devm_clk_get(&pdev->dev, NULL);
3034         if (IS_ERR(sor->clk)) {
3035                 err = PTR_ERR(sor->clk);
3036                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3037                 goto remove;
3038         }
3039
3040         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3041                 struct device_node *np = pdev->dev.of_node;
3042                 const char *name;
3043
3044                 /*
3045                  * For backwards compatibility with Tegra210 device trees,
3046                  * fall back to the old clock name "source" if the new "out"
3047                  * clock is not available.
3048                  */
3049                 if (of_property_match_string(np, "clock-names", "out") < 0)
3050                         name = "source";
3051                 else
3052                         name = "out";
3053
3054                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3055                 if (IS_ERR(sor->clk_out)) {
3056                         err = PTR_ERR(sor->clk_out);
3057                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3058                                 name, err);
3059                         goto remove;
3060                 }
3061         } else {
3062                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3063                 sor->clk_out = sor->clk;
3064         }
3065
3066         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3067         if (IS_ERR(sor->clk_parent)) {
3068                 err = PTR_ERR(sor->clk_parent);
3069                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3070                 goto remove;
3071         }
3072
3073         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3074         if (IS_ERR(sor->clk_safe)) {
3075                 err = PTR_ERR(sor->clk_safe);
3076                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3077                 goto remove;
3078         }
3079
3080         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3081         if (IS_ERR(sor->clk_dp)) {
3082                 err = PTR_ERR(sor->clk_dp);
3083                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3084                 goto remove;
3085         }
3086
3087         /*
3088          * Starting with Tegra186, the BPMP provides an implementation for
3089          * the pad output clock, so we have to look it up from device tree.
3090          */
3091         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3092         if (IS_ERR(sor->clk_pad)) {
3093                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3094                         err = PTR_ERR(sor->clk_pad);
3095                         goto remove;
3096                 }
3097
3098                 /*
3099                  * If the pad output clock is not available, then we assume
3100                  * we're on Tegra210 or earlier and have to provide our own
3101                  * implementation.
3102                  */
3103                 sor->clk_pad = NULL;
3104         }
3105
3106         /*
3107          * The bootloader may have set up the SOR such that it's module clock
3108          * is sourced by one of the display PLLs. However, that doesn't work
3109          * without properly having set up other bits of the SOR.
3110          */
3111         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3112         if (err < 0) {
3113                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3114                 goto remove;
3115         }
3116
3117         platform_set_drvdata(pdev, sor);
3118         pm_runtime_enable(&pdev->dev);
3119
3120         /*
3121          * On Tegra210 and earlier, provide our own implementation for the
3122          * pad output clock.
3123          */
3124         if (!sor->clk_pad) {
3125                 err = pm_runtime_get_sync(&pdev->dev);
3126                 if (err < 0) {
3127                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3128                                 err);
3129                         goto remove;
3130                 }
3131
3132                 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3133                                                           "sor1_pad_clkout");
3134                 pm_runtime_put(&pdev->dev);
3135         }
3136
3137         if (IS_ERR(sor->clk_pad)) {
3138                 err = PTR_ERR(sor->clk_pad);
3139                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3140                         err);
3141                 goto remove;
3142         }
3143
3144         INIT_LIST_HEAD(&sor->client.list);
3145         sor->client.ops = &sor_client_ops;
3146         sor->client.dev = &pdev->dev;
3147
3148         err = host1x_client_register(&sor->client);
3149         if (err < 0) {
3150                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3151                         err);
3152                 goto remove;
3153         }
3154
3155         return 0;
3156
3157 remove:
3158         if (sor->ops && sor->ops->remove)
3159                 sor->ops->remove(sor);
3160 output:
3161         tegra_output_remove(&sor->output);
3162         return err;
3163 }
3164
3165 static int tegra_sor_remove(struct platform_device *pdev)
3166 {
3167         struct tegra_sor *sor = platform_get_drvdata(pdev);
3168         int err;
3169
3170         pm_runtime_disable(&pdev->dev);
3171
3172         err = host1x_client_unregister(&sor->client);
3173         if (err < 0) {
3174                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3175                         err);
3176                 return err;
3177         }
3178
3179         if (sor->ops && sor->ops->remove) {
3180                 err = sor->ops->remove(sor);
3181                 if (err < 0)
3182                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3183         }
3184
3185         tegra_output_remove(&sor->output);
3186
3187         return 0;
3188 }
3189
3190 #ifdef CONFIG_PM
3191 static int tegra_sor_suspend(struct device *dev)
3192 {
3193         struct tegra_sor *sor = dev_get_drvdata(dev);
3194         int err;
3195
3196         if (sor->rst) {
3197                 err = reset_control_assert(sor->rst);
3198                 if (err < 0) {
3199                         dev_err(dev, "failed to assert reset: %d\n", err);
3200                         return err;
3201                 }
3202         }
3203
3204         usleep_range(1000, 2000);
3205
3206         clk_disable_unprepare(sor->clk);
3207
3208         return 0;
3209 }
3210
3211 static int tegra_sor_resume(struct device *dev)
3212 {
3213         struct tegra_sor *sor = dev_get_drvdata(dev);
3214         int err;
3215
3216         err = clk_prepare_enable(sor->clk);
3217         if (err < 0) {
3218                 dev_err(dev, "failed to enable clock: %d\n", err);
3219                 return err;
3220         }
3221
3222         usleep_range(1000, 2000);
3223
3224         if (sor->rst) {
3225                 err = reset_control_deassert(sor->rst);
3226                 if (err < 0) {
3227                         dev_err(dev, "failed to deassert reset: %d\n", err);
3228                         clk_disable_unprepare(sor->clk);
3229                         return err;
3230                 }
3231         }
3232
3233         return 0;
3234 }
3235 #endif
3236
3237 static const struct dev_pm_ops tegra_sor_pm_ops = {
3238         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3239 };
3240
3241 struct platform_driver tegra_sor_driver = {
3242         .driver = {
3243                 .name = "tegra-sor",
3244                 .of_match_table = tegra_sor_of_match,
3245                 .pm = &tegra_sor_pm_ops,
3246         },
3247         .probe = tegra_sor_probe,
3248         .remove = tegra_sor_remove,
3249 };