gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_gem_framebuffer_helper.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_edid.h>
  39
  40 #include <linux/gcd.h>
  41
  42 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  43 {
  44         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  45         struct drm_device *dev = crtc->dev;
  46         struct radeon_device *rdev = dev->dev_private;
  47         u16 *r, *g, *b;
  48         int i;
  49
  50         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  51         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  54         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  55         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  56
  57         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  58         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  59         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  60
  61         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  62         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  63         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  64
  65         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  66         r = crtc->gamma_store;
  67         g = r + crtc->gamma_size;
  68         b = g + crtc->gamma_size;
  69         for (i = 0; i < 256; i++) {
  70                 WREG32(AVIVO_DC_LUT_30_COLOR,
  71                        ((*r++ & 0xffc0) << 14) |
  72                        ((*g++ & 0xffc0) << 4) |
  73                        (*b++ >> 6));
  74         }
  75
  76         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  77         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  78 }
  79
  80 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  81 {
  82         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  83         struct drm_device *dev = crtc->dev;
  84         struct radeon_device *rdev = dev->dev_private;
  85         u16 *r, *g, *b;
  86         int i;
  87
  88         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  89         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  90
  91         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  92         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  93         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  94
  95         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  96         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  97         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  98
  99         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 100         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 101
 102         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 103         r = crtc->gamma_store;
 104         g = r + crtc->gamma_size;
 105         b = g + crtc->gamma_size;
 106         for (i = 0; i < 256; i++) {
 107                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 108                        ((*r++ & 0xffc0) << 14) |
 109                        ((*g++ & 0xffc0) << 4) |
 110                        (*b++ >> 6));
 111         }
 112 }
 113
 114 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 115 {
 116         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 117         struct drm_device *dev = crtc->dev;
 118         struct radeon_device *rdev = dev->dev_private;
 119         u16 *r, *g, *b;
 120         int i;
 121
 122         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 123
 124         msleep(10);
 125
 126         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 127                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 128                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 129         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 130                NI_GRPH_PRESCALE_BYPASS);
 131         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 132                NI_OVL_PRESCALE_BYPASS);
 133         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 134                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 135                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 136
 137         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 138
 139         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 140         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 141         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 142
 143         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 144         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 145         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 146
 147         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 148         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 149
 150         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 151         r = crtc->gamma_store;
 152         g = r + crtc->gamma_size;
 153         b = g + crtc->gamma_size;
 154         for (i = 0; i < 256; i++) {
 155                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 156                        ((*r++ & 0xffc0) << 14) |
 157                        ((*g++ & 0xffc0) << 4) |
 158                        (*b++ >> 6));
 159         }
 160
 161         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 162                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 163                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 164                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 165                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 166         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 167                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 168                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 169         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 170                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 171                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 172         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 173                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 174                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 175         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 176         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 177         if (ASIC_IS_DCE8(rdev)) {
 178                 /* XXX this only needs to be programmed once per crtc at startup,
 179                  * not sure where the best place for it is
 180                  */
 181                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 182                        CIK_CURSOR_ALPHA_BLND_ENA);
 183         }
 184 }
 185
 186 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         u16 *r, *g, *b;
 192         int i;
 193         uint32_t dac2_cntl;
 194
 195         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 196         if (radeon_crtc->crtc_id == 0)
 197                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 198         else
 199                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 200         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 201
 202         WREG8(RADEON_PALETTE_INDEX, 0);
 203         r = crtc->gamma_store;
 204         g = r + crtc->gamma_size;
 205         b = g + crtc->gamma_size;
 206         for (i = 0; i < 256; i++) {
 207                 WREG32(RADEON_PALETTE_30_DATA,
 208                        ((*r++ & 0xffc0) << 14) |
 209                        ((*g++ & 0xffc0) << 4) |
 210                        (*b++ >> 6));
 211         }
 212 }
 213
 214 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 215 {
 216         struct drm_device *dev = crtc->dev;
 217         struct radeon_device *rdev = dev->dev_private;
 218
 219         if (!crtc->enabled)
 220                 return;
 221
 222         if (ASIC_IS_DCE5(rdev))
 223                 dce5_crtc_load_lut(crtc);
 224         else if (ASIC_IS_DCE4(rdev))
 225                 dce4_crtc_load_lut(crtc);
 226         else if (ASIC_IS_AVIVO(rdev))
 227                 avivo_crtc_load_lut(crtc);
 228         else
 229                 legacy_crtc_load_lut(crtc);
 230 }
 231
 232 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                  u16 *blue, uint32_t size,
 234                                  struct drm_modeset_acquire_ctx *ctx)
 235 {
 236         radeon_crtc_load_lut(crtc);
 237
 238         return 0;
 239 }
 240
 241 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 242 {
 243         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 244
 245         drm_crtc_cleanup(crtc);
 246         destroy_workqueue(radeon_crtc->flip_queue);
 247         kfree(radeon_crtc);
 248 }
 249
 250 /**
 251  * radeon_unpin_work_func - unpin old buffer object
 252  *
 253  * @__work - kernel work item
 254  *
 255  * Unpin the old frame buffer object outside of the interrupt handler
 256  */
 257 static void radeon_unpin_work_func(struct work_struct *__work)
 258 {
 259         struct radeon_flip_work *work =
 260                 container_of(__work, struct radeon_flip_work, unpin_work);
 261         int r;
 262
 263         /* unpin of the old buffer */
 264         r = radeon_bo_reserve(work->old_rbo, false);
 265         if (likely(r == 0)) {
 266                 r = radeon_bo_unpin(work->old_rbo);
 267                 if (unlikely(r != 0)) {
 268                         DRM_ERROR("failed to unpin buffer after flip\n");
 269                 }
 270                 radeon_bo_unreserve(work->old_rbo);
 271         } else
 272                 DRM_ERROR("failed to reserve buffer after flip\n");
 273
 274         drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
 275         kfree(work);
 276 }
 277
 278 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 279 {
 280         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 281         unsigned long flags;
 282         u32 update_pending;
 283         int vpos, hpos;
 284
 285         /* can happen during initialization */
 286         if (radeon_crtc == NULL)
 287                 return;
 288
 289         /* Skip the pageflip completion check below (based on polling) on
 290          * asics which reliably support hw pageflip completion irqs. pflip
 291          * irqs are a reliable and race-free method of handling pageflip
 292          * completion detection. A use_pflipirq module parameter < 2 allows
 293          * to override this in case of asics with faulty pflip irqs.
 294          * A module parameter of 0 would only use this polling based path,
 295          * a parameter of 1 would use pflip irq only as a backup to this
 296          * path, as in Linux 3.16.
 297          */
 298         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 299                 return;
 300
 301         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 302         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 303                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 304                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 305                                  radeon_crtc->flip_status,
 306                                  RADEON_FLIP_SUBMITTED);
 307                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 308                 return;
 309         }
 310
 311         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 312
 313         /* Has the pageflip already completed in crtc, or is it certain
 314          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 315          * distance to start of "fudged earlier" vblank in vpos, distance to
 316          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 317          * the last few scanlines before start of real vblank, where the vblank
 318          * irq can fire, so we have sampled update_pending a bit too early and
 319          * know the flip will complete at leading edge of the upcoming real
 320          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 321          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 322          *  == inside real vblank, the flip will complete almost immediately.
 323          * Note that this method of completion handling is still not 100% race
 324          * free, as we could execute before the radeon_flip_work_func managed
 325          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 326          * but the flip still gets programmed into hw and completed during
 327          * vblank, leading to a delayed emission of the flip completion event.
 328          * This applies at least to pre-AVIVO hardware, where flips are always
 329          * completing inside vblank, not only at leading edge of vblank.
 330          */
 331         if (update_pending &&
 332             (DRM_SCANOUTPOS_VALID &
 333              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 334                                         GET_DISTANCE_TO_VBLANKSTART,
 335                                         &vpos, &hpos, NULL, NULL,
 336                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 337             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 338                 /* crtc didn't flip in this target vblank interval,
 339                  * but flip is pending in crtc. Based on the current
 340                  * scanout position we know that the current frame is
 341                  * (nearly) complete and the flip will (likely)
 342                  * complete before the start of the next frame.
 343                  */
 344                 update_pending = 0;
 345         }
 346         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 347         if (!update_pending)
 348                 radeon_crtc_handle_flip(rdev, crtc_id);
 349 }
 350
 351 /**
 352  * radeon_crtc_handle_flip - page flip completed
 353  *
 354  * @rdev: radeon device pointer
 355  * @crtc_id: crtc number this event is for
 356  *
 357  * Called when we are sure that a page flip for this crtc is completed.
 358  */
 359 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 360 {
 361         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 362         struct radeon_flip_work *work;
 363         unsigned long flags;
 364
 365         /* this can happen at init */
 366         if (radeon_crtc == NULL)
 367                 return;
 368
 369         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 370         work = radeon_crtc->flip_work;
 371         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 372                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 373                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 374                                  radeon_crtc->flip_status,
 375                                  RADEON_FLIP_SUBMITTED);
 376                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 377                 return;
 378         }
 379
 380         /* Pageflip completed. Clean up. */
 381         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 382         radeon_crtc->flip_work = NULL;
 383
 384         /* wakeup userspace */
 385         if (work->event)
 386                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 387
 388         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 389
 390         drm_crtc_vblank_put(&radeon_crtc->base);
 391         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 392         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 393 }
 394
 395 /**
 396  * radeon_flip_work_func - page flip framebuffer
 397  *
 398  * @work - kernel work item
 399  *
 400  * Wait for the buffer object to become idle and do the actual page flip
 401  */
 402 static void radeon_flip_work_func(struct work_struct *__work)
 403 {
 404         struct radeon_flip_work *work =
 405                 container_of(__work, struct radeon_flip_work, flip_work);
 406         struct radeon_device *rdev = work->rdev;
 407         struct drm_device *dev = rdev->ddev;
 408         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 409
 410         struct drm_crtc *crtc = &radeon_crtc->base;
 411         unsigned long flags;
 412         int r;
 413         int vpos, hpos;
 414
 415         down_read(&rdev->exclusive_lock);
 416         if (work->fence) {
 417                 struct radeon_fence *fence;
 418
 419                 fence = to_radeon_fence(work->fence);
 420                 if (fence && fence->rdev == rdev) {
 421                         r = radeon_fence_wait(fence, false);
 422                         if (r == -EDEADLK) {
 423                                 up_read(&rdev->exclusive_lock);
 424                                 do {
 425                                         r = radeon_gpu_reset(rdev);
 426                                 } while (r == -EAGAIN);
 427                                 down_read(&rdev->exclusive_lock);
 428                         }
 429                 } else
 430                         r = dma_fence_wait(work->fence, false);
 431
 432                 if (r)
 433                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 434
 435                 /* We continue with the page flip even if we failed to wait on
 436                  * the fence, otherwise the DRM core and userspace will be
 437                  * confused about which BO the CRTC is scanning out
 438                  */
 439
 440                 dma_fence_put(work->fence);
 441                 work->fence = NULL;
 442         }
 443
 444         /* Wait until we're out of the vertical blank period before the one
 445          * targeted by the flip. Always wait on pre DCE4 to avoid races with
 446          * flip completion handling from vblank irq, as these old asics don't
 447          * have reliable pageflip completion interrupts.
 448          */
 449         while (radeon_crtc->enabled &&
 450                 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 451                                             &vpos, &hpos, NULL, NULL,
 452                                             &crtc->hwmode)
 453                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 454                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 455                 (!ASIC_IS_AVIVO(rdev) ||
 456                 ((int) (work->target_vblank -
 457                 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
 458                 usleep_range(1000, 2000);
 459
 460         /* We borrow the event spin lock for protecting flip_status */
 461         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 462
 463         /* set the proper interrupt */
 464         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 465
 466         /* do the flip (mmio) */
 467         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 468
 469         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 470         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 471         up_read(&rdev->exclusive_lock);
 472 }
 473
 474 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 475                                         struct drm_framebuffer *fb,
 476                                         struct drm_pending_vblank_event *event,
 477                                         uint32_t page_flip_flags,
 478                                         uint32_t target,
 479                                         struct drm_modeset_acquire_ctx *ctx)
 480 {
 481         struct drm_device *dev = crtc->dev;
 482         struct radeon_device *rdev = dev->dev_private;
 483         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 484         struct drm_gem_object *obj;
 485         struct radeon_flip_work *work;
 486         struct radeon_bo *new_rbo;
 487         uint32_t tiling_flags, pitch_pixels;
 488         uint64_t base;
 489         unsigned long flags;
 490         int r;
 491
 492         work = kzalloc(sizeof *work, GFP_KERNEL);
 493         if (work == NULL)
 494                 return -ENOMEM;
 495
 496         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 497         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 498
 499         work->rdev = rdev;
 500         work->crtc_id = radeon_crtc->crtc_id;
 501         work->event = event;
 502         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 503
 504         /* schedule unpin of the old buffer */
 505         obj = crtc->primary->fb->obj[0];
 506
 507         /* take a reference to the old object */
 508         drm_gem_object_get(obj);
 509         work->old_rbo = gem_to_radeon_bo(obj);
 510
 511         obj = fb->obj[0];
 512         new_rbo = gem_to_radeon_bo(obj);
 513
 514         /* pin the new buffer */
 515         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 516                          work->old_rbo, new_rbo);
 517
 518         r = radeon_bo_reserve(new_rbo, false);
 519         if (unlikely(r != 0)) {
 520                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 521                 goto cleanup;
 522         }
 523         /* Only 27 bit offset for legacy CRTC */
 524         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 525                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 526         if (unlikely(r != 0)) {
 527                 radeon_bo_unreserve(new_rbo);
 528                 r = -EINVAL;
 529                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 530                 goto cleanup;
 531         }
 532         work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
 533         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 534         radeon_bo_unreserve(new_rbo);
 535
 536         if (!ASIC_IS_AVIVO(rdev)) {
 537                 /* crtc offset is from display base addr not FB location */
 538                 base -= radeon_crtc->legacy_display_base_addr;
 539                 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 540
 541                 if (tiling_flags & RADEON_TILING_MACRO) {
 542                         if (ASIC_IS_R300(rdev)) {
 543                                 base &= ~0x7ff;
 544                         } else {
 545                                 int byteshift = fb->format->cpp[0] * 8 >> 4;
 546                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 547                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 548                         }
 549                 } else {
 550                         int offset = crtc->y * pitch_pixels + crtc->x;
 551                         switch (fb->format->cpp[0] * 8) {
 552                         case 8:
 553                         default:
 554                                 offset *= 1;
 555                                 break;
 556                         case 15:
 557                         case 16:
 558                                 offset *= 2;
 559                                 break;
 560                         case 24:
 561                                 offset *= 3;
 562                                 break;
 563                         case 32:
 564                                 offset *= 4;
 565                                 break;
 566                         }
 567                         base += offset;
 568                 }
 569                 base &= ~7;
 570         }
 571         work->base = base;
 572         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 573                 dev->driver->get_vblank_counter(dev, work->crtc_id);
 574
 575         /* We borrow the event spin lock for protecting flip_work */
 576         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 577
 578         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 579                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 580                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 581                 r = -EBUSY;
 582                 goto pflip_cleanup;
 583         }
 584         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 585         radeon_crtc->flip_work = work;
 586
 587         /* update crtc fb */
 588         crtc->primary->fb = fb;
 589
 590         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 591
 592         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 593         return 0;
 594
 595 pflip_cleanup:
 596         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 597                 DRM_ERROR("failed to reserve new rbo in error path\n");
 598                 goto cleanup;
 599         }
 600         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 601                 DRM_ERROR("failed to unpin new rbo in error path\n");
 602         }
 603         radeon_bo_unreserve(new_rbo);
 604
 605 cleanup:
 606         drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
 607         dma_fence_put(work->fence);
 608         kfree(work);
 609         return r;
 610 }
 611
 612 static int
 613 radeon_crtc_set_config(struct drm_mode_set *set,
 614                        struct drm_modeset_acquire_ctx *ctx)
 615 {
 616         struct drm_device *dev;
 617         struct radeon_device *rdev;
 618         struct drm_crtc *crtc;
 619         bool active = false;
 620         int ret;
 621
 622         if (!set || !set->crtc)
 623                 return -EINVAL;
 624
 625         dev = set->crtc->dev;
 626
 627         ret = pm_runtime_get_sync(dev->dev);
 628         if (ret < 0) {
 629                 pm_runtime_put_autosuspend(dev->dev);
 630                 return ret;
 631         }
 632
 633         ret = drm_crtc_helper_set_config(set, ctx);
 634
 635         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 636                 if (crtc->enabled)
 637                         active = true;
 638
 639         pm_runtime_mark_last_busy(dev->dev);
 640
 641         rdev = dev->dev_private;
 642         /* if we have active crtcs and we don't have a power ref,
 643            take the current one */
 644         if (active && !rdev->have_disp_power_ref) {
 645                 rdev->have_disp_power_ref = true;
 646                 return ret;
 647         }
 648         /* if we have no active crtcs, then drop the power ref
 649            we got before */
 650         if (!active && rdev->have_disp_power_ref) {
 651                 pm_runtime_put_autosuspend(dev->dev);
 652                 rdev->have_disp_power_ref = false;
 653         }
 654
 655         /* drop the power reference we got coming in here */
 656         pm_runtime_put_autosuspend(dev->dev);
 657         return ret;
 658 }
 659
 660 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 661         .cursor_set2 = radeon_crtc_cursor_set2,
 662         .cursor_move = radeon_crtc_cursor_move,
 663         .gamma_set = radeon_crtc_gamma_set,
 664         .set_config = radeon_crtc_set_config,
 665         .destroy = radeon_crtc_destroy,
 666         .page_flip_target = radeon_crtc_page_flip_target,
 667 };
 668
 669 static void radeon_crtc_init(struct drm_device *dev, int index)
 670 {
 671         struct radeon_device *rdev = dev->dev_private;
 672         struct radeon_crtc *radeon_crtc;
 673         int i;
 674
 675         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 676         if (radeon_crtc == NULL)
 677                 return;
 678
 679         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 680
 681         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 682         radeon_crtc->crtc_id = index;
 683         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 684         rdev->mode_info.crtcs[index] = radeon_crtc;
 685
 686         if (rdev->family >= CHIP_BONAIRE) {
 687                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 688                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 689         } else {
 690                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 691                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 692         }
 693         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 694         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 695
 696 #if 0
 697         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 698         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 699         radeon_crtc->mode_set.num_connectors = 0;
 700 #endif
 701
 702         for (i = 0; i < 256; i++) {
 703                 radeon_crtc->lut_r[i] = i << 2;
 704                 radeon_crtc->lut_g[i] = i << 2;
 705                 radeon_crtc->lut_b[i] = i << 2;
 706         }
 707
 708         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 709                 radeon_atombios_init_crtc(dev, radeon_crtc);
 710         else
 711                 radeon_legacy_init_crtc(dev, radeon_crtc);
 712 }
 713
 714 static const char *encoder_names[38] = {
 715         "NONE",
 716         "INTERNAL_LVDS",
 717         "INTERNAL_TMDS1",
 718         "INTERNAL_TMDS2",
 719         "INTERNAL_DAC1",
 720         "INTERNAL_DAC2",
 721         "INTERNAL_SDVOA",
 722         "INTERNAL_SDVOB",
 723         "SI170B",
 724         "CH7303",
 725         "CH7301",
 726         "INTERNAL_DVO1",
 727         "EXTERNAL_SDVOA",
 728         "EXTERNAL_SDVOB",
 729         "TITFP513",
 730         "INTERNAL_LVTM1",
 731         "VT1623",
 732         "HDMI_SI1930",
 733         "HDMI_INTERNAL",
 734         "INTERNAL_KLDSCP_TMDS1",
 735         "INTERNAL_KLDSCP_DVO1",
 736         "INTERNAL_KLDSCP_DAC1",
 737         "INTERNAL_KLDSCP_DAC2",
 738         "SI178",
 739         "MVPU_FPGA",
 740         "INTERNAL_DDI",
 741         "VT1625",
 742         "HDMI_SI1932",
 743         "DP_AN9801",
 744         "DP_DP501",
 745         "INTERNAL_UNIPHY",
 746         "INTERNAL_KLDSCP_LVTMA",
 747         "INTERNAL_UNIPHY1",
 748         "INTERNAL_UNIPHY2",
 749         "NUTMEG",
 750         "TRAVIS",
 751         "INTERNAL_VCE",
 752         "INTERNAL_UNIPHY3",
 753 };
 754
 755 static const char *hpd_names[6] = {
 756         "HPD1",
 757         "HPD2",
 758         "HPD3",
 759         "HPD4",
 760         "HPD5",
 761         "HPD6",
 762 };
 763
 764 static void radeon_print_display_setup(struct drm_device *dev)
 765 {
 766         struct drm_connector *connector;
 767         struct radeon_connector *radeon_connector;
 768         struct drm_encoder *encoder;
 769         struct radeon_encoder *radeon_encoder;
 770         uint32_t devices;
 771         int i = 0;
 772
 773         DRM_INFO("Radeon Display Connectors\n");
 774         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 775                 radeon_connector = to_radeon_connector(connector);
 776                 DRM_INFO("Connector %d:\n", i);
 777                 DRM_INFO("  %s\n", connector->name);
 778                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 779                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 780                 if (radeon_connector->ddc_bus) {
 781                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 782                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 783                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 784                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 785                                  radeon_connector->ddc_bus->rec.a_data_reg,
 786                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 787                                  radeon_connector->ddc_bus->rec.en_data_reg,
 788                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 789                                  radeon_connector->ddc_bus->rec.y_data_reg);
 790                         if (radeon_connector->router.ddc_valid)
 791                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 792                                          radeon_connector->router.ddc_mux_control_pin,
 793                                          radeon_connector->router.ddc_mux_state);
 794                         if (radeon_connector->router.cd_valid)
 795                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 796                                          radeon_connector->router.cd_mux_control_pin,
 797                                          radeon_connector->router.cd_mux_state);
 798                 } else {
 799                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 800                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 801                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 802                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 803                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 804                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 805                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 806                 }
 807                 DRM_INFO("  Encoders:\n");
 808                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 809                         radeon_encoder = to_radeon_encoder(encoder);
 810                         devices = radeon_encoder->devices & radeon_connector->devices;
 811                         if (devices) {
 812                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 813                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 814                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 815                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 816                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 817                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 818                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 819                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 820                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 821                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 822                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 823                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 824                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 825                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 826                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 827                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 828                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 829                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 830                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 831                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 832                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 833                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 834                         }
 835                 }
 836                 i++;
 837         }
 838 }
 839
 840 static bool radeon_setup_enc_conn(struct drm_device *dev)
 841 {
 842         struct radeon_device *rdev = dev->dev_private;
 843         bool ret = false;
 844
 845         if (rdev->bios) {
 846                 if (rdev->is_atom_bios) {
 847                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 848                         if (ret == false)
 849                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 850                 } else {
 851                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 852                         if (ret == false)
 853                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 854                 }
 855         } else {
 856                 if (!ASIC_IS_AVIVO(rdev))
 857                         ret = radeon_get_legacy_connector_info_from_table(dev);
 858         }
 859         if (ret) {
 860                 radeon_setup_encoder_clones(dev);
 861                 radeon_print_display_setup(dev);
 862         }
 863
 864         return ret;
 865 }
 866
 867 /* avivo */
 868
 869 /**
 870  * avivo_reduce_ratio - fractional number reduction
 871  *
 872  * @nom: nominator
 873  * @den: denominator
 874  * @nom_min: minimum value for nominator
 875  * @den_min: minimum value for denominator
 876  *
 877  * Find the greatest common divisor and apply it on both nominator and
 878  * denominator, but make nominator and denominator are at least as large
 879  * as their minimum values.
 880  */
 881 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 882                                unsigned nom_min, unsigned den_min)
 883 {
 884         unsigned tmp;
 885
 886         /* reduce the numbers to a simpler ratio */
 887         tmp = gcd(*nom, *den);
 888         *nom /= tmp;
 889         *den /= tmp;
 890
 891         /* make sure nominator is large enough */
 892         if (*nom < nom_min) {
 893                 tmp = DIV_ROUND_UP(nom_min, *nom);
 894                 *nom *= tmp;
 895                 *den *= tmp;
 896         }
 897
 898         /* make sure the denominator is large enough */
 899         if (*den < den_min) {
 900                 tmp = DIV_ROUND_UP(den_min, *den);
 901                 *nom *= tmp;
 902                 *den *= tmp;
 903         }
 904 }
 905
 906 /**
 907  * avivo_get_fb_ref_div - feedback and ref divider calculation
 908  *
 909  * @nom: nominator
 910  * @den: denominator
 911  * @post_div: post divider
 912  * @fb_div_max: feedback divider maximum
 913  * @ref_div_max: reference divider maximum
 914  * @fb_div: resulting feedback divider
 915  * @ref_div: resulting reference divider
 916  *
 917  * Calculate feedback and reference divider for a given post divider. Makes
 918  * sure we stay within the limits.
 919  */
 920 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 921                                  unsigned fb_div_max, unsigned ref_div_max,
 922                                  unsigned *fb_div, unsigned *ref_div)
 923 {
 924         /* limit reference * post divider to a maximum */
 925         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 926
 927         /* get matching reference and feedback divider */
 928         *ref_div = min(max(den/post_div, 1u), ref_div_max);
 929         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 930
 931         /* limit fb divider to its maximum */
 932         if (*fb_div > fb_div_max) {
 933                 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
 934                 *fb_div = fb_div_max;
 935         }
 936 }
 937
 938 /**
 939  * radeon_compute_pll_avivo - compute PLL paramaters
 940  *
 941  * @pll: information about the PLL
 942  * @dot_clock_p: resulting pixel clock
 943  * fb_div_p: resulting feedback divider
 944  * frac_fb_div_p: fractional part of the feedback divider
 945  * ref_div_p: resulting reference divider
 946  * post_div_p: resulting reference divider
 947  *
 948  * Try to calculate the PLL parameters to generate the given frequency:
 949  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 950  */
 951 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 952                               u32 freq,
 953                               u32 *dot_clock_p,
 954                               u32 *fb_div_p,
 955                               u32 *frac_fb_div_p,
 956                               u32 *ref_div_p,
 957                               u32 *post_div_p)
 958 {
 959         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 960                 freq : freq / 10;
 961
 962         unsigned fb_div_min, fb_div_max, fb_div;
 963         unsigned post_div_min, post_div_max, post_div;
 964         unsigned ref_div_min, ref_div_max, ref_div;
 965         unsigned post_div_best, diff_best;
 966         unsigned nom, den;
 967
 968         /* determine allowed feedback divider range */
 969         fb_div_min = pll->min_feedback_div;
 970         fb_div_max = pll->max_feedback_div;
 971
 972         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 973                 fb_div_min *= 10;
 974                 fb_div_max *= 10;
 975         }
 976
 977         /* determine allowed ref divider range */
 978         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 979                 ref_div_min = pll->reference_div;
 980         else
 981                 ref_div_min = pll->min_ref_div;
 982
 983         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 984             pll->flags & RADEON_PLL_USE_REF_DIV)
 985                 ref_div_max = pll->reference_div;
 986         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 987                 /* fix for problems on RS880 */
 988                 ref_div_max = min(pll->max_ref_div, 7u);
 989         else
 990                 ref_div_max = pll->max_ref_div;
 991
 992         /* determine allowed post divider range */
 993         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 994                 post_div_min = pll->post_div;
 995                 post_div_max = pll->post_div;
 996         } else {
 997                 unsigned vco_min, vco_max;
 998
 999                 if (pll->flags & RADEON_PLL_IS_LCD) {
1000                         vco_min = pll->lcd_pll_out_min;
1001                         vco_max = pll->lcd_pll_out_max;
1002                 } else {
1003                         vco_min = pll->pll_out_min;
1004                         vco_max = pll->pll_out_max;
1005                 }
1006
1007                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1008                         vco_min *= 10;
1009                         vco_max *= 10;
1010                 }
1011
1012                 post_div_min = vco_min / target_clock;
1013                 if ((target_clock * post_div_min) < vco_min)
1014                         ++post_div_min;
1015                 if (post_div_min < pll->min_post_div)
1016                         post_div_min = pll->min_post_div;
1017
1018                 post_div_max = vco_max / target_clock;
1019                 if ((target_clock * post_div_max) > vco_max)
1020                         --post_div_max;
1021                 if (post_div_max > pll->max_post_div)
1022                         post_div_max = pll->max_post_div;
1023         }
1024
1025         /* represent the searched ratio as fractional number */
1026         nom = target_clock;
1027         den = pll->reference_freq;
1028
1029         /* reduce the numbers to a simpler ratio */
1030         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1031
1032         /* now search for a post divider */
1033         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1034                 post_div_best = post_div_min;
1035         else
1036                 post_div_best = post_div_max;
1037         diff_best = ~0;
1038
1039         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1040                 unsigned diff;
1041                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1042                                      ref_div_max, &fb_div, &ref_div);
1043                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1044                         (ref_div * post_div));
1045
1046                 if (diff < diff_best || (diff == diff_best &&
1047                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1048
1049                         post_div_best = post_div;
1050                         diff_best = diff;
1051                 }
1052         }
1053         post_div = post_div_best;
1054
1055         /* get the feedback and reference divider for the optimal value */
1056         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1057                              &fb_div, &ref_div);
1058
1059         /* reduce the numbers to a simpler ratio once more */
1060         /* this also makes sure that the reference divider is large enough */
1061         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1062
1063         /* avoid high jitter with small fractional dividers */
1064         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1065                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1066                 if (fb_div < fb_div_min) {
1067                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1068                         fb_div *= tmp;
1069                         ref_div *= tmp;
1070                 }
1071         }
1072
1073         /* and finally save the result */
1074         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1075                 *fb_div_p = fb_div / 10;
1076                 *frac_fb_div_p = fb_div % 10;
1077         } else {
1078                 *fb_div_p = fb_div;
1079                 *frac_fb_div_p = 0;
1080         }
1081
1082         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1083                         (pll->reference_freq * *frac_fb_div_p)) /
1084                        (ref_div * post_div * 10);
1085         *ref_div_p = ref_div;
1086         *post_div_p = post_div;
1087
1088         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1089                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1090                       ref_div, post_div);
1091 }
1092
1093 /* pre-avivo */
1094 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1095 {
1096         uint64_t mod;
1097
1098         n += d / 2;
1099
1100         mod = do_div(n, d);
1101         return n;
1102 }
1103
1104 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1105                                uint64_t freq,
1106                                uint32_t *dot_clock_p,
1107                                uint32_t *fb_div_p,
1108                                uint32_t *frac_fb_div_p,
1109                                uint32_t *ref_div_p,
1110                                uint32_t *post_div_p)
1111 {
1112         uint32_t min_ref_div = pll->min_ref_div;
1113         uint32_t max_ref_div = pll->max_ref_div;
1114         uint32_t min_post_div = pll->min_post_div;
1115         uint32_t max_post_div = pll->max_post_div;
1116         uint32_t min_fractional_feed_div = 0;
1117         uint32_t max_fractional_feed_div = 0;
1118         uint32_t best_vco = pll->best_vco;
1119         uint32_t best_post_div = 1;
1120         uint32_t best_ref_div = 1;
1121         uint32_t best_feedback_div = 1;
1122         uint32_t best_frac_feedback_div = 0;
1123         uint32_t best_freq = -1;
1124         uint32_t best_error = 0xffffffff;
1125         uint32_t best_vco_diff = 1;
1126         uint32_t post_div;
1127         u32 pll_out_min, pll_out_max;
1128
1129         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1130         freq = freq * 1000;
1131
1132         if (pll->flags & RADEON_PLL_IS_LCD) {
1133                 pll_out_min = pll->lcd_pll_out_min;
1134                 pll_out_max = pll->lcd_pll_out_max;
1135         } else {
1136                 pll_out_min = pll->pll_out_min;
1137                 pll_out_max = pll->pll_out_max;
1138         }
1139
1140         if (pll_out_min > 64800)
1141                 pll_out_min = 64800;
1142
1143         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1144                 min_ref_div = max_ref_div = pll->reference_div;
1145         else {
1146                 while (min_ref_div < max_ref_div-1) {
1147                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1148                         uint32_t pll_in = pll->reference_freq / mid;
1149                         if (pll_in < pll->pll_in_min)
1150                                 max_ref_div = mid;
1151                         else if (pll_in > pll->pll_in_max)
1152                                 min_ref_div = mid;
1153                         else
1154                                 break;
1155                 }
1156         }
1157
1158         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1159                 min_post_div = max_post_div = pll->post_div;
1160
1161         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1162                 min_fractional_feed_div = pll->min_frac_feedback_div;
1163                 max_fractional_feed_div = pll->max_frac_feedback_div;
1164         }
1165
1166         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1167                 uint32_t ref_div;
1168
1169                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1170                         continue;
1171
1172                 /* legacy radeons only have a few post_divs */
1173                 if (pll->flags & RADEON_PLL_LEGACY) {
1174                         if ((post_div == 5) ||
1175                             (post_div == 7) ||
1176                             (post_div == 9) ||
1177                             (post_div == 10) ||
1178                             (post_div == 11) ||
1179                             (post_div == 13) ||
1180                             (post_div == 14) ||
1181                             (post_div == 15))
1182                                 continue;
1183                 }
1184
1185                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1186                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1187                         uint32_t pll_in = pll->reference_freq / ref_div;
1188                         uint32_t min_feed_div = pll->min_feedback_div;
1189                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1190
1191                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1192                                 continue;
1193
1194                         while (min_feed_div < max_feed_div) {
1195                                 uint32_t vco;
1196                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1197                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1198                                 uint32_t frac_feedback_div;
1199                                 uint64_t tmp;
1200
1201                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1202
1203                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1204                                 vco = radeon_div(tmp, ref_div);
1205
1206                                 if (vco < pll_out_min) {
1207                                         min_feed_div = feedback_div + 1;
1208                                         continue;
1209                                 } else if (vco > pll_out_max) {
1210                                         max_feed_div = feedback_div;
1211                                         continue;
1212                                 }
1213
1214                                 while (min_frac_feed_div < max_frac_feed_div) {
1215                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1216                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1217                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1218                                         current_freq = radeon_div(tmp, ref_div * post_div);
1219
1220                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1221                                                 if (freq < current_freq)
1222                                                         error = 0xffffffff;
1223                                                 else
1224                                                         error = freq - current_freq;
1225                                         } else
1226                                                 error = abs(current_freq - freq);
1227                                         vco_diff = abs(vco - best_vco);
1228
1229                                         if ((best_vco == 0 && error < best_error) ||
1230                                             (best_vco != 0 &&
1231                                              ((best_error > 100 && error < best_error - 100) ||
1232                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1233                                                 best_post_div = post_div;
1234                                                 best_ref_div = ref_div;
1235                                                 best_feedback_div = feedback_div;
1236                                                 best_frac_feedback_div = frac_feedback_div;
1237                                                 best_freq = current_freq;
1238                                                 best_error = error;
1239                                                 best_vco_diff = vco_diff;
1240                                         } else if (current_freq == freq) {
1241                                                 if (best_freq == -1) {
1242                                                         best_post_div = post_div;
1243                                                         best_ref_div = ref_div;
1244                                                         best_feedback_div = feedback_div;
1245                                                         best_frac_feedback_div = frac_feedback_div;
1246                                                         best_freq = current_freq;
1247                                                         best_error = error;
1248                                                         best_vco_diff = vco_diff;
1249                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1250                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1251                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1252                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1253                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1254                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1255                                                         best_post_div = post_div;
1256                                                         best_ref_div = ref_div;
1257                                                         best_feedback_div = feedback_div;
1258                                                         best_frac_feedback_div = frac_feedback_div;
1259                                                         best_freq = current_freq;
1260                                                         best_error = error;
1261                                                         best_vco_diff = vco_diff;
1262                                                 }
1263                                         }
1264                                         if (current_freq < freq)
1265                                                 min_frac_feed_div = frac_feedback_div + 1;
1266                                         else
1267                                                 max_frac_feed_div = frac_feedback_div;
1268                                 }
1269                                 if (current_freq < freq)
1270                                         min_feed_div = feedback_div + 1;
1271                                 else
1272                                         max_feed_div = feedback_div;
1273                         }
1274                 }
1275         }
1276
1277         *dot_clock_p = best_freq / 10000;
1278         *fb_div_p = best_feedback_div;
1279         *frac_fb_div_p = best_frac_feedback_div;
1280         *ref_div_p = best_ref_div;
1281         *post_div_p = best_post_div;
1282         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1283                       (long long)freq,
1284                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1285                       best_ref_div, best_post_div);
1286
1287 }
1288
1289 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1290         .destroy = drm_gem_fb_destroy,
1291         .create_handle = drm_gem_fb_create_handle,
1292 };
1293
1294 int
1295 radeon_framebuffer_init(struct drm_device *dev,
1296                         struct drm_framebuffer *fb,
1297                         const struct drm_mode_fb_cmd2 *mode_cmd,
1298                         struct drm_gem_object *obj)
1299 {
1300         int ret;
1301         fb->obj[0] = obj;
1302         drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1303         ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1304         if (ret) {
1305                 fb->obj[0] = NULL;
1306                 return ret;
1307         }
1308         return 0;
1309 }
1310
1311 static struct drm_framebuffer *
1312 radeon_user_framebuffer_create(struct drm_device *dev,
1313                                struct drm_file *file_priv,
1314                                const struct drm_mode_fb_cmd2 *mode_cmd)
1315 {
1316         struct drm_gem_object *obj;
1317         struct drm_framebuffer *fb;
1318         int ret;
1319
1320         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1321         if (obj ==  NULL) {
1322                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1323                         "can't create framebuffer\n", mode_cmd->handles[0]);
1324                 return ERR_PTR(-ENOENT);
1325         }
1326
1327         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1328         if (obj->import_attach) {
1329                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1330                 drm_gem_object_put(obj);
1331                 return ERR_PTR(-EINVAL);
1332         }
1333
1334         fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1335         if (fb == NULL) {
1336                 drm_gem_object_put_unlocked(obj);
1337                 return ERR_PTR(-ENOMEM);
1338         }
1339
1340         ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1341         if (ret) {
1342                 kfree(fb);
1343                 drm_gem_object_put_unlocked(obj);
1344                 return ERR_PTR(ret);
1345         }
1346
1347         return fb;
1348 }
1349
1350 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1351         .fb_create = radeon_user_framebuffer_create,
1352         .output_poll_changed = drm_fb_helper_output_poll_changed,
1353 };
1354
1355 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1356 {       { 0, "driver" },
1357         { 1, "bios" },
1358 };
1359
1360 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1361 {       { TV_STD_NTSC, "ntsc" },
1362         { TV_STD_PAL, "pal" },
1363         { TV_STD_PAL_M, "pal-m" },
1364         { TV_STD_PAL_60, "pal-60" },
1365         { TV_STD_NTSC_J, "ntsc-j" },
1366         { TV_STD_SCART_PAL, "scart-pal" },
1367         { TV_STD_PAL_CN, "pal-cn" },
1368         { TV_STD_SECAM, "secam" },
1369 };
1370
1371 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1372 {       { UNDERSCAN_OFF, "off" },
1373         { UNDERSCAN_ON, "on" },
1374         { UNDERSCAN_AUTO, "auto" },
1375 };
1376
1377 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1378 {       { RADEON_AUDIO_DISABLE, "off" },
1379         { RADEON_AUDIO_ENABLE, "on" },
1380         { RADEON_AUDIO_AUTO, "auto" },
1381 };
1382
1383 /* XXX support different dither options? spatial, temporal, both, etc. */
1384 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1385 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1386         { RADEON_FMT_DITHER_ENABLE, "on" },
1387 };
1388
1389 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1390 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1391         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1392         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1393         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1394 };
1395
1396 static int radeon_modeset_create_props(struct radeon_device *rdev)
1397 {
1398         int sz;
1399
1400         if (rdev->is_atom_bios) {
1401                 rdev->mode_info.coherent_mode_property =
1402                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1403                 if (!rdev->mode_info.coherent_mode_property)
1404                         return -ENOMEM;
1405         }
1406
1407         if (!ASIC_IS_AVIVO(rdev)) {
1408                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1409                 rdev->mode_info.tmds_pll_property =
1410                         drm_property_create_enum(rdev->ddev, 0,
1411                                             "tmds_pll",
1412                                             radeon_tmds_pll_enum_list, sz);
1413         }
1414
1415         rdev->mode_info.load_detect_property =
1416                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1417         if (!rdev->mode_info.load_detect_property)
1418                 return -ENOMEM;
1419
1420         drm_mode_create_scaling_mode_property(rdev->ddev);
1421
1422         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1423         rdev->mode_info.tv_std_property =
1424                 drm_property_create_enum(rdev->ddev, 0,
1425                                     "tv standard",
1426                                     radeon_tv_std_enum_list, sz);
1427
1428         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1429         rdev->mode_info.underscan_property =
1430                 drm_property_create_enum(rdev->ddev, 0,
1431                                     "underscan",
1432                                     radeon_underscan_enum_list, sz);
1433
1434         rdev->mode_info.underscan_hborder_property =
1435                 drm_property_create_range(rdev->ddev, 0,
1436                                         "underscan hborder", 0, 128);
1437         if (!rdev->mode_info.underscan_hborder_property)
1438                 return -ENOMEM;
1439
1440         rdev->mode_info.underscan_vborder_property =
1441                 drm_property_create_range(rdev->ddev, 0,
1442                                         "underscan vborder", 0, 128);
1443         if (!rdev->mode_info.underscan_vborder_property)
1444                 return -ENOMEM;
1445
1446         sz = ARRAY_SIZE(radeon_audio_enum_list);
1447         rdev->mode_info.audio_property =
1448                 drm_property_create_enum(rdev->ddev, 0,
1449                                          "audio",
1450                                          radeon_audio_enum_list, sz);
1451
1452         sz = ARRAY_SIZE(radeon_dither_enum_list);
1453         rdev->mode_info.dither_property =
1454                 drm_property_create_enum(rdev->ddev, 0,
1455                                          "dither",
1456                                          radeon_dither_enum_list, sz);
1457
1458         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1459         rdev->mode_info.output_csc_property =
1460                 drm_property_create_enum(rdev->ddev, 0,
1461                                          "output_csc",
1462                                          radeon_output_csc_enum_list, sz);
1463
1464         return 0;
1465 }
1466
1467 void radeon_update_display_priority(struct radeon_device *rdev)
1468 {
1469         /* adjustment options for the display watermarks */
1470         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1471                 /* set display priority to high for r3xx, rv515 chips
1472                  * this avoids flickering due to underflow to the
1473                  * display controllers during heavy acceleration.
1474                  * Don't force high on rs4xx igp chips as it seems to
1475                  * affect the sound card.  See kernel bug 15982.
1476                  */
1477                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1478                     !(rdev->flags & RADEON_IS_IGP))
1479                         rdev->disp_priority = 2;
1480                 else
1481                         rdev->disp_priority = 0;
1482         } else
1483                 rdev->disp_priority = radeon_disp_priority;
1484
1485 }
1486
1487 /*
1488  * Allocate hdmi structs and determine register offsets
1489  */
1490 static void radeon_afmt_init(struct radeon_device *rdev)
1491 {
1492         int i;
1493
1494         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1495                 rdev->mode_info.afmt[i] = NULL;
1496
1497         if (ASIC_IS_NODCE(rdev)) {
1498                 /* nothing to do */
1499         } else if (ASIC_IS_DCE4(rdev)) {
1500                 static uint32_t eg_offsets[] = {
1501                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1502                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1503                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1504                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1505                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1506                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1507                         0x13830 - 0x7030,
1508                 };
1509                 int num_afmt;
1510
1511                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1512                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1513                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1514                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1515                 if (ASIC_IS_DCE8(rdev))
1516                         num_afmt = 7;
1517                 else if (ASIC_IS_DCE6(rdev))
1518                         num_afmt = 6;
1519                 else if (ASIC_IS_DCE5(rdev))
1520                         num_afmt = 6;
1521                 else if (ASIC_IS_DCE41(rdev))
1522                         num_afmt = 2;
1523                 else /* DCE4 */
1524                         num_afmt = 6;
1525
1526                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1527                 for (i = 0; i < num_afmt; i++) {
1528                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1529                         if (rdev->mode_info.afmt[i]) {
1530                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1531                                 rdev->mode_info.afmt[i]->id = i;
1532                         }
1533                 }
1534         } else if (ASIC_IS_DCE3(rdev)) {
1535                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1536                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1537                 if (rdev->mode_info.afmt[0]) {
1538                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1539                         rdev->mode_info.afmt[0]->id = 0;
1540                 }
1541                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1542                 if (rdev->mode_info.afmt[1]) {
1543                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1544                         rdev->mode_info.afmt[1]->id = 1;
1545                 }
1546         } else if (ASIC_IS_DCE2(rdev)) {
1547                 /* DCE2 has at least 1 routable audio block */
1548                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1549                 if (rdev->mode_info.afmt[0]) {
1550                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1551                         rdev->mode_info.afmt[0]->id = 0;
1552                 }
1553                 /* r6xx has 2 routable audio blocks */
1554                 if (rdev->family >= CHIP_R600) {
1555                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1556                         if (rdev->mode_info.afmt[1]) {
1557                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1558                                 rdev->mode_info.afmt[1]->id = 1;
1559                         }
1560                 }
1561         }
1562 }
1563
1564 static void radeon_afmt_fini(struct radeon_device *rdev)
1565 {
1566         int i;
1567
1568         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1569                 kfree(rdev->mode_info.afmt[i]);
1570                 rdev->mode_info.afmt[i] = NULL;
1571         }
1572 }
1573
1574 int radeon_modeset_init(struct radeon_device *rdev)
1575 {
1576         int i;
1577         int ret;
1578
1579         drm_mode_config_init(rdev->ddev);
1580         rdev->mode_info.mode_config_initialized = true;
1581
1582         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1583
1584         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1585                 rdev->ddev->mode_config.async_page_flip = true;
1586
1587         if (ASIC_IS_DCE5(rdev)) {
1588                 rdev->ddev->mode_config.max_width = 16384;
1589                 rdev->ddev->mode_config.max_height = 16384;
1590         } else if (ASIC_IS_AVIVO(rdev)) {
1591                 rdev->ddev->mode_config.max_width = 8192;
1592                 rdev->ddev->mode_config.max_height = 8192;
1593         } else {
1594                 rdev->ddev->mode_config.max_width = 4096;
1595                 rdev->ddev->mode_config.max_height = 4096;
1596         }
1597
1598         rdev->ddev->mode_config.preferred_depth = 24;
1599         rdev->ddev->mode_config.prefer_shadow = 1;
1600
1601         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1602
1603         ret = radeon_modeset_create_props(rdev);
1604         if (ret) {
1605                 return ret;
1606         }
1607
1608         /* init i2c buses */
1609         radeon_i2c_init(rdev);
1610
1611         /* check combios for a valid hardcoded EDID - Sun servers */
1612         if (!rdev->is_atom_bios) {
1613                 /* check for hardcoded EDID in BIOS */
1614                 radeon_combios_check_hardcoded_edid(rdev);
1615         }
1616
1617         /* allocate crtcs */
1618         for (i = 0; i < rdev->num_crtc; i++) {
1619                 radeon_crtc_init(rdev->ddev, i);
1620         }
1621
1622         /* okay we should have all the bios connectors */
1623         ret = radeon_setup_enc_conn(rdev->ddev);
1624         if (!ret) {
1625                 return ret;
1626         }
1627
1628         /* init dig PHYs, disp eng pll */
1629         if (rdev->is_atom_bios) {
1630                 radeon_atom_encoder_init(rdev);
1631                 radeon_atom_disp_eng_pll_init(rdev);
1632         }
1633
1634         /* initialize hpd */
1635         radeon_hpd_init(rdev);
1636
1637         /* setup afmt */
1638         radeon_afmt_init(rdev);
1639
1640         radeon_fbdev_init(rdev);
1641         drm_kms_helper_poll_init(rdev->ddev);
1642
1643         /* do pm late init */
1644         ret = radeon_pm_late_init(rdev);
1645
1646         return 0;
1647 }
1648
1649 void radeon_modeset_fini(struct radeon_device *rdev)
1650 {
1651         if (rdev->mode_info.mode_config_initialized) {
1652                 drm_kms_helper_poll_fini(rdev->ddev);
1653                 radeon_hpd_fini(rdev);
1654                 drm_crtc_force_disable_all(rdev->ddev);
1655                 radeon_fbdev_fini(rdev);
1656                 radeon_afmt_fini(rdev);
1657                 drm_mode_config_cleanup(rdev->ddev);
1658                 rdev->mode_info.mode_config_initialized = false;
1659         }
1660
1661         kfree(rdev->mode_info.bios_hardcoded_edid);
1662
1663         /* free i2c buses */
1664         radeon_i2c_fini(rdev);
1665 }
1666
1667 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1668 {
1669         /* try and guess if this is a tv or a monitor */
1670         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1671             (mode->vdisplay == 576) || /* 576p */
1672             (mode->vdisplay == 720) || /* 720p */
1673             (mode->vdisplay == 1080)) /* 1080p */
1674                 return true;
1675         else
1676                 return false;
1677 }
1678
1679 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1680                                 const struct drm_display_mode *mode,
1681                                 struct drm_display_mode *adjusted_mode)
1682 {
1683         struct drm_device *dev = crtc->dev;
1684         struct radeon_device *rdev = dev->dev_private;
1685         struct drm_encoder *encoder;
1686         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1687         struct radeon_encoder *radeon_encoder;
1688         struct drm_connector *connector;
1689         struct radeon_connector *radeon_connector;
1690         bool first = true;
1691         u32 src_v = 1, dst_v = 1;
1692         u32 src_h = 1, dst_h = 1;
1693
1694         radeon_crtc->h_border = 0;
1695         radeon_crtc->v_border = 0;
1696
1697         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1698                 if (encoder->crtc != crtc)
1699                         continue;
1700                 radeon_encoder = to_radeon_encoder(encoder);
1701                 connector = radeon_get_connector_for_encoder(encoder);
1702                 radeon_connector = to_radeon_connector(connector);
1703
1704                 if (first) {
1705                         /* set scaling */
1706                         if (radeon_encoder->rmx_type == RMX_OFF)
1707                                 radeon_crtc->rmx_type = RMX_OFF;
1708                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1709                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1710                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1711                         else
1712                                 radeon_crtc->rmx_type = RMX_OFF;
1713                         /* copy native mode */
1714                         memcpy(&radeon_crtc->native_mode,
1715                                &radeon_encoder->native_mode,
1716                                 sizeof(struct drm_display_mode));
1717                         src_v = crtc->mode.vdisplay;
1718                         dst_v = radeon_crtc->native_mode.vdisplay;
1719                         src_h = crtc->mode.hdisplay;
1720                         dst_h = radeon_crtc->native_mode.hdisplay;
1721
1722                         /* fix up for overscan on hdmi */
1723                         if (ASIC_IS_AVIVO(rdev) &&
1724                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1725                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1726                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1727                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1728                               is_hdtv_mode(mode)))) {
1729                                 if (radeon_encoder->underscan_hborder != 0)
1730                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1731                                 else
1732                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1733                                 if (radeon_encoder->underscan_vborder != 0)
1734                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1735                                 else
1736                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1737                                 radeon_crtc->rmx_type = RMX_FULL;
1738                                 src_v = crtc->mode.vdisplay;
1739                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1740                                 src_h = crtc->mode.hdisplay;
1741                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1742                         }
1743                         first = false;
1744                 } else {
1745                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1746                                 /* WARNING: Right now this can't happen but
1747                                  * in the future we need to check that scaling
1748                                  * are consistent across different encoder
1749                                  * (ie all encoder can work with the same
1750                                  *  scaling).
1751                                  */
1752                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1753                                 return false;
1754                         }
1755                 }
1756         }
1757         if (radeon_crtc->rmx_type != RMX_OFF) {
1758                 fixed20_12 a, b;
1759                 a.full = dfixed_const(src_v);
1760                 b.full = dfixed_const(dst_v);
1761                 radeon_crtc->vsc.full = dfixed_div(a, b);
1762                 a.full = dfixed_const(src_h);
1763                 b.full = dfixed_const(dst_h);
1764                 radeon_crtc->hsc.full = dfixed_div(a, b);
1765         } else {
1766                 radeon_crtc->vsc.full = dfixed_const(1);
1767                 radeon_crtc->hsc.full = dfixed_const(1);
1768         }
1769         return true;
1770 }
1771
1772 /*
1773  * Retrieve current video scanout position of crtc on a given gpu, and
1774  * an optional accurate timestamp of when query happened.
1775  *
1776  * \param dev Device to query.
1777  * \param crtc Crtc to query.
1778  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1779  *              For driver internal use only also supports these flags:
1780  *
1781  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1782  *              of a fudged earlier start of vblank.
1783  *
1784  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1785  *              fudged earlier start of vblank in *vpos and the distance
1786  *              to true start of vblank in *hpos.
1787  *
1788  * \param *vpos Location where vertical scanout position should be stored.
1789  * \param *hpos Location where horizontal scanout position should go.
1790  * \param *stime Target location for timestamp taken immediately before
1791  *               scanout position query. Can be NULL to skip timestamp.
1792  * \param *etime Target location for timestamp taken immediately after
1793  *               scanout position query. Can be NULL to skip timestamp.
1794  *
1795  * Returns vpos as a positive number while in active scanout area.
1796  * Returns vpos as a negative number inside vblank, counting the number
1797  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1798  * until start of active scanout / end of vblank."
1799  *
1800  * \return Flags, or'ed together as follows:
1801  *
1802  * DRM_SCANOUTPOS_VALID = Query successful.
1803  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1804  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1805  * this flag means that returned position may be offset by a constant but
1806  * unknown small number of scanlines wrt. real scanout position.
1807  *
1808  */
1809 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1810                                unsigned int flags, int *vpos, int *hpos,
1811                                ktime_t *stime, ktime_t *etime,
1812                                const struct drm_display_mode *mode)
1813 {
1814         u32 stat_crtc = 0, vbl = 0, position = 0;
1815         int vbl_start, vbl_end, vtotal, ret = 0;
1816         bool in_vbl = true;
1817
1818         struct radeon_device *rdev = dev->dev_private;
1819
1820         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1821
1822         /* Get optional system timestamp before query. */
1823         if (stime)
1824                 *stime = ktime_get();
1825
1826         if (ASIC_IS_DCE4(rdev)) {
1827                 if (pipe == 0) {
1828                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1829                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1830                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1831                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1832                         ret |= DRM_SCANOUTPOS_VALID;
1833                 }
1834                 if (pipe == 1) {
1835                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1836                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1837                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1838                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1839                         ret |= DRM_SCANOUTPOS_VALID;
1840                 }
1841                 if (pipe == 2) {
1842                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1843                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1844                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1845                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1846                         ret |= DRM_SCANOUTPOS_VALID;
1847                 }
1848                 if (pipe == 3) {
1849                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1850                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1851                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1852                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1853                         ret |= DRM_SCANOUTPOS_VALID;
1854                 }
1855                 if (pipe == 4) {
1856                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1857                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1858                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1859                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1860                         ret |= DRM_SCANOUTPOS_VALID;
1861                 }
1862                 if (pipe == 5) {
1863                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1864                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1865                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1866                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1867                         ret |= DRM_SCANOUTPOS_VALID;
1868                 }
1869         } else if (ASIC_IS_AVIVO(rdev)) {
1870                 if (pipe == 0) {
1871                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1872                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1873                         ret |= DRM_SCANOUTPOS_VALID;
1874                 }
1875                 if (pipe == 1) {
1876                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1877                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1878                         ret |= DRM_SCANOUTPOS_VALID;
1879                 }
1880         } else {
1881                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1882                 if (pipe == 0) {
1883                         /* Assume vbl_end == 0, get vbl_start from
1884                          * upper 16 bits.
1885                          */
1886                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1887                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1888                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1889                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1890                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1891                         if (!(stat_crtc & 1))
1892                                 in_vbl = false;
1893
1894                         ret |= DRM_SCANOUTPOS_VALID;
1895                 }
1896                 if (pipe == 1) {
1897                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1898                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1899                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1900                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1901                         if (!(stat_crtc & 1))
1902                                 in_vbl = false;
1903
1904                         ret |= DRM_SCANOUTPOS_VALID;
1905                 }
1906         }
1907
1908         /* Get optional system timestamp after query. */
1909         if (etime)
1910                 *etime = ktime_get();
1911
1912         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1913
1914         /* Decode into vertical and horizontal scanout position. */
1915         *vpos = position & 0x1fff;
1916         *hpos = (position >> 16) & 0x1fff;
1917
1918         /* Valid vblank area boundaries from gpu retrieved? */
1919         if (vbl > 0) {
1920                 /* Yes: Decode. */
1921                 ret |= DRM_SCANOUTPOS_ACCURATE;
1922                 vbl_start = vbl & 0x1fff;
1923                 vbl_end = (vbl >> 16) & 0x1fff;
1924         }
1925         else {
1926                 /* No: Fake something reasonable which gives at least ok results. */
1927                 vbl_start = mode->crtc_vdisplay;
1928                 vbl_end = 0;
1929         }
1930
1931         /* Called from driver internal vblank counter query code? */
1932         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1933             /* Caller wants distance from real vbl_start in *hpos */
1934             *hpos = *vpos - vbl_start;
1935         }
1936
1937         /* Fudge vblank to start a few scanlines earlier to handle the
1938          * problem that vblank irqs fire a few scanlines before start
1939          * of vblank. Some driver internal callers need the true vblank
1940          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1941          *
1942          * The cause of the "early" vblank irq is that the irq is triggered
1943          * by the line buffer logic when the line buffer read position enters
1944          * the vblank, whereas our crtc scanout position naturally lags the
1945          * line buffer read position.
1946          */
1947         if (!(flags & USE_REAL_VBLANKSTART))
1948                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1949
1950         /* Test scanout position against vblank region. */
1951         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1952                 in_vbl = false;
1953
1954         /* In vblank? */
1955         if (in_vbl)
1956             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1957
1958         /* Called from driver internal vblank counter query code? */
1959         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1960                 /* Caller wants distance from fudged earlier vbl_start */
1961                 *vpos -= vbl_start;
1962                 return ret;
1963         }
1964
1965         /* Check if inside vblank area and apply corrective offsets:
1966          * vpos will then be >=0 in video scanout area, but negative
1967          * within vblank area, counting down the number of lines until
1968          * start of scanout.
1969          */
1970
1971         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1972         if (in_vbl && (*vpos >= vbl_start)) {
1973                 vtotal = mode->crtc_vtotal;
1974                 *vpos = *vpos - vtotal;
1975         }
1976
1977         /* Correct for shifted end of vbl at vbl_end. */
1978         *vpos = *vpos - vbl_end;
1979
1980         return ret;
1981 }