2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39 #define MSM_VERSION_MAJOR 1
40 #define MSM_VERSION_MINOR 3
41 #define MSM_VERSION_PATCHLEVEL 0
43 static const struct drm_mode_config_funcs mode_config_funcs = {
44 .fb_create = msm_framebuffer_create,
45 .output_poll_changed = drm_fb_helper_output_poll_changed,
46 .atomic_check = drm_atomic_helper_check,
47 .atomic_commit = drm_atomic_helper_commit,
50 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
51 .atomic_commit_tail = msm_atomic_commit_tail,
54 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
55 static bool reglog = false;
56 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
57 module_param(reglog, bool, 0600);
62 #ifdef CONFIG_DRM_FBDEV_EMULATION
63 static bool fbdev = true;
64 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
65 module_param(fbdev, bool, 0600);
68 static char *vram = "16m";
69 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
70 module_param(vram, charp, 0);
72 bool dumpstate = false;
73 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
74 module_param(dumpstate, bool, 0600);
76 static bool modeset = true;
77 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
78 module_param(modeset, bool, 0600);
84 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
86 struct property *prop;
88 struct clk_bulk_data *local;
89 int i = 0, ret, count;
91 count = of_property_count_strings(dev->of_node, "clock-names");
95 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
100 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
101 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
103 devm_kfree(dev, local);
110 ret = devm_clk_bulk_get(dev, count, local);
113 for (i = 0; i < count; i++)
114 devm_kfree(dev, (void *) local[i].id);
115 devm_kfree(dev, local);
124 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
130 snprintf(n, sizeof(n), "%s_clk", name);
132 for (i = 0; bulk && i < count; i++) {
133 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
141 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
146 clk = devm_clk_get(&pdev->dev, name);
147 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
150 snprintf(name2, sizeof(name2), "%s_clk", name);
152 clk = devm_clk_get(&pdev->dev, name2);
154 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
155 "\"%s\" instead of \"%s\"\n", name, name2);
160 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
163 struct resource *res;
168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
174 return ERR_PTR(-EINVAL);
177 size = resource_size(res);
179 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
181 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
182 return ERR_PTR(-ENOMEM);
186 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
191 void msm_writel(u32 data, void __iomem *addr)
194 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
198 u32 msm_readl(const void __iomem *addr)
200 u32 val = readl(addr);
202 pr_err("IO:R %p %08x\n", addr, val);
206 struct vblank_event {
207 struct list_head node;
212 static void vblank_ctrl_worker(struct kthread_work *work)
214 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
215 struct msm_vblank_ctrl, work);
216 struct msm_drm_private *priv = container_of(vbl_ctrl,
217 struct msm_drm_private, vblank_ctrl);
218 struct msm_kms *kms = priv->kms;
219 struct vblank_event *vbl_ev, *tmp;
222 spin_lock_irqsave(&vbl_ctrl->lock, flags);
223 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
224 list_del(&vbl_ev->node);
225 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
228 kms->funcs->enable_vblank(kms,
229 priv->crtcs[vbl_ev->crtc_id]);
231 kms->funcs->disable_vblank(kms,
232 priv->crtcs[vbl_ev->crtc_id]);
236 spin_lock_irqsave(&vbl_ctrl->lock, flags);
239 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
242 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
243 int crtc_id, bool enable)
245 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
246 struct vblank_event *vbl_ev;
249 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
253 vbl_ev->crtc_id = crtc_id;
254 vbl_ev->enable = enable;
256 spin_lock_irqsave(&vbl_ctrl->lock, flags);
257 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
258 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
260 kthread_queue_work(&priv->disp_thread[crtc_id].worker,
266 static int msm_drm_uninit(struct device *dev)
268 struct platform_device *pdev = to_platform_device(dev);
269 struct drm_device *ddev = platform_get_drvdata(pdev);
270 struct msm_drm_private *priv = ddev->dev_private;
271 struct msm_kms *kms = priv->kms;
272 struct msm_mdss *mdss = priv->mdss;
273 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
274 struct vblank_event *vbl_ev, *tmp;
277 /* We must cancel and cleanup any pending vblank enable/disable
278 * work before drm_irq_uninstall() to avoid work re-enabling an
279 * irq after uninstall has disabled it.
281 kthread_flush_work(&vbl_ctrl->work);
282 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
283 list_del(&vbl_ev->node);
287 /* clean up display commit/event worker threads */
288 for (i = 0; i < priv->num_crtcs; i++) {
289 if (priv->disp_thread[i].thread) {
290 kthread_flush_worker(&priv->disp_thread[i].worker);
291 kthread_stop(priv->disp_thread[i].thread);
292 priv->disp_thread[i].thread = NULL;
295 if (priv->event_thread[i].thread) {
296 kthread_flush_worker(&priv->event_thread[i].worker);
297 kthread_stop(priv->event_thread[i].thread);
298 priv->event_thread[i].thread = NULL;
302 msm_gem_shrinker_cleanup(ddev);
304 drm_kms_helper_poll_fini(ddev);
306 drm_dev_unregister(ddev);
308 msm_perf_debugfs_cleanup(priv);
309 msm_rd_debugfs_cleanup(priv);
311 #ifdef CONFIG_DRM_FBDEV_EMULATION
312 if (fbdev && priv->fbdev)
313 msm_fbdev_free(ddev);
315 drm_mode_config_cleanup(ddev);
317 pm_runtime_get_sync(dev);
318 drm_irq_uninstall(ddev);
319 pm_runtime_put_sync(dev);
321 flush_workqueue(priv->wq);
322 destroy_workqueue(priv->wq);
324 if (kms && kms->funcs)
325 kms->funcs->destroy(kms);
327 if (priv->vram.paddr) {
328 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
329 drm_mm_takedown(&priv->vram.mm);
330 dma_free_attrs(dev, priv->vram.size, NULL,
331 priv->vram.paddr, attrs);
334 component_unbind_all(dev, ddev);
336 if (mdss && mdss->funcs)
337 mdss->funcs->destroy(ddev);
339 ddev->dev_private = NULL;
351 static int get_mdp_ver(struct platform_device *pdev)
353 struct device *dev = &pdev->dev;
355 return (int) (unsigned long) of_device_get_match_data(dev);
358 #include <linux/of_address.h>
360 static int msm_init_vram(struct drm_device *dev)
362 struct msm_drm_private *priv = dev->dev_private;
363 struct device_node *node;
364 unsigned long size = 0;
367 /* In the device-tree world, we could have a 'memory-region'
368 * phandle, which gives us a link to our "vram". Allocating
369 * is all nicely abstracted behind the dma api, but we need
370 * to know the entire size to allocate it all in one go. There
372 * 1) device with no IOMMU, in which case we need exclusive
373 * access to a VRAM carveout big enough for all gpu
375 * 2) device with IOMMU, but where the bootloader puts up
376 * a splash screen. In this case, the VRAM carveout
377 * need only be large enough for fbdev fb. But we need
378 * exclusive access to the buffer to avoid the kernel
379 * using those pages for other purposes (which appears
380 * as corruption on screen before we have a chance to
381 * load and do initial modeset)
384 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
387 ret = of_address_to_resource(node, 0, &r);
391 size = r.end - r.start;
392 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
394 /* if we have no IOMMU, then we need to use carveout allocator.
395 * Grab the entire CMA chunk carved out in early startup in
398 } else if (!iommu_present(&platform_bus_type)) {
399 DRM_INFO("using %s VRAM carveout\n", vram);
400 size = memparse(vram, NULL);
404 unsigned long attrs = 0;
407 priv->vram.size = size;
409 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
410 spin_lock_init(&priv->vram.lock);
412 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
413 attrs |= DMA_ATTR_WRITE_COMBINE;
415 /* note that for no-kernel-mapping, the vaddr returned
416 * is bogus, but non-null if allocation succeeded:
418 p = dma_alloc_attrs(dev->dev, size,
419 &priv->vram.paddr, GFP_KERNEL, attrs);
421 dev_err(dev->dev, "failed to allocate VRAM\n");
422 priv->vram.paddr = 0;
426 dev_info(dev->dev, "VRAM: %08x->%08x\n",
427 (uint32_t)priv->vram.paddr,
428 (uint32_t)(priv->vram.paddr + size));
434 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
436 struct platform_device *pdev = to_platform_device(dev);
437 struct drm_device *ddev;
438 struct msm_drm_private *priv;
440 struct msm_mdss *mdss;
442 struct sched_param param;
444 ddev = drm_dev_alloc(drv, dev);
446 dev_err(dev, "failed to allocate drm_device\n");
447 return PTR_ERR(ddev);
450 platform_set_drvdata(pdev, ddev);
452 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
455 goto err_unref_drm_dev;
458 ddev->dev_private = priv;
461 switch (get_mdp_ver(pdev)) {
463 ret = mdp5_mdss_init(ddev);
466 ret = dpu_mdss_init(ddev);
477 priv->wq = alloc_ordered_workqueue("msm", 0);
479 INIT_LIST_HEAD(&priv->inactive_list);
480 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
481 kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
482 spin_lock_init(&priv->vblank_ctrl.lock);
484 drm_mode_config_init(ddev);
486 ret = msm_init_vram(ddev);
488 goto err_destroy_mdss;
490 /* Bind all our sub-components: */
491 ret = component_bind_all(dev, ddev);
493 goto err_destroy_mdss;
495 if (!dev->dma_parms) {
496 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
498 if (!dev->dma_parms) {
503 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
505 msm_gem_shrinker_init(ddev);
507 switch (get_mdp_ver(pdev)) {
509 kms = mdp4_kms_init(ddev);
513 kms = mdp5_kms_init(ddev);
516 kms = dpu_kms_init(ddev);
520 kms = ERR_PTR(-ENODEV);
526 * NOTE: once we have GPU support, having no kms should not
527 * be considered fatal.. ideally we would still support gpu
528 * and (for example) use dmabuf/prime to share buffers with
529 * imx drm driver on iMX5
531 dev_err(dev, "failed to load kms\n");
536 /* Enable normalization of plane zpos */
537 ddev->mode_config.normalize_zpos = true;
540 ret = kms->funcs->hw_init(kms);
542 dev_err(dev, "kms hw init failed: %d\n", ret);
547 ddev->mode_config.funcs = &mode_config_funcs;
548 ddev->mode_config.helper_private = &mode_config_helper_funcs;
551 * this priority was found during empiric testing to have appropriate
552 * realtime scheduling to process display updates and interact with
553 * other real time and normal priority task
555 param.sched_priority = 16;
556 for (i = 0; i < priv->num_crtcs; i++) {
558 /* initialize display thread */
559 priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
560 kthread_init_worker(&priv->disp_thread[i].worker);
561 priv->disp_thread[i].dev = ddev;
562 priv->disp_thread[i].thread =
563 kthread_run(kthread_worker_fn,
564 &priv->disp_thread[i].worker,
565 "crtc_commit:%d", priv->disp_thread[i].crtc_id);
566 ret = sched_setscheduler(priv->disp_thread[i].thread,
569 pr_warn("display thread priority update failed: %d\n",
572 if (IS_ERR(priv->disp_thread[i].thread)) {
573 dev_err(dev, "failed to create crtc_commit kthread\n");
574 priv->disp_thread[i].thread = NULL;
577 /* initialize event thread */
578 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
579 kthread_init_worker(&priv->event_thread[i].worker);
580 priv->event_thread[i].dev = ddev;
581 priv->event_thread[i].thread =
582 kthread_run(kthread_worker_fn,
583 &priv->event_thread[i].worker,
584 "crtc_event:%d", priv->event_thread[i].crtc_id);
586 * event thread should also run at same priority as disp_thread
587 * because it is handling frame_done events. A lower priority
588 * event thread and higher priority disp_thread can causes
589 * frame_pending counters beyond 2. This can lead to commit
590 * failure at crtc commit level.
592 ret = sched_setscheduler(priv->event_thread[i].thread,
595 pr_warn("display event thread priority update failed: %d\n",
598 if (IS_ERR(priv->event_thread[i].thread)) {
599 dev_err(dev, "failed to create crtc_event kthread\n");
600 priv->event_thread[i].thread = NULL;
603 if ((!priv->disp_thread[i].thread) ||
604 !priv->event_thread[i].thread) {
605 /* clean up previously created threads if any */
606 for ( ; i >= 0; i--) {
607 if (priv->disp_thread[i].thread) {
609 priv->disp_thread[i].thread);
610 priv->disp_thread[i].thread = NULL;
613 if (priv->event_thread[i].thread) {
615 priv->event_thread[i].thread);
616 priv->event_thread[i].thread = NULL;
623 ret = drm_vblank_init(ddev, priv->num_crtcs);
625 dev_err(dev, "failed to initialize vblank\n");
630 pm_runtime_get_sync(dev);
631 ret = drm_irq_install(ddev, kms->irq);
632 pm_runtime_put_sync(dev);
634 dev_err(dev, "failed to install IRQ handler\n");
639 ret = drm_dev_register(ddev, 0);
643 drm_mode_config_reset(ddev);
645 #ifdef CONFIG_DRM_FBDEV_EMULATION
647 priv->fbdev = msm_fbdev_init(ddev);
650 ret = msm_debugfs_late_init(ddev);
654 drm_kms_helper_poll_init(ddev);
662 if (mdss && mdss->funcs)
663 mdss->funcs->destroy(ddev);
675 static void load_gpu(struct drm_device *dev)
677 static DEFINE_MUTEX(init_lock);
678 struct msm_drm_private *priv = dev->dev_private;
680 mutex_lock(&init_lock);
683 priv->gpu = adreno_load_gpu(dev);
685 mutex_unlock(&init_lock);
688 static int context_init(struct drm_device *dev, struct drm_file *file)
690 struct msm_file_private *ctx;
692 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
696 msm_submitqueue_init(dev, ctx);
698 file->driver_priv = ctx;
703 static int msm_open(struct drm_device *dev, struct drm_file *file)
705 /* For now, load gpu on open.. to avoid the requirement of having
706 * firmware in the initrd.
710 return context_init(dev, file);
713 static void context_close(struct msm_file_private *ctx)
715 msm_submitqueue_close(ctx);
719 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
721 struct msm_drm_private *priv = dev->dev_private;
722 struct msm_file_private *ctx = file->driver_priv;
724 mutex_lock(&dev->struct_mutex);
725 if (ctx == priv->lastctx)
726 priv->lastctx = NULL;
727 mutex_unlock(&dev->struct_mutex);
732 static irqreturn_t msm_irq(int irq, void *arg)
734 struct drm_device *dev = arg;
735 struct msm_drm_private *priv = dev->dev_private;
736 struct msm_kms *kms = priv->kms;
738 return kms->funcs->irq(kms);
741 static void msm_irq_preinstall(struct drm_device *dev)
743 struct msm_drm_private *priv = dev->dev_private;
744 struct msm_kms *kms = priv->kms;
746 kms->funcs->irq_preinstall(kms);
749 static int msm_irq_postinstall(struct drm_device *dev)
751 struct msm_drm_private *priv = dev->dev_private;
752 struct msm_kms *kms = priv->kms;
754 return kms->funcs->irq_postinstall(kms);
757 static void msm_irq_uninstall(struct drm_device *dev)
759 struct msm_drm_private *priv = dev->dev_private;
760 struct msm_kms *kms = priv->kms;
762 kms->funcs->irq_uninstall(kms);
765 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
767 struct msm_drm_private *priv = dev->dev_private;
768 struct msm_kms *kms = priv->kms;
771 DBG("dev=%p, crtc=%u", dev, pipe);
772 return vblank_ctrl_queue_work(priv, pipe, true);
775 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
777 struct msm_drm_private *priv = dev->dev_private;
778 struct msm_kms *kms = priv->kms;
781 DBG("dev=%p, crtc=%u", dev, pipe);
782 vblank_ctrl_queue_work(priv, pipe, false);
789 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
790 struct drm_file *file)
792 struct msm_drm_private *priv = dev->dev_private;
793 struct drm_msm_param *args = data;
796 /* for now, we just have 3d pipe.. eventually this would need to
797 * be more clever to dispatch to appropriate gpu module:
799 if (args->pipe != MSM_PIPE_3D0)
807 return gpu->funcs->get_param(gpu, args->param, &args->value);
810 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
811 struct drm_file *file)
813 struct drm_msm_gem_new *args = data;
815 if (args->flags & ~MSM_BO_FLAGS) {
816 DRM_ERROR("invalid flags: %08x\n", args->flags);
820 return msm_gem_new_handle(dev, file, args->size,
821 args->flags, &args->handle);
824 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
826 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
829 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
830 struct drm_file *file)
832 struct drm_msm_gem_cpu_prep *args = data;
833 struct drm_gem_object *obj;
834 ktime_t timeout = to_ktime(args->timeout);
837 if (args->op & ~MSM_PREP_FLAGS) {
838 DRM_ERROR("invalid op: %08x\n", args->op);
842 obj = drm_gem_object_lookup(file, args->handle);
846 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
848 drm_gem_object_put_unlocked(obj);
853 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
854 struct drm_file *file)
856 struct drm_msm_gem_cpu_fini *args = data;
857 struct drm_gem_object *obj;
860 obj = drm_gem_object_lookup(file, args->handle);
864 ret = msm_gem_cpu_fini(obj);
866 drm_gem_object_put_unlocked(obj);
871 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
872 struct drm_gem_object *obj, uint64_t *iova)
874 struct msm_drm_private *priv = dev->dev_private;
879 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
882 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
883 struct drm_file *file)
885 struct drm_msm_gem_info *args = data;
886 struct drm_gem_object *obj;
889 if (args->flags & ~MSM_INFO_FLAGS)
892 obj = drm_gem_object_lookup(file, args->handle);
896 if (args->flags & MSM_INFO_IOVA) {
899 ret = msm_ioctl_gem_info_iova(dev, obj, &iova);
903 args->offset = msm_gem_mmap_offset(obj);
906 drm_gem_object_put_unlocked(obj);
911 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
912 struct drm_file *file)
914 struct msm_drm_private *priv = dev->dev_private;
915 struct drm_msm_wait_fence *args = data;
916 ktime_t timeout = to_ktime(args->timeout);
917 struct msm_gpu_submitqueue *queue;
918 struct msm_gpu *gpu = priv->gpu;
922 DRM_ERROR("invalid pad: %08x\n", args->pad);
929 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
933 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
936 msm_submitqueue_put(queue);
940 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
941 struct drm_file *file)
943 struct drm_msm_gem_madvise *args = data;
944 struct drm_gem_object *obj;
947 switch (args->madv) {
948 case MSM_MADV_DONTNEED:
949 case MSM_MADV_WILLNEED:
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 obj = drm_gem_object_lookup(file, args->handle);
965 ret = msm_gem_madvise(obj, args->madv);
967 args->retained = ret;
971 drm_gem_object_put(obj);
974 mutex_unlock(&dev->struct_mutex);
979 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
980 struct drm_file *file)
982 struct drm_msm_submitqueue *args = data;
984 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
987 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
988 args->flags, &args->id);
992 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
993 struct drm_file *file)
995 u32 id = *(u32 *) data;
997 return msm_submitqueue_remove(file->driver_priv, id);
1000 static const struct drm_ioctl_desc msm_ioctls[] = {
1001 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
1003 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1005 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
1007 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
1009 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
1010 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
1013 static const struct vm_operations_struct vm_ops = {
1014 .fault = msm_gem_fault,
1015 .open = drm_gem_vm_open,
1016 .close = drm_gem_vm_close,
1019 static const struct file_operations fops = {
1020 .owner = THIS_MODULE,
1022 .release = drm_release,
1023 .unlocked_ioctl = drm_ioctl,
1024 .compat_ioctl = drm_compat_ioctl,
1027 .llseek = no_llseek,
1028 .mmap = msm_gem_mmap,
1031 static struct drm_driver msm_driver = {
1032 .driver_features = DRIVER_HAVE_IRQ |
1039 .postclose = msm_postclose,
1040 .lastclose = drm_fb_helper_lastclose,
1041 .irq_handler = msm_irq,
1042 .irq_preinstall = msm_irq_preinstall,
1043 .irq_postinstall = msm_irq_postinstall,
1044 .irq_uninstall = msm_irq_uninstall,
1045 .enable_vblank = msm_enable_vblank,
1046 .disable_vblank = msm_disable_vblank,
1047 .gem_free_object = msm_gem_free_object,
1048 .gem_vm_ops = &vm_ops,
1049 .dumb_create = msm_gem_dumb_create,
1050 .dumb_map_offset = msm_gem_dumb_map_offset,
1051 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1052 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1053 .gem_prime_export = drm_gem_prime_export,
1054 .gem_prime_import = drm_gem_prime_import,
1055 .gem_prime_res_obj = msm_gem_prime_res_obj,
1056 .gem_prime_pin = msm_gem_prime_pin,
1057 .gem_prime_unpin = msm_gem_prime_unpin,
1058 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1059 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1060 .gem_prime_vmap = msm_gem_prime_vmap,
1061 .gem_prime_vunmap = msm_gem_prime_vunmap,
1062 .gem_prime_mmap = msm_gem_prime_mmap,
1063 #ifdef CONFIG_DEBUG_FS
1064 .debugfs_init = msm_debugfs_init,
1066 .ioctls = msm_ioctls,
1067 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1070 .desc = "MSM Snapdragon DRM",
1072 .major = MSM_VERSION_MAJOR,
1073 .minor = MSM_VERSION_MINOR,
1074 .patchlevel = MSM_VERSION_PATCHLEVEL,
1077 #ifdef CONFIG_PM_SLEEP
1078 static int msm_pm_suspend(struct device *dev)
1080 struct drm_device *ddev = dev_get_drvdata(dev);
1081 struct msm_drm_private *priv = ddev->dev_private;
1082 struct msm_kms *kms = priv->kms;
1084 /* TODO: Use atomic helper suspend/resume */
1085 if (kms && kms->funcs && kms->funcs->pm_suspend)
1086 return kms->funcs->pm_suspend(dev);
1088 drm_kms_helper_poll_disable(ddev);
1090 priv->pm_state = drm_atomic_helper_suspend(ddev);
1091 if (IS_ERR(priv->pm_state)) {
1092 drm_kms_helper_poll_enable(ddev);
1093 return PTR_ERR(priv->pm_state);
1099 static int msm_pm_resume(struct device *dev)
1101 struct drm_device *ddev = dev_get_drvdata(dev);
1102 struct msm_drm_private *priv = ddev->dev_private;
1103 struct msm_kms *kms = priv->kms;
1105 /* TODO: Use atomic helper suspend/resume */
1106 if (kms && kms->funcs && kms->funcs->pm_resume)
1107 return kms->funcs->pm_resume(dev);
1109 drm_atomic_helper_resume(ddev, priv->pm_state);
1110 drm_kms_helper_poll_enable(ddev);
1117 static int msm_runtime_suspend(struct device *dev)
1119 struct drm_device *ddev = dev_get_drvdata(dev);
1120 struct msm_drm_private *priv = ddev->dev_private;
1121 struct msm_mdss *mdss = priv->mdss;
1125 if (mdss && mdss->funcs)
1126 return mdss->funcs->disable(mdss);
1131 static int msm_runtime_resume(struct device *dev)
1133 struct drm_device *ddev = dev_get_drvdata(dev);
1134 struct msm_drm_private *priv = ddev->dev_private;
1135 struct msm_mdss *mdss = priv->mdss;
1139 if (mdss && mdss->funcs)
1140 return mdss->funcs->enable(mdss);
1146 static const struct dev_pm_ops msm_pm_ops = {
1147 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1148 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1152 * Componentized driver support:
1156 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1157 * so probably some room for some helpers
1159 static int compare_of(struct device *dev, void *data)
1161 return dev->of_node == data;
1165 * Identify what components need to be added by parsing what remote-endpoints
1166 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1167 * is no external component that we need to add since LVDS is within MDP4
1170 static int add_components_mdp(struct device *mdp_dev,
1171 struct component_match **matchptr)
1173 struct device_node *np = mdp_dev->of_node;
1174 struct device_node *ep_node;
1175 struct device *master_dev;
1178 * on MDP4 based platforms, the MDP platform device is the component
1179 * master that adds other display interface components to itself.
1181 * on MDP5 based platforms, the MDSS platform device is the component
1182 * master that adds MDP5 and other display interface components to
1185 if (of_device_is_compatible(np, "qcom,mdp4"))
1186 master_dev = mdp_dev;
1188 master_dev = mdp_dev->parent;
1190 for_each_endpoint_of_node(np, ep_node) {
1191 struct device_node *intf;
1192 struct of_endpoint ep;
1195 ret = of_graph_parse_endpoint(ep_node, &ep);
1197 dev_err(mdp_dev, "unable to parse port endpoint\n");
1198 of_node_put(ep_node);
1203 * The LCDC/LVDS port on MDP4 is a speacial case where the
1204 * remote-endpoint isn't a component that we need to add
1206 if (of_device_is_compatible(np, "qcom,mdp4") &&
1211 * It's okay if some of the ports don't have a remote endpoint
1212 * specified. It just means that the port isn't connected to
1213 * any external interface.
1215 intf = of_graph_get_remote_port_parent(ep_node);
1219 drm_of_component_match_add(master_dev, matchptr, compare_of,
1227 static int compare_name_mdp(struct device *dev, void *data)
1229 return (strstr(dev_name(dev), "mdp") != NULL);
1232 static int add_display_components(struct device *dev,
1233 struct component_match **matchptr)
1235 struct device *mdp_dev;
1239 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1240 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1241 * Populate the children devices, find the MDP5/DPU node, and then add
1242 * the interfaces to our components list.
1244 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1245 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1246 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1248 dev_err(dev, "failed to populate children devices\n");
1252 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1254 dev_err(dev, "failed to find MDSS MDP node\n");
1255 of_platform_depopulate(dev);
1259 put_device(mdp_dev);
1261 /* add the MDP component itself */
1262 drm_of_component_match_add(dev, matchptr, compare_of,
1269 ret = add_components_mdp(mdp_dev, matchptr);
1271 of_platform_depopulate(dev);
1277 * We don't know what's the best binding to link the gpu with the drm device.
1278 * Fow now, we just hunt for all the possible gpus that we support, and add them
1281 static const struct of_device_id msm_gpu_match[] = {
1282 { .compatible = "qcom,adreno" },
1283 { .compatible = "qcom,adreno-3xx" },
1284 { .compatible = "qcom,kgsl-3d0" },
1288 static int add_gpu_components(struct device *dev,
1289 struct component_match **matchptr)
1291 struct device_node *np;
1293 np = of_find_matching_node(NULL, msm_gpu_match);
1297 if (of_device_is_available(np))
1298 drm_of_component_match_add(dev, matchptr, compare_of, np);
1305 static int msm_drm_bind(struct device *dev)
1307 return msm_drm_init(dev, &msm_driver);
1310 static void msm_drm_unbind(struct device *dev)
1312 msm_drm_uninit(dev);
1315 static const struct component_master_ops msm_drm_ops = {
1316 .bind = msm_drm_bind,
1317 .unbind = msm_drm_unbind,
1324 static int msm_pdev_probe(struct platform_device *pdev)
1326 struct component_match *match = NULL;
1329 ret = add_display_components(&pdev->dev, &match);
1333 ret = add_gpu_components(&pdev->dev, &match);
1337 /* on all devices that I am aware of, iommu's which can map
1338 * any address the cpu can see are used:
1340 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1344 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1351 of_platform_depopulate(&pdev->dev);
1355 static int msm_pdev_remove(struct platform_device *pdev)
1357 component_master_del(&pdev->dev, &msm_drm_ops);
1358 of_platform_depopulate(&pdev->dev);
1363 static void msm_pdev_shutdown(struct platform_device *pdev)
1365 struct drm_device *drm = platform_get_drvdata(pdev);
1366 struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
1368 if (!priv || !priv->kms)
1371 drm_atomic_helper_shutdown(drm);
1374 static const struct of_device_id dt_match[] = {
1375 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1376 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1377 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1380 MODULE_DEVICE_TABLE(of, dt_match);
1382 static struct platform_driver msm_platform_driver = {
1383 .probe = msm_pdev_probe,
1384 .remove = msm_pdev_remove,
1385 .shutdown = msm_pdev_shutdown,
1388 .of_match_table = dt_match,
1393 static int __init msm_drm_register(void)
1403 msm_hdmi_register();
1405 return platform_driver_register(&msm_platform_driver);
1408 static void __exit msm_drm_unregister(void)
1411 platform_driver_unregister(&msm_platform_driver);
1412 msm_hdmi_unregister();
1413 adreno_unregister();
1414 msm_edp_unregister();
1415 msm_dsi_unregister();
1416 msm_mdp_unregister();
1417 msm_dpu_unregister();
1420 module_init(msm_drm_register);
1421 module_exit(msm_drm_unregister);
1423 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1424 MODULE_DESCRIPTION("MSM DRM Driver");
1425 MODULE_LICENSE("GPL");