gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "intel_guc_ads.h"
  27 #include "intel_guc_submission.h"
  28 #include "i915_drv.h"
  29
  30 static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
  31
  32 static void gen8_guc_raise_irq(struct intel_guc *guc)
  33 {
  34         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  35
  36         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  37 }
  38
  39 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  40 {
  41         GEM_BUG_ON(!guc->send_regs.base);
  42         GEM_BUG_ON(!guc->send_regs.count);
  43         GEM_BUG_ON(i >= guc->send_regs.count);
  44
  45         return _MMIO(guc->send_regs.base + 4 * i);
  46 }
  47
  48 void intel_guc_init_send_regs(struct intel_guc *guc)
  49 {
  50         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  51         enum forcewake_domains fw_domains = 0;
  52         unsigned int i;
  53
  54         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  55         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
  56
  57         for (i = 0; i < guc->send_regs.count; i++) {
  58                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
  59                                         guc_send_reg(guc, i),
  60                                         FW_REG_READ | FW_REG_WRITE);
  61         }
  62         guc->send_regs.fw_domains = fw_domains;
  63 }
  64
  65 void intel_guc_init_early(struct intel_guc *guc)
  66 {
  67         intel_guc_fw_init_early(guc);
  68         intel_guc_ct_init_early(&guc->ct);
  69         intel_guc_log_init_early(&guc->log);
  70
  71         mutex_init(&guc->send_mutex);
  72         spin_lock_init(&guc->irq_lock);
  73         guc->send = intel_guc_send_nop;
  74         guc->handler = intel_guc_to_host_event_handler_nop;
  75         guc->notify = gen8_guc_raise_irq;
  76 }
  77
  78 static int guc_init_wq(struct intel_guc *guc)
  79 {
  80         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  81
  82         /*
  83          * GuC log buffer flush work item has to do register access to
  84          * send the ack to GuC and this work item, if not synced before
  85          * suspend, can potentially get executed after the GFX device is
  86          * suspended.
  87          * By marking the WQ as freezable, we don't have to bother about
  88          * flushing of this work item from the suspend hooks, the pending
  89          * work item if any will be either executed before the suspend
  90          * or scheduled later on resume. This way the handling of work
  91          * item can be kept same between system suspend & rpm suspend.
  92          */
  93         guc->log.relay.flush_wq =
  94                 alloc_ordered_workqueue("i915-guc_log",
  95                                         WQ_HIGHPRI | WQ_FREEZABLE);
  96         if (!guc->log.relay.flush_wq) {
  97                 DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
  98                 return -ENOMEM;
  99         }
 100
 101         /*
 102          * Even though both sending GuC action, and adding a new workitem to
 103          * GuC workqueue are serialized (each with its own locking), since
 104          * we're using mutliple engines, it's possible that we're going to
 105          * issue a preempt request with two (or more - each for different
 106          * engine) workitems in GuC queue. In this situation, GuC may submit
 107          * all of them, which will make us very confused.
 108          * Our preemption contexts may even already be complete - before we
 109          * even had the chance to sent the preempt action to GuC!. Rather
 110          * than introducing yet another lock, we can just use ordered workqueue
 111          * to make sure we're always sending a single preemption request with a
 112          * single workitem.
 113          */
 114         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 115             USES_GUC_SUBMISSION(dev_priv)) {
 116                 guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
 117                                                           WQ_HIGHPRI);
 118                 if (!guc->preempt_wq) {
 119                         destroy_workqueue(guc->log.relay.flush_wq);
 120                         DRM_ERROR("Couldn't allocate workqueue for GuC "
 121                                   "preemption\n");
 122                         return -ENOMEM;
 123                 }
 124         }
 125
 126         return 0;
 127 }
 128
 129 static void guc_fini_wq(struct intel_guc *guc)
 130 {
 131         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 132
 133         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 134             USES_GUC_SUBMISSION(dev_priv))
 135                 destroy_workqueue(guc->preempt_wq);
 136
 137         destroy_workqueue(guc->log.relay.flush_wq);
 138 }
 139
 140 int intel_guc_init_misc(struct intel_guc *guc)
 141 {
 142         struct drm_i915_private *i915 = guc_to_i915(guc);
 143         int ret;
 144
 145         guc_init_ggtt_pin_bias(guc);
 146
 147         ret = guc_init_wq(guc);
 148         if (ret)
 149                 return ret;
 150
 151         intel_uc_fw_fetch(i915, &guc->fw);
 152
 153         return 0;
 154 }
 155
 156 void intel_guc_fini_misc(struct intel_guc *guc)
 157 {
 158         intel_uc_fw_fini(&guc->fw);
 159         guc_fini_wq(guc);
 160 }
 161
 162 static int guc_shared_data_create(struct intel_guc *guc)
 163 {
 164         struct i915_vma *vma;
 165         void *vaddr;
 166
 167         vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
 168         if (IS_ERR(vma))
 169                 return PTR_ERR(vma);
 170
 171         vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
 172         if (IS_ERR(vaddr)) {
 173                 i915_vma_unpin_and_release(&vma);
 174                 return PTR_ERR(vaddr);
 175         }
 176
 177         guc->shared_data = vma;
 178         guc->shared_data_vaddr = vaddr;
 179
 180         return 0;
 181 }
 182
 183 static void guc_shared_data_destroy(struct intel_guc *guc)
 184 {
 185         i915_gem_object_unpin_map(guc->shared_data->obj);
 186         i915_vma_unpin_and_release(&guc->shared_data);
 187 }
 188
 189 int intel_guc_init(struct intel_guc *guc)
 190 {
 191         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 192         int ret;
 193
 194         ret = guc_shared_data_create(guc);
 195         if (ret)
 196                 goto err_fetch;
 197         GEM_BUG_ON(!guc->shared_data);
 198
 199         ret = intel_guc_log_create(&guc->log);
 200         if (ret)
 201                 goto err_shared;
 202
 203         ret = intel_guc_ads_create(guc);
 204         if (ret)
 205                 goto err_log;
 206         GEM_BUG_ON(!guc->ads_vma);
 207
 208         /* We need to notify the guc whenever we change the GGTT */
 209         i915_ggtt_enable_guc(dev_priv);
 210
 211         return 0;
 212
 213 err_log:
 214         intel_guc_log_destroy(&guc->log);
 215 err_shared:
 216         guc_shared_data_destroy(guc);
 217 err_fetch:
 218         intel_uc_fw_fini(&guc->fw);
 219         return ret;
 220 }
 221
 222 void intel_guc_fini(struct intel_guc *guc)
 223 {
 224         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 225
 226         i915_ggtt_disable_guc(dev_priv);
 227         intel_guc_ads_destroy(guc);
 228         intel_guc_log_destroy(&guc->log);
 229         guc_shared_data_destroy(guc);
 230         intel_uc_fw_fini(&guc->fw);
 231 }
 232
 233 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
 234 {
 235         u32 level = intel_guc_log_get_level(&guc->log);
 236         u32 flags;
 237         u32 ads;
 238
 239         ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
 240         flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
 241
 242         if (!GUC_LOG_LEVEL_IS_ENABLED(level))
 243                 flags |= GUC_LOG_DEFAULT_DISABLED;
 244
 245         if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 246                 flags |= GUC_LOG_DISABLED;
 247         else
 248                 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
 249                          GUC_LOG_VERBOSITY_SHIFT;
 250
 251         return flags;
 252 }
 253
 254 static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 255 {
 256         u32 flags = 0;
 257
 258         flags |=  GUC_CTL_VCS2_ENABLED;
 259
 260         if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
 261                 flags |= GUC_CTL_KERNEL_SUBMISSIONS;
 262         else
 263                 flags |= GUC_CTL_DISABLE_SCHEDULER;
 264
 265         return flags;
 266 }
 267
 268 static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
 269 {
 270         u32 flags = 0;
 271
 272         if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
 273                 u32 ctxnum, base;
 274
 275                 base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
 276                 ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
 277
 278                 base >>= PAGE_SHIFT;
 279                 flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
 280                         (ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
 281         }
 282         return flags;
 283 }
 284
 285 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 286 {
 287         u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
 288         u32 flags;
 289
 290         #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
 291         #define UNIT SZ_1M
 292         #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE
 293         #else
 294         #define UNIT SZ_4K
 295         #define FLAG 0
 296         #endif
 297
 298         BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
 299         BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
 300         BUILD_BUG_ON(!DPC_BUFFER_SIZE);
 301         BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
 302         BUILD_BUG_ON(!ISR_BUFFER_SIZE);
 303         BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
 304
 305         BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
 306                         (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
 307         BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
 308                         (GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
 309         BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
 310                         (GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
 311
 312         flags = GUC_LOG_VALID |
 313                 GUC_LOG_NOTIFY_ON_HALF_FULL |
 314                 FLAG |
 315                 ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
 316                 ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
 317                 ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
 318                 (offset << GUC_LOG_BUF_ADDR_SHIFT);
 319
 320         #undef UNIT
 321         #undef FLAG
 322
 323         return flags;
 324 }
 325
 326 /*
 327  * Initialise the GuC parameter block before starting the firmware
 328  * transfer. These parameters are read by the firmware on startup
 329  * and cannot be changed thereafter.
 330  */
 331 void intel_guc_init_params(struct intel_guc *guc)
 332 {
 333         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 334         u32 params[GUC_CTL_MAX_DWORDS];
 335         int i;
 336
 337         memset(params, 0, sizeof(params));
 338
 339         /*
 340          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 341          * second. This ARAR is calculated by:
 342          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 343          */
 344         params[GUC_CTL_ARAT_HIGH] = 0;
 345         params[GUC_CTL_ARAT_LOW] = 100000000;
 346
 347         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 348
 349         params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
 350         params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
 351         params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
 352         params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
 353
 354         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 355                 DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
 356
 357         /*
 358          * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
 359          * they are power context saved so it's ok to release forcewake
 360          * when we are done here and take it again at xfer time.
 361          */
 362         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 363
 364         I915_WRITE(SOFT_SCRATCH(0), 0);
 365
 366         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 367                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 368
 369         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
 370 }
 371
 372 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
 373                        u32 *response_buf, u32 response_buf_size)
 374 {
 375         WARN(1, "Unexpected send: action=%#x\n", *action);
 376         return -ENODEV;
 377 }
 378
 379 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
 380 {
 381         WARN(1, "Unexpected event: no suitable handler\n");
 382 }
 383
 384 /*
 385  * This function implements the MMIO based host to GuC interface.
 386  */
 387 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 388                         u32 *response_buf, u32 response_buf_size)
 389 {
 390         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 391         u32 status;
 392         int i;
 393         int ret;
 394
 395         GEM_BUG_ON(!len);
 396         GEM_BUG_ON(len > guc->send_regs.count);
 397
 398         /* We expect only action code */
 399         GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
 400
 401         /* If CT is available, we expect to use MMIO only during init/fini */
 402         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
 403                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 404                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 405
 406         mutex_lock(&guc->send_mutex);
 407         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
 408
 409         for (i = 0; i < len; i++)
 410                 I915_WRITE(guc_send_reg(guc, i), action[i]);
 411
 412         POSTING_READ(guc_send_reg(guc, i - 1));
 413
 414         intel_guc_notify(guc);
 415
 416         /*
 417          * No GuC command should ever take longer than 10ms.
 418          * Fast commands should still complete in 10us.
 419          */
 420         ret = __intel_wait_for_register_fw(dev_priv,
 421                                            guc_send_reg(guc, 0),
 422                                            INTEL_GUC_MSG_TYPE_MASK,
 423                                            INTEL_GUC_MSG_TYPE_RESPONSE <<
 424                                            INTEL_GUC_MSG_TYPE_SHIFT,
 425                                            10, 10, &status);
 426         /* If GuC explicitly returned an error, convert it to -EIO */
 427         if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
 428                 ret = -EIO;
 429
 430         if (ret) {
 431                 DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
 432                           action[0], ret, status);
 433                 goto out;
 434         }
 435
 436         if (response_buf) {
 437                 int count = min(response_buf_size, guc->send_regs.count - 1);
 438
 439                 for (i = 0; i < count; i++)
 440                         response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
 441         }
 442
 443         /* Use data from the GuC response as our return value */
 444         ret = INTEL_GUC_MSG_TO_DATA(status);
 445
 446 out:
 447         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 448         mutex_unlock(&guc->send_mutex);
 449
 450         return ret;
 451 }
 452
 453 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
 454 {
 455         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 456         u32 msg, val;
 457
 458         /*
 459          * Sample the log buffer flush related bits & clear them out now
 460          * itself from the message identity register to minimize the
 461          * probability of losing a flush interrupt, when there are back
 462          * to back flush interrupts.
 463          * There can be a new flush interrupt, for different log buffer
 464          * type (like for ISR), whilst Host is handling one (for DPC).
 465          * Since same bit is used in message register for ISR & DPC, it
 466          * could happen that GuC sets the bit for 2nd interrupt but Host
 467          * clears out the bit on handling the 1st interrupt.
 468          */
 469         disable_rpm_wakeref_asserts(dev_priv);
 470         spin_lock(&guc->irq_lock);
 471         val = I915_READ(SOFT_SCRATCH(15));
 472         msg = val & guc->msg_enabled_mask;
 473         I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
 474         spin_unlock(&guc->irq_lock);
 475         enable_rpm_wakeref_asserts(dev_priv);
 476
 477         intel_guc_to_host_process_recv_msg(guc, msg);
 478 }
 479
 480 void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)
 481 {
 482         /* Make sure to handle only enabled messages */
 483         msg &= guc->msg_enabled_mask;
 484
 485         if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
 486                    INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
 487                 intel_guc_log_handle_flush_event(&guc->log);
 488 }
 489
 490 int intel_guc_sample_forcewake(struct intel_guc *guc)
 491 {
 492         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 493         u32 action[2];
 494
 495         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 496         /* WaRsDisableCoarsePowerGating:skl,cnl */
 497         if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 498                 action[1] = 0;
 499         else
 500                 /* bit 0 and 1 are for Render and Media domain separately */
 501                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 502
 503         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 504 }
 505
 506 /**
 507  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 508  * @guc: intel_guc structure
 509  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 510  *
 511  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 512  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 513  * intel_huc_auth().
 514  *
 515  * Return:      non-zero code on error
 516  */
 517 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 518 {
 519         u32 action[] = {
 520                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 521                 rsa_offset
 522         };
 523
 524         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 525 }
 526
 527 /**
 528  * intel_guc_suspend() - notify GuC entering suspend state
 529  * @guc:        the guc
 530  */
 531 int intel_guc_suspend(struct intel_guc *guc)
 532 {
 533         u32 data[] = {
 534                 INTEL_GUC_ACTION_ENTER_S_STATE,
 535                 GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
 536                 intel_guc_ggtt_offset(guc, guc->shared_data)
 537         };
 538
 539         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 540 }
 541
 542 /**
 543  * intel_guc_reset_engine() - ask GuC to reset an engine
 544  * @guc:        intel_guc structure
 545  * @engine:     engine to be reset
 546  */
 547 int intel_guc_reset_engine(struct intel_guc *guc,
 548                            struct intel_engine_cs *engine)
 549 {
 550         u32 data[7];
 551
 552         GEM_BUG_ON(!guc->execbuf_client);
 553
 554         data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
 555         data[1] = engine->guc_id;
 556         data[2] = 0;
 557         data[3] = 0;
 558         data[4] = 0;
 559         data[5] = guc->execbuf_client->stage_id;
 560         data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 561
 562         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 563 }
 564
 565 /**
 566  * intel_guc_resume() - notify GuC resuming from suspend state
 567  * @guc:        the guc
 568  */
 569 int intel_guc_resume(struct intel_guc *guc)
 570 {
 571         u32 data[] = {
 572                 INTEL_GUC_ACTION_EXIT_S_STATE,
 573                 GUC_POWER_D0,
 574                 intel_guc_ggtt_offset(guc, guc->shared_data)
 575         };
 576
 577         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 578 }
 579
 580 /**
 581  * DOC: GuC Address Space
 582  *
 583  * The layout of GuC address space is shown below:
 584  *
 585  * ::
 586  *
 587  *     +==============> +====================+ <== GUC_GGTT_TOP
 588  *     ^                |                    |
 589  *     |                |                    |
 590  *     |                |        DRAM        |
 591  *     |                |       Memory       |
 592  *     |                |                    |
 593  *    GuC               |                    |
 594  *  Address  +========> +====================+ <== WOPCM Top
 595  *   Space   ^          |   HW contexts RSVD |
 596  *     |     |          |        WOPCM       |
 597  *     |     |     +==> +--------------------+ <== GuC WOPCM Top
 598  *     |    GuC    ^    |                    |
 599  *     |    GGTT   |    |                    |
 600  *     |    Pin   GuC   |        GuC         |
 601  *     |    Bias WOPCM  |       WOPCM        |
 602  *     |     |    Size  |                    |
 603  *     |     |     |    |                    |
 604  *     v     v     v    |                    |
 605  *     +=====+=====+==> +====================+ <== GuC WOPCM Base
 606  *                      |   Non-GuC WOPCM    |
 607  *                      |   (HuC/Reserved)   |
 608  *                      +====================+ <== WOPCM Base
 609  *
 610  * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
 611  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
 612  * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
 613  * actual GuC WOPCM size.
 614  */
 615
 616 /**
 617  * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
 618  * @guc: intel_guc structure.
 619  *
 620  * This function will calculate and initialize the ggtt_pin_bias value based on
 621  * overall WOPCM size and GuC WOPCM size.
 622  */
 623 static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
 624 {
 625         struct drm_i915_private *i915 = guc_to_i915(guc);
 626
 627         GEM_BUG_ON(!i915->wopcm.size);
 628         GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
 629
 630         guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
 631 }
 632
 633 /**
 634  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 635  * @guc:        the guc
 636  * @size:       size of area to allocate (both virtual space and memory)
 637  *
 638  * This is a wrapper to create an object for use with the GuC. In order to
 639  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 640  * both some backing storage and a range inside the Global GTT. We must pin
 641  * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
 642  * range is reserved inside GuC.
 643  *
 644  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 645  */
 646 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 647 {
 648         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 649         struct drm_i915_gem_object *obj;
 650         struct i915_vma *vma;
 651         int ret;
 652
 653         obj = i915_gem_object_create(dev_priv, size);
 654         if (IS_ERR(obj))
 655                 return ERR_CAST(obj);
 656
 657         vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
 658         if (IS_ERR(vma))
 659                 goto err;
 660
 661         ret = i915_vma_pin(vma, 0, PAGE_SIZE,
 662                            PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
 663         if (ret) {
 664                 vma = ERR_PTR(ret);
 665                 goto err;
 666         }
 667
 668         return vma;
 669
 670 err:
 671         i915_gem_object_put(obj);
 672         return vma;
 673 }