2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define I915_CSR_GLK "/*(DEBLOBBED)*/"
39 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
41 #define I915_CSR_CNL "/*(DEBLOBBED)*/"
43 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
45 #define I915_CSR_KBL "/*(DEBLOBBED)*/"
47 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
49 #define I915_CSR_SKL "/*(DEBLOBBED)*/"
51 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
53 #define I915_CSR_BXT "/*(DEBLOBBED)*/"
55 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
58 #define CSR_MAX_FW_SIZE 0x2FFF
59 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
61 struct intel_css_header {
65 /* Includes the DMC specific header in dwords */
68 /* always value would be 0x10000 */
75 uint32_t module_vendor;
77 /* in YYYYMMDD format */
80 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
87 uint32_t modulus_size;
90 uint32_t exponent_size;
93 uint32_t reserved1[12];
99 uint32_t reserved2[8];
102 uint32_t kernel_header_info;
105 struct intel_fw_info {
108 /* Stepping (A, B, C, ..., *). * is a wildcard */
111 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
118 struct intel_package_header {
119 /* DMC container header length in dwords */
120 unsigned char header_len;
122 /* always value would be 0x01 */
123 unsigned char header_ver;
125 unsigned char reserved[10];
127 /* Number of valid entries in the FWInfo array below */
128 uint32_t num_entries;
130 struct intel_fw_info fw_info[20];
133 struct intel_dmc_header {
134 /* always value would be 0x40403E3E */
137 /* DMC binary header length */
138 unsigned char header_len;
141 unsigned char header_ver;
149 /* Firmware program size (excluding header) in dwords */
152 /* Major Minor version */
155 /* Number of valid MMIO cycles present. */
159 uint32_t mmioaddr[8];
162 uint32_t mmiodata[8];
165 unsigned char dfile[32];
167 uint32_t reserved1[2];
170 struct stepping_info {
175 static const struct stepping_info skl_stepping_info[] = {
176 {'A', '0'}, {'B', '0'}, {'C', '0'},
177 {'D', '0'}, {'E', '0'}, {'F', '0'},
178 {'G', '0'}, {'H', '0'}, {'I', '0'},
179 {'J', '0'}, {'K', '0'}
182 static const struct stepping_info bxt_stepping_info[] = {
183 {'A', '0'}, {'A', '1'}, {'A', '2'},
184 {'B', '0'}, {'B', '1'}, {'B', '2'}
187 static const struct stepping_info no_stepping_info = { '*', '*' };
189 static const struct stepping_info *
190 intel_get_stepping_info(struct drm_i915_private *dev_priv)
192 const struct stepping_info *si;
195 if (IS_SKYLAKE(dev_priv)) {
196 size = ARRAY_SIZE(skl_stepping_info);
197 si = skl_stepping_info;
198 } else if (IS_BROXTON(dev_priv)) {
199 size = ARRAY_SIZE(bxt_stepping_info);
200 si = bxt_stepping_info;
206 if (INTEL_REVID(dev_priv) < size)
207 return si + INTEL_REVID(dev_priv);
209 return &no_stepping_info;
212 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
216 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
218 if (IS_GEN9_LP(dev_priv))
219 mask |= DC_STATE_DEBUG_MASK_CORES;
221 /* The below bit doesn't need to be cleared ever afterwards */
222 val = I915_READ(DC_STATE_DEBUG);
223 if ((val & mask) != mask) {
225 I915_WRITE(DC_STATE_DEBUG, val);
226 POSTING_READ(DC_STATE_DEBUG);
231 * intel_csr_load_program() - write the firmware from memory to register.
232 * @dev_priv: i915 drm device.
234 * CSR firmware is read from a .bin file and kept in internal memory one time.
235 * Everytime display comes back from low power state this function is called to
236 * copy the firmware from internal memory to registers.
238 void intel_csr_load_program(struct drm_i915_private *dev_priv)
240 u32 *payload = dev_priv->csr.dmc_payload;
243 if (!HAS_CSR(dev_priv)) {
244 DRM_ERROR("No CSR support available for this platform\n");
248 if (!dev_priv->csr.dmc_payload) {
249 DRM_ERROR("Tried to program CSR with empty payload\n");
253 fw_size = dev_priv->csr.dmc_fw_size;
254 assert_rpm_wakelock_held(dev_priv);
258 for (i = 0; i < fw_size; i++)
259 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
263 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
264 I915_WRITE(dev_priv->csr.mmioaddr[i],
265 dev_priv->csr.mmiodata[i]);
268 dev_priv->csr.dc_state = 0;
270 gen9_set_dc_state_debugmask(dev_priv);
273 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
274 const struct firmware *fw)
276 struct intel_css_header *css_header;
277 struct intel_package_header *package_header;
278 struct intel_dmc_header *dmc_header;
279 struct intel_csr *csr = &dev_priv->csr;
280 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
281 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
283 uint32_t *dmc_payload;
284 uint32_t required_version;
290 fsize = sizeof(struct intel_css_header) +
291 sizeof(struct intel_package_header) +
292 sizeof(struct intel_dmc_header);
293 if (fsize > fw->size)
294 goto error_truncated;
296 /* Extract CSS Header information*/
297 css_header = (struct intel_css_header *)fw->data;
298 if (sizeof(struct intel_css_header) !=
299 (css_header->header_len * 4)) {
300 DRM_ERROR("DMC firmware has wrong CSS header length "
302 (css_header->header_len * 4));
306 csr->version = css_header->version;
308 if (csr->fw_path == i915_modparams.dmc_firmware_path) {
309 /* Bypass version check for firmware override. */
310 required_version = csr->version;
311 } else if (IS_CANNONLAKE(dev_priv)) {
312 required_version = CNL_CSR_VERSION_REQUIRED;
313 } else if (IS_GEMINILAKE(dev_priv)) {
314 required_version = GLK_CSR_VERSION_REQUIRED;
315 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
316 required_version = KBL_CSR_VERSION_REQUIRED;
317 } else if (IS_SKYLAKE(dev_priv)) {
318 required_version = SKL_CSR_VERSION_REQUIRED;
319 } else if (IS_BROXTON(dev_priv)) {
320 required_version = BXT_CSR_VERSION_REQUIRED;
322 MISSING_CASE(INTEL_REVID(dev_priv));
323 required_version = 0;
326 if (csr->version != required_version) {
327 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
328 " please use v%u.%u\n",
329 CSR_VERSION_MAJOR(csr->version),
330 CSR_VERSION_MINOR(csr->version),
331 CSR_VERSION_MAJOR(required_version),
332 CSR_VERSION_MINOR(required_version));
336 readcount += sizeof(struct intel_css_header);
338 /* Extract Package Header information*/
339 package_header = (struct intel_package_header *)
340 &fw->data[readcount];
341 if (sizeof(struct intel_package_header) !=
342 (package_header->header_len * 4)) {
343 DRM_ERROR("DMC firmware has wrong package header length "
345 (package_header->header_len * 4));
348 readcount += sizeof(struct intel_package_header);
350 /* Search for dmc_offset to find firware binary. */
351 for (i = 0; i < package_header->num_entries; i++) {
352 if (package_header->fw_info[i].substepping == '*' &&
353 si->stepping == package_header->fw_info[i].stepping) {
354 dmc_offset = package_header->fw_info[i].offset;
356 } else if (si->stepping == package_header->fw_info[i].stepping &&
357 si->substepping == package_header->fw_info[i].substepping) {
358 dmc_offset = package_header->fw_info[i].offset;
360 } else if (package_header->fw_info[i].stepping == '*' &&
361 package_header->fw_info[i].substepping == '*')
362 dmc_offset = package_header->fw_info[i].offset;
364 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
365 DRM_ERROR("DMC firmware not supported for %c stepping\n",
369 readcount += dmc_offset;
371 if (fsize > fw->size)
372 goto error_truncated;
374 /* Extract dmc_header information. */
375 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
376 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
377 DRM_ERROR("DMC firmware has wrong dmc header length "
379 (dmc_header->header_len));
382 readcount += sizeof(struct intel_dmc_header);
384 /* Cache the dmc header info. */
385 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
386 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
387 dmc_header->mmio_count);
390 csr->mmio_count = dmc_header->mmio_count;
391 for (i = 0; i < dmc_header->mmio_count; i++) {
392 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
393 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
394 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
395 dmc_header->mmioaddr[i]);
398 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
399 csr->mmiodata[i] = dmc_header->mmiodata[i];
402 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
403 nbytes = dmc_header->fw_size * 4;
405 if (fsize > fw->size)
406 goto error_truncated;
408 if (nbytes > CSR_MAX_FW_SIZE) {
409 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
412 csr->dmc_fw_size = dmc_header->fw_size;
414 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
416 DRM_ERROR("Memory allocation failed for dmc payload\n");
420 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
423 DRM_ERROR("Truncated DMC firmware, rejecting.\n");
427 static void csr_load_work_fn(struct work_struct *work)
429 struct drm_i915_private *dev_priv;
430 struct intel_csr *csr;
431 const struct firmware *fw = NULL;
433 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
434 csr = &dev_priv->csr;
436 reject_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
438 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
440 if (dev_priv->csr.dmc_payload) {
441 intel_csr_load_program(dev_priv);
443 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
445 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
446 dev_priv->csr.fw_path,
447 CSR_VERSION_MAJOR(csr->version),
448 CSR_VERSION_MINOR(csr->version));
450 dev_notice(dev_priv->drm.dev,
451 "Failed to load DMC firmware %s."
452 " Disabling runtime power management.\n",
454 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
455 INTEL_UC_FIRMWARE_URL);
458 release_firmware(fw);
462 * intel_csr_ucode_init() - initialize the firmware loading.
463 * @dev_priv: i915 drm device.
465 * This function is called at the time of loading the display driver to read
466 * firmware from a .bin file and copied into a internal memory.
468 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
470 struct intel_csr *csr = &dev_priv->csr;
472 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
474 if (!HAS_CSR(dev_priv))
477 if (i915_modparams.dmc_firmware_path)
478 csr->fw_path = i915_modparams.dmc_firmware_path;
479 else if (IS_CANNONLAKE(dev_priv))
480 csr->fw_path = I915_CSR_CNL;
481 else if (IS_GEMINILAKE(dev_priv))
482 csr->fw_path = I915_CSR_GLK;
483 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
484 csr->fw_path = I915_CSR_KBL;
485 else if (IS_SKYLAKE(dev_priv))
486 csr->fw_path = I915_CSR_SKL;
487 else if (IS_BROXTON(dev_priv))
488 csr->fw_path = I915_CSR_BXT;
490 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
494 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
497 * Obtain a runtime pm reference, until CSR is loaded,
498 * to avoid entering runtime-suspend.
500 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
502 schedule_work(&dev_priv->csr.work);
506 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
507 * @dev_priv: i915 drm device
509 * Prepare the DMC firmware before entering system suspend. This includes
510 * flushing pending work items and releasing any resources acquired during
513 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
515 if (!HAS_CSR(dev_priv))
518 flush_work(&dev_priv->csr.work);
520 /* Drop the reference held in case DMC isn't loaded. */
521 if (!dev_priv->csr.dmc_payload)
522 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
526 * intel_csr_ucode_resume() - init CSR firmware during system resume
527 * @dev_priv: i915 drm device
529 * Reinitialize the DMC firmware during system resume, reacquiring any
530 * resources released in intel_csr_ucode_suspend().
532 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
534 if (!HAS_CSR(dev_priv))
538 * Reacquire the reference to keep RPM disabled in case DMC isn't
541 if (!dev_priv->csr.dmc_payload)
542 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
546 * intel_csr_ucode_fini() - unload the CSR firmware.
547 * @dev_priv: i915 drm device.
549 * Firmmware unloading includes freeing the internal memory and reset the
550 * firmware loading status.
552 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
554 if (!HAS_CSR(dev_priv))
557 intel_csr_ucode_suspend(dev_priv);
559 kfree(dev_priv->csr.dmc_payload);