1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <asm/hypervisor.h>
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <linux/backlight.h>
42 #include <linux/hash.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/mm_types.h>
46 #include <linux/perf_event.h>
47 #include <linux/pm_qos.h>
48 #include <linux/reservation.h>
49 #include <linux/shmem_fs.h>
52 #include <drm/intel-gtt.h>
53 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
54 #include <drm/drm_gem.h>
55 #include <drm/drm_auth.h>
56 #include <drm/drm_cache.h>
58 #include "i915_params.h"
60 #include "i915_utils.h"
62 #include "intel_bios.h"
63 #include "intel_device_info.h"
64 #include "intel_display.h"
65 #include "intel_dpll_mgr.h"
66 #include "intel_lrc.h"
67 #include "intel_opregion.h"
68 #include "intel_ringbuffer.h"
69 #include "intel_uncore.h"
70 #include "intel_wopcm.h"
74 #include "i915_gem_context.h"
75 #include "i915_gem_fence_reg.h"
76 #include "i915_gem_object.h"
77 #include "i915_gem_gtt.h"
78 #include "i915_gpu_error.h"
79 #include "i915_request.h"
80 #include "i915_scheduler.h"
81 #include "i915_timeline.h"
84 #include "intel_gvt.h"
86 /* General customization:
89 #define DRIVER_NAME "i915"
90 #define DRIVER_DESC "Intel Graphics"
91 #define DRIVER_DATE "20180719"
92 #define DRIVER_TIMESTAMP 1532015279
94 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
95 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
96 * which may not necessarily be a user visible problem. This will either
97 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
98 * enable distros and users to tailor their preferred amount of i915 abrt
101 #define I915_STATE_WARN(condition, format...) ({ \
102 int __ret_warn_on = !!(condition); \
103 if (unlikely(__ret_warn_on)) \
104 if (!WARN(i915_modparams.verbose_state_checks, format)) \
106 unlikely(__ret_warn_on); \
109 #define I915_STATE_WARN_ON(x) \
110 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
112 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
114 bool __i915_inject_load_failure(const char *func, int line);
115 #define i915_inject_load_failure() \
116 __i915_inject_load_failure(__func__, __LINE__)
118 bool i915_error_injected(void);
122 #define i915_inject_load_failure() false
123 #define i915_error_injected() false
127 #define i915_load_error(i915, fmt, ...) \
128 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
133 } uint_fixed_16_16_t;
135 #define FP_16_16_MAX ({ \
136 uint_fixed_16_16_t fp; \
141 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
148 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
150 uint_fixed_16_16_t fp;
152 WARN_ON(val > U16_MAX);
158 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
160 return DIV_ROUND_UP(fp.val, 1 << 16);
163 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
168 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
169 uint_fixed_16_16_t min2)
171 uint_fixed_16_16_t min;
173 min.val = min(min1.val, min2.val);
177 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
178 uint_fixed_16_16_t max2)
180 uint_fixed_16_16_t max;
182 max.val = max(max1.val, max2.val);
186 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
188 uint_fixed_16_16_t fp;
189 WARN_ON(val > U32_MAX);
190 fp.val = (uint32_t) val;
194 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
195 uint_fixed_16_16_t d)
197 return DIV_ROUND_UP(val.val, d.val);
200 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
201 uint_fixed_16_16_t mul)
203 uint64_t intermediate_val;
205 intermediate_val = (uint64_t) val * mul.val;
206 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
207 WARN_ON(intermediate_val > U32_MAX);
208 return (uint32_t) intermediate_val;
211 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
212 uint_fixed_16_16_t mul)
214 uint64_t intermediate_val;
216 intermediate_val = (uint64_t) val.val * mul.val;
217 intermediate_val = intermediate_val >> 16;
218 return clamp_u64_to_fixed16(intermediate_val);
221 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
225 interm_val = (uint64_t)val << 16;
226 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
227 return clamp_u64_to_fixed16(interm_val);
230 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
231 uint_fixed_16_16_t d)
235 interm_val = (uint64_t)val << 16;
236 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
237 WARN_ON(interm_val > U32_MAX);
238 return (uint32_t) interm_val;
241 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
242 uint_fixed_16_16_t mul)
244 uint64_t intermediate_val;
246 intermediate_val = (uint64_t) val * mul.val;
247 return clamp_u64_to_fixed16(intermediate_val);
250 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
251 uint_fixed_16_16_t add2)
255 interm_sum = (uint64_t) add1.val + add2.val;
256 return clamp_u64_to_fixed16(interm_sum);
259 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
263 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
265 interm_sum = (uint64_t) add1.val + interm_add2.val;
266 return clamp_u64_to_fixed16(interm_sum);
271 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
284 #define for_each_hpd_pin(__pin) \
285 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
287 #define HPD_STORM_DEFAULT_THRESHOLD 5
289 struct i915_hotplug {
290 struct work_struct hotplug_work;
293 unsigned long last_jiffies;
298 HPD_MARK_DISABLED = 2
300 } stats[HPD_NUM_PINS];
302 struct delayed_work reenable_work;
306 struct work_struct dig_port_work;
308 struct work_struct poll_init_work;
311 unsigned int hpd_storm_threshold;
314 * if we get a HPD irq from DP and a HPD irq from non-DP
315 * the non-DP HPD could block the workqueue on a mode config
316 * mutex getting, that userspace may have taken. However
317 * userspace is waiting on the DP workqueue to run which is
318 * blocked behind the non-DP one.
320 struct workqueue_struct *dp_wq;
323 #define I915_GEM_GPU_DOMAINS \
324 (I915_GEM_DOMAIN_RENDER | \
325 I915_GEM_DOMAIN_SAMPLER | \
326 I915_GEM_DOMAIN_COMMAND | \
327 I915_GEM_DOMAIN_INSTRUCTION | \
328 I915_GEM_DOMAIN_VERTEX)
330 struct drm_i915_private;
331 struct i915_mm_struct;
332 struct i915_mmu_object;
334 struct drm_i915_file_private {
335 struct drm_i915_private *dev_priv;
336 struct drm_file *file;
340 struct list_head request_list;
341 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
342 * chosen to prevent the CPU getting more than a frame ahead of the GPU
343 * (when using lax throttling for the frontbuffer). We also use it to
344 * offer free GPU waitboosts for severely congested workloads.
346 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
348 struct idr context_idr;
350 struct intel_rps_client {
354 unsigned int bsd_engine;
357 * Every context ban increments per client ban score. Also
358 * hangs in short succession increments ban score. If ban threshold
359 * is reached, client is considered banned and submitting more work
360 * will fail. This is a stop gap measure to limit the badly behaving
361 * clients access to gpu. Note that unbannable contexts never increment
362 * the client ban score.
364 #define I915_CLIENT_SCORE_HANG_FAST 1
365 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
366 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
367 #define I915_CLIENT_SCORE_BANNED 9
368 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
370 unsigned long hang_timestamp;
373 /* Interface history:
376 * 1.2: Add Power Management
377 * 1.3: Add vblank support
378 * 1.4: Fix cmdbuffer path, add heap destroy
379 * 1.5: Add vblank pipe configuration
380 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
381 * - Support vertical blank on secondary display pipe
383 #define DRIVER_MAJOR 1
384 #define DRIVER_MINOR 6
385 #define DRIVER_PATCHLEVEL 0
387 struct intel_overlay;
388 struct intel_overlay_error_state;
390 struct sdvo_device_mapping {
399 struct intel_connector;
400 struct intel_encoder;
401 struct intel_atomic_state;
402 struct intel_crtc_state;
403 struct intel_initial_plane_config;
407 struct intel_cdclk_state;
409 struct drm_i915_display_funcs {
410 void (*get_cdclk)(struct drm_i915_private *dev_priv,
411 struct intel_cdclk_state *cdclk_state);
412 void (*set_cdclk)(struct drm_i915_private *dev_priv,
413 const struct intel_cdclk_state *cdclk_state);
414 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
415 enum i9xx_plane_id i9xx_plane);
416 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
417 int (*compute_intermediate_wm)(struct drm_device *dev,
418 struct intel_crtc *intel_crtc,
419 struct intel_crtc_state *newstate);
420 void (*initial_watermarks)(struct intel_atomic_state *state,
421 struct intel_crtc_state *cstate);
422 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
423 struct intel_crtc_state *cstate);
424 void (*optimize_watermarks)(struct intel_atomic_state *state,
425 struct intel_crtc_state *cstate);
426 int (*compute_global_watermarks)(struct drm_atomic_state *state);
427 void (*update_wm)(struct intel_crtc *crtc);
428 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
429 /* Returns the active state of the crtc, and if the crtc is active,
430 * fills out the pipe-config with the hw state. */
431 bool (*get_pipe_config)(struct intel_crtc *,
432 struct intel_crtc_state *);
433 void (*get_initial_plane_config)(struct intel_crtc *,
434 struct intel_initial_plane_config *);
435 int (*crtc_compute_clock)(struct intel_crtc *crtc,
436 struct intel_crtc_state *crtc_state);
437 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
438 struct drm_atomic_state *old_state);
439 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
440 struct drm_atomic_state *old_state);
441 void (*update_crtcs)(struct drm_atomic_state *state);
442 void (*audio_codec_enable)(struct intel_encoder *encoder,
443 const struct intel_crtc_state *crtc_state,
444 const struct drm_connector_state *conn_state);
445 void (*audio_codec_disable)(struct intel_encoder *encoder,
446 const struct intel_crtc_state *old_crtc_state,
447 const struct drm_connector_state *old_conn_state);
448 void (*fdi_link_train)(struct intel_crtc *crtc,
449 const struct intel_crtc_state *crtc_state);
450 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
451 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
452 /* clock updates for mode set */
454 /* render clock increase/decrease */
455 /* display clock increase/decrease */
456 /* pll clock increase/decrease */
458 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
459 void (*load_luts)(struct drm_crtc_state *crtc_state);
462 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
463 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
464 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
467 struct work_struct work;
469 uint32_t *dmc_payload;
470 uint32_t dmc_fw_size;
473 i915_reg_t mmioaddr[8];
474 uint32_t mmiodata[8];
476 uint32_t allowed_dc_mask;
479 enum i915_cache_level {
481 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
482 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
483 caches, eg sampler/render caches, and the
484 large Last-Level-Cache. LLC is coherent with
485 the CPU, but L3 is only visible to the GPU. */
486 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
489 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
500 /* This is always the inner lock when overlapping with struct_mutex and
501 * it's the outer lock when overlapping with stolen_lock. */
504 unsigned int possible_framebuffer_bits;
505 unsigned int busy_bits;
506 unsigned int visible_pipes_mask;
507 struct intel_crtc *crtc;
509 struct drm_mm_node compressed_fb;
510 struct drm_mm_node *compressed_llb;
518 bool underrun_detected;
519 struct work_struct underrun_work;
522 * Due to the atomic rules we can't access some structures without the
523 * appropriate locking, so we cache information here in order to avoid
526 struct intel_fbc_state_cache {
527 struct i915_vma *vma;
531 unsigned int mode_flags;
532 uint32_t hsw_bdw_pixel_rate;
536 unsigned int rotation;
541 * Display surface base address adjustement for
542 * pageflips. Note that on gen4+ this only adjusts up
543 * to a tile, offsets within a tile are handled in
544 * the hw itself (with the TILEOFF register).
553 const struct drm_format_info *format;
559 * This structure contains everything that's relevant to program the
560 * hardware registers. When we want to figure out if we need to disable
561 * and re-enable FBC for a new configuration we just check if there's
562 * something different in the struct. The genx_fbc_activate functions
563 * are supposed to read from it in order to program the registers.
565 struct intel_fbc_reg_params {
566 struct i915_vma *vma;
571 enum i9xx_plane_id i9xx_plane;
572 unsigned int fence_y_offset;
576 const struct drm_format_info *format;
581 unsigned int gen9_wa_cfb_stride;
584 const char *no_fbc_reason;
588 * HIGH_RR is the highest eDP panel refresh rate read from EDID
589 * LOW_RR is the lowest eDP panel refresh rate found from EDID
590 * parsing for same resolution.
592 enum drrs_refresh_rate_type {
595 DRRS_MAX_RR, /* RR count */
598 enum drrs_support_type {
599 DRRS_NOT_SUPPORTED = 0,
600 STATIC_DRRS_SUPPORT = 1,
601 SEAMLESS_DRRS_SUPPORT = 2
607 struct delayed_work work;
609 unsigned busy_frontbuffer_bits;
610 enum drrs_refresh_rate_type refresh_rate_type;
611 enum drrs_support_type type;
617 struct intel_dp *enabled;
619 struct work_struct work;
620 unsigned busy_frontbuffer_bits;
621 bool sink_psr2_support;
623 bool colorimetry_support;
626 u8 sink_sync_latency;
628 ktime_t last_entry_attempt;
633 PCH_NONE = 0, /* No PCH present */
634 PCH_IBX, /* Ibexpeak PCH */
635 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
636 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
637 PCH_SPT, /* Sunrisepoint PCH */
638 PCH_KBP, /* Kaby Lake PCH */
639 PCH_CNP, /* Cannon Lake PCH */
640 PCH_ICP, /* Ice Lake PCH */
641 PCH_NOP, /* PCH without south display */
644 enum intel_sbi_destination {
649 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
650 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
651 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
652 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
653 #define QUIRK_INCREASE_T12_DELAY (1<<6)
654 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
657 struct intel_fbc_work;
660 struct i2c_adapter adapter;
661 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
665 struct i2c_algo_bit_data bit_algo;
666 struct drm_i915_private *dev_priv;
669 struct i915_suspend_saved_registers {
672 u32 saveCACHE_MODE_0;
673 u32 saveMI_ARB_STATE;
677 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
678 u32 savePCH_PORT_HOTPLUG;
682 struct vlv_s0ix_state {
689 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
690 u32 media_max_req_count;
691 u32 gfx_max_req_count;
723 /* Display 1 CZ domain */
728 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
730 /* GT SA CZ domain */
737 /* Display 2 CZ domain */
744 struct intel_rps_ei {
752 * work, interrupts_enabled and pm_iir are protected by
755 struct work_struct work;
756 bool interrupts_enabled;
759 /* PM interrupt bits that should never be masked */
762 /* Frequencies are stored in potentially platform dependent multiples.
763 * In other words, *_freq needs to be multiplied by X to be interesting.
764 * Soft limits are those which are used for the dynamic reclocking done
765 * by the driver (raise frequencies under heavy loads, and lower for
766 * lighter loads). Hard limits are those imposed by the hardware.
768 * A distinction is made for overclocking, which is never enabled by
769 * default, and is considered to be above the hard limit if it's
772 u8 cur_freq; /* Current frequency (cached, may not == HW) */
773 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
774 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
775 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
776 u8 min_freq; /* AKA RPn. Minimum frequency */
777 u8 boost_freq; /* Frequency to request when wait boosting */
778 u8 idle_freq; /* Frequency to request when we are idle */
779 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
780 u8 rp1_freq; /* "less than" RP0 power/freqency */
781 u8 rp0_freq; /* Non-overclocked max frequency. */
782 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
789 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
790 unsigned int interactive;
792 u8 up_threshold; /* Current %busy required to uplock */
793 u8 down_threshold; /* Current %busy required to downclock */
797 atomic_t num_waiters;
800 /* manual wa residency calculations */
801 struct intel_rps_ei ei;
807 u64 prev_hw_residency[4];
808 u64 cur_residency[4];
811 struct intel_llc_pstate {
815 struct intel_gen6_power_mgmt {
816 struct intel_rps rps;
817 struct intel_rc6 rc6;
818 struct intel_llc_pstate llc_pstate;
821 /* defined intel_pm.c */
822 extern spinlock_t mchdev_lock;
824 struct intel_ilk_power_mgmt {
832 unsigned long last_time1;
833 unsigned long chipset_power;
836 unsigned long gfx_power;
843 struct drm_i915_private;
844 struct i915_power_well;
846 struct i915_power_well_ops {
848 * Synchronize the well's hw state to match the current sw state, for
849 * example enable/disable it based on the current refcount. Called
850 * during driver init and resume time, possibly after first calling
851 * the enable/disable handlers.
853 void (*sync_hw)(struct drm_i915_private *dev_priv,
854 struct i915_power_well *power_well);
856 * Enable the well and resources that depend on it (for example
857 * interrupts located on the well). Called after the 0->1 refcount
860 void (*enable)(struct drm_i915_private *dev_priv,
861 struct i915_power_well *power_well);
863 * Disable the well and resources that depend on it. Called after
864 * the 1->0 refcount transition.
866 void (*disable)(struct drm_i915_private *dev_priv,
867 struct i915_power_well *power_well);
868 /* Returns the hw enabled state. */
869 bool (*is_enabled)(struct drm_i915_private *dev_priv,
870 struct i915_power_well *power_well);
873 /* Power well structure for haswell */
874 struct i915_power_well {
877 /* power well enable/disable usage count */
879 /* cached hw enabled state */
882 /* unique identifier for this power well */
883 enum i915_power_well_id id;
885 * Arbitraty data associated with this power well. Platform and power
893 /* Mask of pipes whose IRQ logic is backed by the pw */
895 /* The pw is backing the VGA functionality */
900 const struct i915_power_well_ops *ops;
903 struct i915_power_domains {
905 * Power wells needed for initialization at driver init and suspend
906 * time are on. They are kept on until after the first modeset.
910 int power_well_count;
913 int domain_use_count[POWER_DOMAIN_NUM];
914 struct i915_power_well *power_wells;
917 #define MAX_L3_SLICES 2
918 struct intel_l3_parity {
919 u32 *remap_info[MAX_L3_SLICES];
920 struct work_struct error_work;
925 /** Memory allocator for GTT stolen memory */
926 struct drm_mm stolen;
927 /** Protects the usage of the GTT stolen memory allocator. This is
928 * always the inner lock when overlapping with struct_mutex. */
929 struct mutex stolen_lock;
931 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
934 /** List of all objects in gtt_space. Used to restore gtt
935 * mappings on resume */
936 struct list_head bound_list;
938 * List of objects which are not bound to the GTT (thus
939 * are idle and not used by the GPU). These objects may or may
940 * not actually have any pages attached.
942 struct list_head unbound_list;
944 /** List of all objects in gtt_space, currently mmaped by userspace.
945 * All objects within this list must also be on bound_list.
947 struct list_head userfault_list;
950 * List of objects which are pending destruction.
952 struct llist_head free_list;
953 struct work_struct free_work;
954 spinlock_t free_lock;
956 * Count of objects pending destructions. Used to skip needlessly
957 * waiting on an RCU barrier if no objects are waiting to be freed.
962 * Small stash of WC pages
964 struct pagestash wc_stash;
967 * tmpfs instance used for shmem backed objects
969 struct vfsmount *gemfs;
971 /** PPGTT used for aliasing the PPGTT with the GTT */
972 struct i915_hw_ppgtt *aliasing_ppgtt;
974 struct notifier_block oom_notifier;
975 struct notifier_block vmap_notifier;
976 struct shrinker shrinker;
978 /** LRU list of objects with fence regs on them. */
979 struct list_head fence_list;
982 * Workqueue to fault in userptr pages, flushed by the execbuf
983 * when required but otherwise left to userspace to try again
986 struct workqueue_struct *userptr_wq;
988 u64 unordered_timeline;
990 /* the indicator for dispatch video commands on two BSD rings */
991 atomic_t bsd_engine_dispatch_index;
993 /** Bit 6 swizzling required for X tiling */
994 uint32_t bit_6_swizzle_x;
995 /** Bit 6 swizzling required for Y tiling */
996 uint32_t bit_6_swizzle_y;
998 /* accounting, useful for userland debugging */
999 spinlock_t object_stat_lock;
1004 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1006 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1007 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1009 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1010 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1012 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
1014 #define DP_AUX_A 0x40
1015 #define DP_AUX_B 0x10
1016 #define DP_AUX_C 0x20
1017 #define DP_AUX_D 0x30
1018 #define DP_AUX_E 0x50
1019 #define DP_AUX_F 0x60
1021 #define DDC_PIN_B 0x05
1022 #define DDC_PIN_C 0x04
1023 #define DDC_PIN_D 0x06
1025 struct ddi_vbt_port_info {
1029 * This is an index in the HDMI/DVI DDI buffer translation table.
1030 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1031 * populate this field.
1033 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1034 uint8_t hdmi_level_shift;
1036 uint8_t supports_dvi:1;
1037 uint8_t supports_hdmi:1;
1038 uint8_t supports_dp:1;
1039 uint8_t supports_edp:1;
1041 uint8_t alternate_aux_channel;
1042 uint8_t alternate_ddc_pin;
1044 uint8_t dp_boost_level;
1045 uint8_t hdmi_boost_level;
1046 int dp_max_link_rate; /* 0 for not limited by VBT */
1049 enum psr_lines_to_wait {
1050 PSR_0_LINES_TO_WAIT = 0,
1052 PSR_4_LINES_TO_WAIT,
1056 struct intel_vbt_data {
1057 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1058 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1061 unsigned int int_tv_support:1;
1062 unsigned int lvds_dither:1;
1063 unsigned int int_crt_support:1;
1064 unsigned int lvds_use_ssc:1;
1065 unsigned int int_lvds_support:1;
1066 unsigned int display_clock_mode:1;
1067 unsigned int fdi_rx_polarity_inverted:1;
1068 unsigned int panel_type:4;
1070 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1072 enum drrs_support_type drrs_type;
1082 struct edp_power_seq pps;
1088 bool require_aux_wakeup;
1090 enum psr_lines_to_wait lines_to_wait;
1091 int tp1_wakeup_time_us;
1092 int tp2_tp3_wakeup_time_us;
1098 bool active_low_pwm;
1099 u8 min_brightness; /* min_brightness/255 of max */
1100 u8 controller; /* brightness controller number */
1101 enum intel_backlight_type type;
1107 struct mipi_config *config;
1108 struct mipi_pps_data *pps;
1114 const u8 *sequence[MIPI_SEQ_MAX];
1115 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1121 struct child_device_config *child_dev;
1123 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1124 struct sdvo_device_mapping sdvo_mappings[2];
1127 enum intel_ddb_partitioning {
1129 INTEL_DDB_PART_5_6, /* IVB+ */
1132 struct intel_wm_level {
1140 struct ilk_wm_values {
1141 uint32_t wm_pipe[3];
1143 uint32_t wm_lp_spr[3];
1144 uint32_t wm_linetime[3];
1146 enum intel_ddb_partitioning partitioning;
1149 struct g4x_pipe_wm {
1150 uint16_t plane[I915_MAX_PLANES];
1160 struct vlv_wm_ddl_values {
1161 uint8_t plane[I915_MAX_PLANES];
1164 struct vlv_wm_values {
1165 struct g4x_pipe_wm pipe[3];
1166 struct g4x_sr_wm sr;
1167 struct vlv_wm_ddl_values ddl[3];
1172 struct g4x_wm_values {
1173 struct g4x_pipe_wm pipe[2];
1174 struct g4x_sr_wm sr;
1175 struct g4x_sr_wm hpll;
1181 struct skl_ddb_entry {
1182 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1185 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1187 return entry->end - entry->start;
1190 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1191 const struct skl_ddb_entry *e2)
1193 if (e1->start == e2->start && e1->end == e2->end)
1199 struct skl_ddb_allocation {
1201 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1202 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1203 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1206 struct skl_ddb_values {
1207 unsigned dirty_pipes;
1208 struct skl_ddb_allocation ddb;
1211 struct skl_wm_level {
1213 uint16_t plane_res_b;
1214 uint8_t plane_res_l;
1217 /* Stores plane specific WM parameters */
1218 struct skl_wm_params {
1219 bool x_tiled, y_tiled;
1224 uint32_t plane_pixel_rate;
1225 uint32_t y_min_scanlines;
1226 uint32_t plane_bytes_per_line;
1227 uint_fixed_16_16_t plane_blocks_per_line;
1228 uint_fixed_16_16_t y_tile_minimum;
1229 uint32_t linetime_us;
1230 uint32_t dbuf_block_size;
1234 * This struct helps tracking the state needed for runtime PM, which puts the
1235 * device in PCI D3 state. Notice that when this happens, nothing on the
1236 * graphics device works, even register access, so we don't get interrupts nor
1239 * Every piece of our code that needs to actually touch the hardware needs to
1240 * either call intel_runtime_pm_get or call intel_display_power_get with the
1241 * appropriate power domain.
1243 * Our driver uses the autosuspend delay feature, which means we'll only really
1244 * suspend if we stay with zero refcount for a certain amount of time. The
1245 * default value is currently very conservative (see intel_runtime_pm_enable), but
1246 * it can be changed with the standard runtime PM files from sysfs.
1248 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1249 * goes back to false exactly before we reenable the IRQs. We use this variable
1250 * to check if someone is trying to enable/disable IRQs while they're supposed
1251 * to be disabled. This shouldn't happen and we'll print some error messages in
1254 * For more, read the Documentation/power/runtime_pm.txt.
1256 struct i915_runtime_pm {
1257 atomic_t wakeref_count;
1262 enum intel_pipe_crc_source {
1263 INTEL_PIPE_CRC_SOURCE_NONE,
1264 INTEL_PIPE_CRC_SOURCE_PLANE1,
1265 INTEL_PIPE_CRC_SOURCE_PLANE2,
1266 INTEL_PIPE_CRC_SOURCE_PF,
1267 INTEL_PIPE_CRC_SOURCE_PIPE,
1268 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1269 INTEL_PIPE_CRC_SOURCE_TV,
1270 INTEL_PIPE_CRC_SOURCE_DP_B,
1271 INTEL_PIPE_CRC_SOURCE_DP_C,
1272 INTEL_PIPE_CRC_SOURCE_DP_D,
1273 INTEL_PIPE_CRC_SOURCE_AUTO,
1274 INTEL_PIPE_CRC_SOURCE_MAX,
1277 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1278 struct intel_pipe_crc {
1281 enum intel_pipe_crc_source source;
1284 struct i915_frontbuffer_tracking {
1288 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1295 struct i915_wa_reg {
1298 /* bitmask representing WA bits */
1302 #define I915_MAX_WA_REGS 16
1304 struct i915_workarounds {
1305 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1309 struct i915_virtual_gpu {
1314 /* used in computing the new watermarks state */
1315 struct intel_wm_config {
1316 unsigned int num_pipes_active;
1317 bool sprites_enabled;
1318 bool sprites_scaled;
1321 struct i915_oa_format {
1326 struct i915_oa_reg {
1331 struct i915_oa_config {
1332 char uuid[UUID_STRING_LEN + 1];
1335 const struct i915_oa_reg *mux_regs;
1337 const struct i915_oa_reg *b_counter_regs;
1338 u32 b_counter_regs_len;
1339 const struct i915_oa_reg *flex_regs;
1342 struct attribute_group sysfs_metric;
1343 struct attribute *attrs[2];
1344 struct device_attribute sysfs_metric_id;
1349 struct i915_perf_stream;
1352 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1354 struct i915_perf_stream_ops {
1356 * @enable: Enables the collection of HW samples, either in response to
1357 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1358 * without `I915_PERF_FLAG_DISABLED`.
1360 void (*enable)(struct i915_perf_stream *stream);
1363 * @disable: Disables the collection of HW samples, either in response
1364 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1367 void (*disable)(struct i915_perf_stream *stream);
1370 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1371 * once there is something ready to read() for the stream
1373 void (*poll_wait)(struct i915_perf_stream *stream,
1378 * @wait_unlocked: For handling a blocking read, wait until there is
1379 * something to ready to read() for the stream. E.g. wait on the same
1380 * wait queue that would be passed to poll_wait().
1382 int (*wait_unlocked)(struct i915_perf_stream *stream);
1385 * @read: Copy buffered metrics as records to userspace
1386 * **buf**: the userspace, destination buffer
1387 * **count**: the number of bytes to copy, requested by userspace
1388 * **offset**: zero at the start of the read, updated as the read
1389 * proceeds, it represents how many bytes have been copied so far and
1390 * the buffer offset for copying the next record.
1392 * Copy as many buffered i915 perf samples and records for this stream
1393 * to userspace as will fit in the given buffer.
1395 * Only write complete records; returning -%ENOSPC if there isn't room
1396 * for a complete record.
1398 * Return any error condition that results in a short read such as
1399 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1400 * returning to userspace.
1402 int (*read)(struct i915_perf_stream *stream,
1408 * @destroy: Cleanup any stream specific resources.
1410 * The stream will always be disabled before this is called.
1412 void (*destroy)(struct i915_perf_stream *stream);
1416 * struct i915_perf_stream - state for a single open stream FD
1418 struct i915_perf_stream {
1420 * @dev_priv: i915 drm device
1422 struct drm_i915_private *dev_priv;
1425 * @link: Links the stream into ``&drm_i915_private->streams``
1427 struct list_head link;
1430 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1431 * properties given when opening a stream, representing the contents
1432 * of a single sample as read() by userspace.
1437 * @sample_size: Considering the configured contents of a sample
1438 * combined with the required header size, this is the total size
1439 * of a single sample record.
1444 * @ctx: %NULL if measuring system-wide across all contexts or a
1445 * specific context that is being monitored.
1447 struct i915_gem_context *ctx;
1450 * @enabled: Whether the stream is currently enabled, considering
1451 * whether the stream was opened in a disabled state and based
1452 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1457 * @ops: The callbacks providing the implementation of this specific
1458 * type of configured stream.
1460 const struct i915_perf_stream_ops *ops;
1463 * @oa_config: The OA configuration used by the stream.
1465 struct i915_oa_config *oa_config;
1469 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1471 struct i915_oa_ops {
1473 * @is_valid_b_counter_reg: Validates register's address for
1474 * programming boolean counters for a particular platform.
1476 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1480 * @is_valid_mux_reg: Validates register's address for programming mux
1481 * for a particular platform.
1483 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1486 * @is_valid_flex_reg: Validates register's address for programming
1487 * flex EU filtering for a particular platform.
1489 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1492 * @init_oa_buffer: Resets the head and tail pointers of the
1493 * circular buffer for periodic OA reports.
1495 * Called when first opening a stream for OA metrics, but also may be
1496 * called in response to an OA buffer overflow or other error
1499 * Note it may be necessary to clear the full OA buffer here as part of
1500 * maintaining the invariable that new reports must be written to
1501 * zeroed memory for us to be able to reliable detect if an expected
1502 * report has not yet landed in memory. (At least on Haswell the OA
1503 * buffer tail pointer is not synchronized with reports being visible
1506 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1509 * @enable_metric_set: Selects and applies any MUX configuration to set
1510 * up the Boolean and Custom (B/C) counters that are part of the
1511 * counter reports being sampled. May apply system constraints such as
1512 * disabling EU clock gating as required.
1514 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1515 const struct i915_oa_config *oa_config);
1518 * @disable_metric_set: Remove system constraints associated with using
1521 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1524 * @oa_enable: Enable periodic sampling
1526 void (*oa_enable)(struct drm_i915_private *dev_priv);
1529 * @oa_disable: Disable periodic sampling
1531 void (*oa_disable)(struct drm_i915_private *dev_priv);
1534 * @read: Copy data from the circular OA buffer into a given userspace
1537 int (*read)(struct i915_perf_stream *stream,
1543 * @oa_hw_tail_read: read the OA tail pointer register
1545 * In particular this enables us to share all the fiddly code for
1546 * handling the OA unit tail pointer race that affects multiple
1549 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1552 struct intel_cdclk_state {
1553 unsigned int cdclk, vco, ref, bypass;
1557 struct drm_i915_private {
1558 struct drm_device drm;
1560 struct kmem_cache *objects;
1561 struct kmem_cache *vmas;
1562 struct kmem_cache *luts;
1563 struct kmem_cache *requests;
1564 struct kmem_cache *dependencies;
1565 struct kmem_cache *priorities;
1567 const struct intel_device_info info;
1568 struct intel_driver_caps caps;
1571 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1572 * end of stolen which we can optionally use to create GEM objects
1573 * backed by stolen memory. Note that stolen_usable_size tells us
1574 * exactly how much of this we are actually allowed to use, given that
1575 * some portion of it is in fact reserved for use by hardware functions.
1577 struct resource dsm;
1579 * Reseved portion of Data Stolen Memory
1581 struct resource dsm_reserved;
1584 * Stolen memory is segmented in hardware with different portions
1585 * offlimits to certain functions.
1587 * The drm_mm is initialised to the total accessible range, as found
1588 * from the PCI config. On Broadwell+, this is further restricted to
1589 * avoid the first page! The upper end of stolen memory is reserved for
1590 * hardware functions and similarly removed from the accessible range.
1592 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1596 struct intel_uncore uncore;
1598 struct i915_virtual_gpu vgpu;
1600 struct intel_gvt *gvt;
1602 struct intel_wopcm wopcm;
1604 struct intel_huc huc;
1605 struct intel_guc guc;
1607 struct intel_csr csr;
1609 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1611 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1612 * controller on different i2c buses. */
1613 struct mutex gmbus_mutex;
1616 * Base address of the gmbus and gpio block.
1618 uint32_t gpio_mmio_base;
1620 /* MMIO base address for MIPI regs */
1621 uint32_t mipi_mmio_base;
1623 uint32_t psr_mmio_base;
1625 uint32_t pps_mmio_base;
1627 wait_queue_head_t gmbus_wait_queue;
1629 struct pci_dev *bridge_dev;
1630 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1631 /* Context used internally to idle the GPU and setup initial state */
1632 struct i915_gem_context *kernel_context;
1633 /* Context only to be used for injecting preemption commands */
1634 struct i915_gem_context *preempt_context;
1635 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1636 [MAX_ENGINE_INSTANCE + 1];
1638 struct drm_dma_handle *status_page_dmah;
1639 struct resource mch_res;
1641 /* protects the irq masks */
1642 spinlock_t irq_lock;
1644 bool display_irqs_enabled;
1646 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1647 struct pm_qos_request pm_qos;
1649 /* Sideband mailbox protection */
1650 struct mutex sb_lock;
1652 /** Cached value of IMR to avoid reads in updating the bitfield */
1655 u32 de_irq_mask[I915_MAX_PIPES];
1662 u32 pipestat_irq_mask[I915_MAX_PIPES];
1664 struct i915_hotplug hotplug;
1665 struct intel_fbc fbc;
1666 struct i915_drrs drrs;
1667 struct intel_opregion opregion;
1668 struct intel_vbt_data vbt;
1670 bool preserve_bios_swizzle;
1673 struct intel_overlay *overlay;
1675 /* backlight registers and fields in struct intel_panel */
1676 struct mutex backlight_lock;
1679 bool no_aux_handshake;
1681 /* protects panel power sequencer state */
1682 struct mutex pps_mutex;
1684 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1685 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1687 unsigned int fsb_freq, mem_freq, is_ddr3;
1688 unsigned int skl_preferred_vco_freq;
1689 unsigned int max_cdclk_freq;
1691 unsigned int max_dotclk_freq;
1692 unsigned int rawclk_freq;
1693 unsigned int hpll_freq;
1694 unsigned int fdi_pll_freq;
1695 unsigned int czclk_freq;
1699 * The current logical cdclk state.
1700 * See intel_atomic_state.cdclk.logical
1702 * For reading holding any crtc lock is sufficient,
1703 * for writing must hold all of them.
1705 struct intel_cdclk_state logical;
1707 * The current actual cdclk state.
1708 * See intel_atomic_state.cdclk.actual
1710 struct intel_cdclk_state actual;
1711 /* The current hardware cdclk state */
1712 struct intel_cdclk_state hw;
1716 * wq - Driver workqueue for GEM.
1718 * NOTE: Work items scheduled here are not allowed to grab any modeset
1719 * locks, for otherwise the flushing done in the pageflip code will
1720 * result in deadlocks.
1722 struct workqueue_struct *wq;
1724 /* ordered wq for modesets */
1725 struct workqueue_struct *modeset_wq;
1727 /* Display functions */
1728 struct drm_i915_display_funcs display;
1730 /* PCH chipset type */
1731 enum intel_pch pch_type;
1732 unsigned short pch_id;
1734 unsigned long quirks;
1736 struct drm_atomic_state *modeset_restore_state;
1737 struct drm_modeset_acquire_ctx reset_ctx;
1739 struct i915_ggtt ggtt; /* VM representing the global address space */
1741 struct i915_gem_mm mm;
1742 DECLARE_HASHTABLE(mm_structs, 7);
1743 struct mutex mm_lock;
1745 struct intel_ppat ppat;
1747 /* Kernel Modesetting */
1749 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1750 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1752 #ifdef CONFIG_DEBUG_FS
1753 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1756 /* dpll and cdclk state is protected by connection_mutex */
1757 int num_shared_dpll;
1758 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1759 const struct intel_dpll_mgr *dpll_mgr;
1762 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1763 * Must be global rather than per dpll, because on some platforms
1764 * plls share registers.
1766 struct mutex dpll_lock;
1768 unsigned int active_crtcs;
1769 /* minimum acceptable cdclk for each pipe */
1770 int min_cdclk[I915_MAX_PIPES];
1771 /* minimum acceptable voltage level for each pipe */
1772 u8 min_voltage_level[I915_MAX_PIPES];
1774 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1776 struct i915_workarounds workarounds;
1778 struct i915_frontbuffer_tracking fb_tracking;
1780 struct intel_atomic_helper {
1781 struct llist_head free_list;
1782 struct work_struct free_work;
1787 bool mchbar_need_disable;
1789 struct intel_l3_parity l3_parity;
1791 /* Cannot be determined by PCIID. You must always read a register. */
1795 * Protects RPS/RC6 register access and PCU communication.
1796 * Must be taken after struct_mutex if nested. Note that
1797 * this lock may be held for long periods of time when
1798 * talking to hw - so only take it when talking to hw!
1800 struct mutex pcu_lock;
1802 /* gen6+ GT PM state */
1803 struct intel_gen6_power_mgmt gt_pm;
1805 /* ilk-only ips/rps state. Everything in here is protected by the global
1806 * mchdev_lock in intel_pm.c */
1807 struct intel_ilk_power_mgmt ips;
1809 struct i915_power_domains power_domains;
1811 struct i915_psr psr;
1813 struct i915_gpu_error gpu_error;
1815 struct drm_i915_gem_object *vlv_pctx;
1817 /* list of fbdev register on this device */
1818 struct intel_fbdev *fbdev;
1819 struct work_struct fbdev_suspend_work;
1821 struct drm_property *broadcast_rgb_property;
1822 struct drm_property *force_audio_property;
1824 /* hda/i915 audio component */
1825 struct i915_audio_component *audio_component;
1826 bool audio_component_registered;
1828 * av_mutex - mutex for audio/video sync
1831 struct mutex av_mutex;
1834 struct list_head list;
1835 struct llist_head free_list;
1836 struct work_struct free_work;
1838 /* The hw wants to have a stable context identifier for the
1839 * lifetime of the context (for OA, PASID, faults, etc).
1840 * This is limited in execlists to 21 bits.
1843 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1844 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1845 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1850 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1851 u32 chv_phy_control;
1853 * Shadows for CHV DPLL_MD regs to keep the state
1854 * checker somewhat working in the presence hardware
1855 * crappiness (can't read out DPLL_MD for pipes B & C).
1857 u32 chv_dpll_md[I915_MAX_PIPES];
1861 bool power_domains_suspended;
1862 struct i915_suspend_saved_registers regfile;
1863 struct vlv_s0ix_state vlv_s0ix_state;
1866 I915_SAGV_UNKNOWN = 0,
1869 I915_SAGV_NOT_CONTROLLED
1874 * Raw watermark latency values:
1875 * in 0.1us units for WM0,
1876 * in 0.5us units for WM1+.
1879 uint16_t pri_latency[5];
1881 uint16_t spr_latency[5];
1883 uint16_t cur_latency[5];
1885 * Raw watermark memory latency values
1886 * for SKL for all 8 levels
1889 uint16_t skl_latency[8];
1891 /* current hardware state */
1893 struct ilk_wm_values hw;
1894 struct skl_ddb_values skl_hw;
1895 struct vlv_wm_values vlv;
1896 struct g4x_wm_values g4x;
1902 * Should be held around atomic WM register writing; also
1903 * protects * intel_crtc->wm.active and
1904 * cstate->wm.need_postvbl_update.
1906 struct mutex wm_mutex;
1909 * Set during HW readout of watermarks/DDB. Some platforms
1910 * need to know when we're still using BIOS-provided values
1911 * (which we don't fully trust).
1913 bool distrust_bios_wm;
1916 struct i915_runtime_pm runtime_pm;
1921 struct kobject *metrics_kobj;
1922 struct ctl_table_header *sysctl_header;
1925 * Lock associated with adding/modifying/removing OA configs
1926 * in dev_priv->perf.metrics_idr.
1928 struct mutex metrics_lock;
1931 * List of dynamic configurations, you need to hold
1932 * dev_priv->perf.metrics_lock to access it.
1934 struct idr metrics_idr;
1937 * Lock associated with anything below within this structure
1938 * except exclusive_stream.
1941 struct list_head streams;
1945 * The stream currently using the OA unit. If accessed
1946 * outside a syscall associated to its file
1947 * descriptor, you need to hold
1948 * dev_priv->drm.struct_mutex.
1950 struct i915_perf_stream *exclusive_stream;
1952 struct intel_context *pinned_ctx;
1953 u32 specific_ctx_id;
1954 u32 specific_ctx_id_mask;
1956 struct hrtimer poll_check_timer;
1957 wait_queue_head_t poll_wq;
1961 * For rate limiting any notifications of spurious
1962 * invalid OA reports
1964 struct ratelimit_state spurious_report_rs;
1967 int period_exponent;
1969 struct i915_oa_config test_config;
1972 struct i915_vma *vma;
1979 * Locks reads and writes to all head/tail state
1981 * Consider: the head and tail pointer state
1982 * needs to be read consistently from a hrtimer
1983 * callback (atomic context) and read() fop
1984 * (user context) with tail pointer updates
1985 * happening in atomic context and head updates
1986 * in user context and the (unlikely)
1987 * possibility of read() errors needing to
1988 * reset all head/tail state.
1990 * Note: Contention or performance aren't
1991 * currently a significant concern here
1992 * considering the relatively low frequency of
1993 * hrtimer callbacks (5ms period) and that
1994 * reads typically only happen in response to a
1995 * hrtimer event and likely complete before the
1998 * Note: This lock is not held *while* reading
1999 * and copying data to userspace so the value
2000 * of head observed in htrimer callbacks won't
2001 * represent any partial consumption of data.
2003 spinlock_t ptr_lock;
2006 * One 'aging' tail pointer and one 'aged'
2007 * tail pointer ready to used for reading.
2009 * Initial values of 0xffffffff are invalid
2010 * and imply that an update is required
2011 * (and should be ignored by an attempted
2019 * Index for the aged tail ready to read()
2022 unsigned int aged_tail_idx;
2025 * A monotonic timestamp for when the current
2026 * aging tail pointer was read; used to
2027 * determine when it is old enough to trust.
2029 u64 aging_timestamp;
2032 * Although we can always read back the head
2033 * pointer register, we prefer to avoid
2034 * trusting the HW state, just to avoid any
2035 * risk that some hardware condition could
2036 * somehow bump the head pointer unpredictably
2037 * and cause us to forward the wrong OA buffer
2038 * data to userspace.
2043 u32 gen7_latched_oastatus1;
2044 u32 ctx_oactxctrl_offset;
2045 u32 ctx_flexeu0_offset;
2048 * The RPT_ID/reason field for Gen8+ includes a bit
2049 * to determine if the CTX ID in the report is valid
2050 * but the specific bit differs between Gen 8 and 9
2052 u32 gen8_valid_ctx_bit;
2054 struct i915_oa_ops ops;
2055 const struct i915_oa_format *oa_formats;
2059 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2061 void (*resume)(struct drm_i915_private *);
2062 void (*cleanup_engine)(struct intel_engine_cs *engine);
2064 struct list_head timelines;
2066 struct list_head active_rings;
2067 struct list_head closed_vma;
2068 u32 active_requests;
2072 * Is the GPU currently considered idle, or busy executing
2073 * userspace requests? Whilst idle, we allow runtime power
2074 * management to power down the hardware and display clocks.
2075 * In order to reduce the effect on performance, there
2076 * is a slight delay before we do so.
2081 * The number of times we have woken up.
2084 #define I915_EPOCH_INVALID 0
2087 * We leave the user IRQ off as much as possible,
2088 * but this means that requests will finish and never
2089 * be retired once the system goes idle. Set a timer to
2090 * fire periodically while the ring is running. When it
2091 * fires, go retire requests.
2093 struct delayed_work retire_work;
2096 * When we detect an idle GPU, we want to turn on
2097 * powersaving features. So once we see that there
2098 * are no more requests outstanding and no more
2099 * arrive within a small period of time, we fire
2100 * off the idle_work.
2102 struct delayed_work idle_work;
2104 ktime_t last_init_time;
2107 /* perform PHY state sanity checks? */
2108 bool chv_phy_assert[2];
2112 /* Used to save the pipe-to-encoder mapping for audio */
2113 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2115 /* necessary resource sharing with HDMI LPE audio driver. */
2117 struct platform_device *platdev;
2121 struct i915_pmu pmu;
2124 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2125 * will be rejected. Instead look for a better place.
2129 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2131 return container_of(dev, struct drm_i915_private, drm);
2134 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2136 return to_i915(dev_get_drvdata(kdev));
2139 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2141 return container_of(wopcm, struct drm_i915_private, wopcm);
2144 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2146 return container_of(guc, struct drm_i915_private, guc);
2149 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2151 return container_of(huc, struct drm_i915_private, huc);
2154 /* Simple iterator over all initialised engines */
2155 #define for_each_engine(engine__, dev_priv__, id__) \
2157 (id__) < I915_NUM_ENGINES; \
2159 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2161 /* Iterator over subset of engines selected by mask */
2162 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2163 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2165 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2168 enum hdmi_force_audio {
2169 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2170 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2171 HDMI_AUDIO_AUTO, /* trust EDID */
2172 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2175 #define I915_GTT_OFFSET_NONE ((u32)-1)
2178 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2179 * considered to be the frontbuffer for the given plane interface-wise. This
2180 * doesn't mean that the hw necessarily already scans it out, but that any
2181 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2183 * We have one bit per pipe and per scanout plane type.
2185 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2186 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2187 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2188 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2189 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2191 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2192 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2193 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2194 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2195 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2198 * Optimised SGL iterator for GEM objects
2200 static __always_inline struct sgt_iter {
2201 struct scatterlist *sgp;
2208 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2209 struct sgt_iter s = { .sgp = sgl };
2212 s.max = s.curr = s.sgp->offset;
2213 s.max += s.sgp->length;
2215 s.dma = sg_dma_address(s.sgp);
2217 s.pfn = page_to_pfn(sg_page(s.sgp));
2223 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2226 if (unlikely(sg_is_chain(sg)))
2227 sg = sg_chain_ptr(sg);
2232 * __sg_next - return the next scatterlist entry in a list
2233 * @sg: The current sg entry
2236 * If the entry is the last, return NULL; otherwise, step to the next
2237 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2238 * otherwise just return the pointer to the current element.
2240 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2242 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2246 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2247 * @__dmap: DMA address (output)
2248 * @__iter: 'struct sgt_iter' (iterator state, internal)
2249 * @__sgt: sg_table to iterate over (input)
2251 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2252 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2253 ((__dmap) = (__iter).dma + (__iter).curr); \
2254 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2255 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2258 * for_each_sgt_page - iterate over the pages of the given sg_table
2259 * @__pp: page pointer (output)
2260 * @__iter: 'struct sgt_iter' (iterator state, internal)
2261 * @__sgt: sg_table to iterate over (input)
2263 #define for_each_sgt_page(__pp, __iter, __sgt) \
2264 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2265 ((__pp) = (__iter).pfn == 0 ? NULL : \
2266 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2267 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2268 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2270 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2272 unsigned int page_sizes;
2276 GEM_BUG_ON(sg->offset);
2277 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2278 page_sizes |= sg->length;
2285 static inline unsigned int i915_sg_segment_size(void)
2287 unsigned int size = swiotlb_max_segment();
2290 return SCATTERLIST_MAX_SEGMENT;
2292 size = rounddown(size, PAGE_SIZE);
2293 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2294 if (size < PAGE_SIZE)
2300 static inline const struct intel_device_info *
2301 intel_info(const struct drm_i915_private *dev_priv)
2303 return &dev_priv->info;
2306 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2307 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2309 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2310 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2312 #define REVID_FOREVER 0xff
2313 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2315 #define GEN_FOREVER (0)
2317 #define INTEL_GEN_MASK(s, e) ( \
2318 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2319 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2320 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2321 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2325 * Returns true if Gen is in inclusive range [Start, End].
2327 * Use GEN_FOREVER for unbound start and or end.
2329 #define IS_GEN(dev_priv, s, e) \
2330 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2333 * Return true if revision is in range [since,until] inclusive.
2335 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2337 #define IS_REVID(p, since, until) \
2338 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2340 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2342 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2343 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2344 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2345 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2346 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2347 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2348 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2349 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2350 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2351 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2352 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2353 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2354 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2355 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2356 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2357 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2358 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2359 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2360 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2361 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2362 (dev_priv)->info.gt == 1)
2363 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2364 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2365 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2366 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2367 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2368 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2369 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2370 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2371 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2372 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2373 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2374 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2375 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2376 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2377 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2378 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2379 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2380 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2381 /* ULX machines are also considered ULT. */
2382 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2383 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2384 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2385 (dev_priv)->info.gt == 3)
2386 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2387 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2388 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2389 (dev_priv)->info.gt == 3)
2390 /* ULX machines are also considered ULT. */
2391 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2392 INTEL_DEVID(dev_priv) == 0x0A1E)
2393 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2394 INTEL_DEVID(dev_priv) == 0x1913 || \
2395 INTEL_DEVID(dev_priv) == 0x1916 || \
2396 INTEL_DEVID(dev_priv) == 0x1921 || \
2397 INTEL_DEVID(dev_priv) == 0x1926)
2398 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2399 INTEL_DEVID(dev_priv) == 0x1915 || \
2400 INTEL_DEVID(dev_priv) == 0x191E)
2401 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2402 INTEL_DEVID(dev_priv) == 0x5913 || \
2403 INTEL_DEVID(dev_priv) == 0x5916 || \
2404 INTEL_DEVID(dev_priv) == 0x5921 || \
2405 INTEL_DEVID(dev_priv) == 0x5926)
2406 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2407 INTEL_DEVID(dev_priv) == 0x5915 || \
2408 INTEL_DEVID(dev_priv) == 0x591E)
2409 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2410 (dev_priv)->info.gt == 2)
2411 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2412 (dev_priv)->info.gt == 3)
2413 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2414 (dev_priv)->info.gt == 4)
2415 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2416 (dev_priv)->info.gt == 2)
2417 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2418 (dev_priv)->info.gt == 3)
2419 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2420 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2421 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2422 (dev_priv)->info.gt == 2)
2423 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2424 (dev_priv)->info.gt == 3)
2425 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2426 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2428 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2430 #define SKL_REVID_A0 0x0
2431 #define SKL_REVID_B0 0x1
2432 #define SKL_REVID_C0 0x2
2433 #define SKL_REVID_D0 0x3
2434 #define SKL_REVID_E0 0x4
2435 #define SKL_REVID_F0 0x5
2436 #define SKL_REVID_G0 0x6
2437 #define SKL_REVID_H0 0x7
2439 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2441 #define BXT_REVID_A0 0x0
2442 #define BXT_REVID_A1 0x1
2443 #define BXT_REVID_B0 0x3
2444 #define BXT_REVID_B_LAST 0x8
2445 #define BXT_REVID_C0 0x9
2447 #define IS_BXT_REVID(dev_priv, since, until) \
2448 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2450 #define KBL_REVID_A0 0x0
2451 #define KBL_REVID_B0 0x1
2452 #define KBL_REVID_C0 0x2
2453 #define KBL_REVID_D0 0x3
2454 #define KBL_REVID_E0 0x4
2456 #define IS_KBL_REVID(dev_priv, since, until) \
2457 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2459 #define GLK_REVID_A0 0x0
2460 #define GLK_REVID_A1 0x1
2462 #define IS_GLK_REVID(dev_priv, since, until) \
2463 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2465 #define CNL_REVID_A0 0x0
2466 #define CNL_REVID_B0 0x1
2467 #define CNL_REVID_C0 0x2
2469 #define IS_CNL_REVID(p, since, until) \
2470 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2472 #define ICL_REVID_A0 0x0
2473 #define ICL_REVID_A2 0x1
2474 #define ICL_REVID_B0 0x3
2475 #define ICL_REVID_B2 0x4
2476 #define ICL_REVID_C0 0x5
2478 #define IS_ICL_REVID(p, since, until) \
2479 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2482 * The genX designation typically refers to the render engine, so render
2483 * capability related checks should use IS_GEN, while display and other checks
2484 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2487 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2488 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2489 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2490 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2491 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2492 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2493 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2494 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2495 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2496 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2498 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2499 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2500 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2503 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
2504 * All later gens can run the final buffer from the ppgtt
2506 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN7(dev_priv)
2508 #define ENGINE_MASK(id) BIT(id)
2509 #define RENDER_RING ENGINE_MASK(RCS)
2510 #define BSD_RING ENGINE_MASK(VCS)
2511 #define BLT_RING ENGINE_MASK(BCS)
2512 #define VEBOX_RING ENGINE_MASK(VECS)
2513 #define BSD2_RING ENGINE_MASK(VCS2)
2514 #define BSD3_RING ENGINE_MASK(VCS3)
2515 #define BSD4_RING ENGINE_MASK(VCS4)
2516 #define VEBOX2_RING ENGINE_MASK(VECS2)
2517 #define ALL_ENGINES (~0)
2519 #define HAS_ENGINE(dev_priv, id) \
2520 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2522 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2523 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2524 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2525 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2527 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2529 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
2531 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2532 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2533 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2534 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2535 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2537 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2539 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2540 ((dev_priv)->info.has_logical_ring_contexts)
2541 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2542 ((dev_priv)->info.has_logical_ring_elsq)
2543 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2544 ((dev_priv)->info.has_logical_ring_preemption)
2546 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2548 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2549 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2550 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2551 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2552 GEM_BUG_ON((sizes) == 0); \
2553 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2556 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2557 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2558 ((dev_priv)->info.overlay_needs_physical)
2560 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2561 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2563 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
2564 (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) == 9)
2566 /* WaRsDisableCoarsePowerGating:skl,cnl */
2567 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2568 (IS_CANNONLAKE(dev_priv) || INTEL_GEN(dev_priv) == 9)
2570 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2571 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2572 IS_GEMINILAKE(dev_priv) || \
2573 IS_KABYLAKE(dev_priv))
2575 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2576 * rows, which changed the alignment requirements and fence programming.
2578 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2579 !(IS_I915G(dev_priv) || \
2580 IS_I915GM(dev_priv)))
2581 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2582 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2584 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2585 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2586 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2588 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2590 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2592 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2593 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2594 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2596 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2597 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2598 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2600 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2602 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2603 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2605 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2608 * For now, anything with a GuC requires uCode loading, and then supports
2609 * command submission once loaded. But these are logically independent
2610 * properties, so we have separate macros to test them.
2612 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2613 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2614 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2615 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2617 /* For now, anything with a GuC has also HuC */
2618 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2619 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2621 /* Having a GuC is not the same as using a GuC */
2622 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2623 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2624 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2626 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2628 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2630 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2631 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2632 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2633 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2634 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2635 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2636 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2637 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2638 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2639 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2640 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2641 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2642 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2643 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2644 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2645 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2646 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2648 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2649 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2650 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2651 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2652 #define HAS_PCH_CNP_LP(dev_priv) \
2653 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2654 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2655 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2656 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2657 #define HAS_PCH_LPT_LP(dev_priv) \
2658 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2659 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2660 #define HAS_PCH_LPT_H(dev_priv) \
2661 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2662 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2663 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2664 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2665 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2666 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2668 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2670 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2672 /* DPF == dynamic parity feature */
2673 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2674 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2675 2 : HAS_L3_DPF(dev_priv))
2677 #define GT_FREQUENCY_MULTIPLIER 50
2678 #define GEN9_FREQ_SCALER 3
2680 #include "i915_trace.h"
2682 static inline bool intel_vtd_active(void)
2684 #ifdef CONFIG_INTEL_IOMMU
2685 if (intel_iommu_gfx_mapped)
2689 /* Running as a guest, we assume the host is enforcing VT'd */
2690 return !hypervisor_is_type(X86_HYPER_NATIVE);
2693 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2695 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2699 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2701 return IS_BROXTON(dev_priv) && intel_vtd_active();
2704 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2709 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2710 const char *fmt, ...);
2712 #define i915_report_error(dev_priv, fmt, ...) \
2713 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2715 #ifdef CONFIG_COMPAT
2716 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2719 #define i915_compat_ioctl NULL
2721 extern const struct dev_pm_ops i915_pm_ops;
2723 extern int i915_driver_load(struct pci_dev *pdev,
2724 const struct pci_device_id *ent);
2725 extern void i915_driver_unload(struct drm_device *dev);
2726 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2727 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2729 extern void i915_reset(struct drm_i915_private *i915,
2730 unsigned int stalled_mask,
2731 const char *reason);
2732 extern int i915_reset_engine(struct intel_engine_cs *engine,
2733 const char *reason);
2735 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2736 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2737 extern int intel_guc_reset_engine(struct intel_guc *guc,
2738 struct intel_engine_cs *engine);
2739 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2740 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2741 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2742 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2743 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2744 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2745 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2747 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2748 int intel_engines_init(struct drm_i915_private *dev_priv);
2750 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2752 /* intel_hotplug.c */
2753 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2754 u32 pin_mask, u32 long_mask);
2755 void intel_hpd_init(struct drm_i915_private *dev_priv);
2756 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2757 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2758 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2760 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2761 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2764 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2766 unsigned long delay;
2768 if (unlikely(!i915_modparams.enable_hangcheck))
2771 /* Don't continually defer the hangcheck so that it is always run at
2772 * least once after work has been scheduled on any ring. Otherwise,
2773 * we will ignore a hung ring if a second ring is kept busy.
2776 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2777 queue_delayed_work(system_long_wq,
2778 &dev_priv->gpu_error.hangcheck_work, delay);
2782 void i915_handle_error(struct drm_i915_private *dev_priv,
2784 unsigned long flags,
2785 const char *fmt, ...);
2786 #define I915_ERROR_CAPTURE BIT(0)
2788 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2789 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2790 int intel_irq_install(struct drm_i915_private *dev_priv);
2791 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2793 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2795 return dev_priv->gvt;
2798 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2800 return dev_priv->vgpu.active;
2803 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2806 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2810 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2813 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2814 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2815 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2818 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2819 uint32_t interrupt_mask,
2820 uint32_t enabled_irq_mask);
2822 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2824 ilk_update_display_irq(dev_priv, bits, bits);
2827 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2829 ilk_update_display_irq(dev_priv, bits, 0);
2831 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2833 uint32_t interrupt_mask,
2834 uint32_t enabled_irq_mask);
2835 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2836 enum pipe pipe, uint32_t bits)
2838 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2840 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2841 enum pipe pipe, uint32_t bits)
2843 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2845 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2846 uint32_t interrupt_mask,
2847 uint32_t enabled_irq_mask);
2849 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2851 ibx_display_interrupt_update(dev_priv, bits, bits);
2854 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2856 ibx_display_interrupt_update(dev_priv, bits, 0);
2860 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2861 struct drm_file *file_priv);
2862 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2863 struct drm_file *file_priv);
2864 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2865 struct drm_file *file_priv);
2866 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2867 struct drm_file *file_priv);
2868 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2869 struct drm_file *file_priv);
2870 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2871 struct drm_file *file_priv);
2872 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2873 struct drm_file *file_priv);
2874 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2875 struct drm_file *file_priv);
2876 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2877 struct drm_file *file_priv);
2878 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2879 struct drm_file *file_priv);
2880 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2881 struct drm_file *file);
2882 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2883 struct drm_file *file);
2884 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2885 struct drm_file *file_priv);
2886 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2887 struct drm_file *file_priv);
2888 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2889 struct drm_file *file_priv);
2890 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2891 struct drm_file *file_priv);
2892 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2893 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2894 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2895 struct drm_file *file);
2896 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2897 struct drm_file *file_priv);
2898 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2899 struct drm_file *file_priv);
2900 void i915_gem_sanitize(struct drm_i915_private *i915);
2901 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2902 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2903 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2904 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2905 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2907 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2908 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2909 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2910 const struct drm_i915_gem_object_ops *ops);
2911 struct drm_i915_gem_object *
2912 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2913 struct drm_i915_gem_object *
2914 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2915 const void *data, size_t size);
2916 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2917 void i915_gem_free_object(struct drm_gem_object *obj);
2919 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2921 if (!atomic_read(&i915->mm.free_count))
2924 /* A single pass should suffice to release all the freed objects (along
2925 * most call paths) , but be a little more paranoid in that freeing
2926 * the objects does take a little amount of time, during which the rcu
2927 * callbacks could have added new objects into the freed list, and
2928 * armed the work again.
2932 } while (flush_work(&i915->mm.free_work));
2935 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2938 * Similar to objects above (see i915_gem_drain_freed-objects), in
2939 * general we have workers that are armed by RCU and then rearm
2940 * themselves in their callbacks. To be paranoid, we need to
2941 * drain the workqueue a second time after waiting for the RCU
2942 * grace period so that we catch work queued via RCU from the first
2943 * pass. As neither drain_workqueue() nor flush_workqueue() report
2944 * a result, we make an assumption that we only don't require more
2945 * than 2 passes to catch all recursive RCU delayed work.
2951 drain_workqueue(i915->wq);
2955 struct i915_vma * __must_check
2956 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2957 const struct i915_ggtt_view *view,
2962 struct i915_vma * __must_check
2963 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2964 struct i915_address_space *vm,
2965 const struct i915_ggtt_view *view,
2970 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2971 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2973 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2975 static inline int __sg_page_count(const struct scatterlist *sg)
2977 return sg->length >> PAGE_SHIFT;
2980 struct scatterlist *
2981 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2982 unsigned int n, unsigned int *offset);
2985 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2989 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2993 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2996 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2997 struct sg_table *pages,
2998 unsigned int sg_page_sizes);
2999 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3001 static inline int __must_check
3002 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3004 might_lock(&obj->mm.lock);
3006 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3009 return __i915_gem_object_get_pages(obj);
3013 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
3015 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3019 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3021 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3023 atomic_inc(&obj->mm.pages_pin_count);
3027 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3029 return atomic_read(&obj->mm.pages_pin_count);
3033 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3035 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3036 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3038 atomic_dec(&obj->mm.pages_pin_count);
3042 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3044 __i915_gem_object_unpin_pages(obj);
3047 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3052 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3053 enum i915_mm_subclass subclass);
3054 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3056 enum i915_map_type {
3059 #define I915_MAP_OVERRIDE BIT(31)
3060 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3061 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3065 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3066 * @obj: the object to map into kernel address space
3067 * @type: the type of mapping, used to select pgprot_t
3069 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3070 * pages and then returns a contiguous mapping of the backing storage into
3071 * the kernel address space. Based on the @type of mapping, the PTE will be
3072 * set to either WriteBack or WriteCombine (via pgprot_t).
3074 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3075 * mapping is no longer required.
3077 * Returns the pointer through which to access the mapped object, or an
3078 * ERR_PTR() on error.
3080 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3081 enum i915_map_type type);
3084 * i915_gem_object_unpin_map - releases an earlier mapping
3085 * @obj: the object to unmap
3087 * After pinning the object and mapping its pages, once you are finished
3088 * with your access, call i915_gem_object_unpin_map() to release the pin
3089 * upon the mapping. Once the pin count reaches zero, that mapping may be
3092 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3094 i915_gem_object_unpin_pages(obj);
3097 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3098 unsigned int *needs_clflush);
3099 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3100 unsigned int *needs_clflush);
3101 #define CLFLUSH_BEFORE BIT(0)
3102 #define CLFLUSH_AFTER BIT(1)
3103 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3106 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3108 i915_gem_object_unpin_pages(obj);
3111 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3112 int i915_gem_dumb_create(struct drm_file *file_priv,
3113 struct drm_device *dev,
3114 struct drm_mode_create_dumb *args);
3115 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3116 uint32_t handle, uint64_t *offset);
3117 int i915_gem_mmap_gtt_version(void);
3119 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3120 struct drm_i915_gem_object *new,
3121 unsigned frontbuffer_bits);
3123 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3125 struct i915_request *
3126 i915_gem_find_active_request(struct intel_engine_cs *engine);
3128 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3130 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3133 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3135 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3138 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3140 return unlikely(test_bit(I915_WEDGED, &error->flags));
3143 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3145 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3148 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3150 return READ_ONCE(error->reset_count);
3153 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3154 struct intel_engine_cs *engine)
3156 return READ_ONCE(error->reset_engine_count[engine->id]);
3159 struct i915_request *
3160 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3161 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3162 void i915_gem_reset(struct drm_i915_private *dev_priv,
3163 unsigned int stalled_mask);
3164 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3165 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3166 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3167 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3168 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3169 struct i915_request *request,
3172 void i915_gem_init_mmio(struct drm_i915_private *i915);
3173 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3174 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3175 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3176 void i915_gem_fini(struct drm_i915_private *dev_priv);
3177 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3178 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3179 unsigned int flags, long timeout);
3180 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3181 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3182 void i915_gem_resume(struct drm_i915_private *dev_priv);
3183 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3184 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3187 struct intel_rps_client *rps);
3188 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3190 const struct i915_sched_attr *attr);
3191 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3194 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3196 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3198 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3199 struct i915_vma * __must_check
3200 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3202 const struct i915_ggtt_view *view,
3203 unsigned int flags);
3204 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3205 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3207 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3208 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3210 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3211 enum i915_cache_level cache_level);
3213 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3214 struct dma_buf *dma_buf);
3216 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3217 struct drm_gem_object *gem_obj, int flags);
3219 static inline struct i915_hw_ppgtt *
3220 i915_vm_to_ppgtt(struct i915_address_space *vm)
3222 return container_of(vm, struct i915_hw_ppgtt, vm);
3225 /* i915_gem_fence_reg.c */
3226 struct drm_i915_fence_reg *
3227 i915_reserve_fence(struct drm_i915_private *dev_priv);
3228 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3230 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3231 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3233 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3234 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3235 struct sg_table *pages);
3236 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3237 struct sg_table *pages);
3239 static inline struct i915_gem_context *
3240 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3242 return idr_find(&file_priv->context_idr, id);
3245 static inline struct i915_gem_context *
3246 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3248 struct i915_gem_context *ctx;
3251 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3252 if (ctx && !kref_get_unless_zero(&ctx->ref))
3259 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3260 struct drm_file *file);
3261 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3262 struct drm_file *file);
3263 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3264 struct drm_file *file);
3265 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3266 struct i915_gem_context *ctx,
3267 uint32_t *reg_state);
3269 /* i915_gem_evict.c */
3270 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3271 u64 min_size, u64 alignment,
3272 unsigned cache_level,
3275 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3276 struct drm_mm_node *node,
3277 unsigned int flags);
3278 int i915_gem_evict_vm(struct i915_address_space *vm);
3280 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3282 /* belongs in i915_gem_gtt.h */
3283 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3286 if (INTEL_GEN(dev_priv) < 6)
3287 intel_gtt_chipset_flush();
3290 /* i915_gem_stolen.c */
3291 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3292 struct drm_mm_node *node, u64 size,
3293 unsigned alignment);
3294 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3295 struct drm_mm_node *node, u64 size,
3296 unsigned alignment, u64 start,
3298 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3299 struct drm_mm_node *node);
3300 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3301 void i915_gem_cleanup_stolen(struct drm_device *dev);
3302 struct drm_i915_gem_object *
3303 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3304 resource_size_t size);
3305 struct drm_i915_gem_object *
3306 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3307 resource_size_t stolen_offset,
3308 resource_size_t gtt_offset,
3309 resource_size_t size);
3311 /* i915_gem_internal.c */
3312 struct drm_i915_gem_object *
3313 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3316 /* i915_gem_shrinker.c */
3317 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3318 unsigned long target,
3319 unsigned long *nr_scanned,
3321 #define I915_SHRINK_PURGEABLE 0x1
3322 #define I915_SHRINK_UNBOUND 0x2
3323 #define I915_SHRINK_BOUND 0x4
3324 #define I915_SHRINK_ACTIVE 0x8
3325 #define I915_SHRINK_VMAPS 0x10
3326 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3327 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3328 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3329 void i915_gem_shrinker_taints_mutex(struct mutex *mutex);
3331 /* i915_gem_tiling.c */
3332 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3334 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3336 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3337 i915_gem_object_is_tiled(obj);
3340 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3341 unsigned int tiling, unsigned int stride);
3342 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3343 unsigned int tiling, unsigned int stride);
3345 /* i915_debugfs.c */
3346 #ifdef CONFIG_DEBUG_FS
3347 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3348 int i915_debugfs_connector_add(struct drm_connector *connector);
3349 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3351 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3352 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3354 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3357 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3359 /* i915_cmd_parser.c */
3360 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3361 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3362 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3363 int intel_engine_cmd_parser(struct i915_gem_context *cxt,
3364 struct intel_engine_cs *engine,
3365 struct drm_i915_gem_object *batch_obj,
3366 u64 user_batch_start,
3367 u32 batch_start_offset,
3369 struct drm_i915_gem_object *shadow_batch_obj,
3370 u64 shadow_batch_start);
3373 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3374 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3375 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3376 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3378 /* i915_suspend.c */
3379 extern int i915_save_state(struct drm_i915_private *dev_priv);
3380 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3383 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3384 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3386 /* intel_lpe_audio.c */
3387 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3388 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3389 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3390 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3391 enum pipe pipe, enum port port,
3392 const void *eld, int ls_clock, bool dp_output);
3395 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3396 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3397 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3399 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3401 extern struct i2c_adapter *
3402 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3403 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3404 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3405 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3407 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3409 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3412 void intel_bios_init(struct drm_i915_private *dev_priv);
3413 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3414 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3415 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3416 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3417 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3418 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3419 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3420 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3421 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3423 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3428 extern void intel_register_dsm_handler(void);
3429 extern void intel_unregister_dsm_handler(void);
3431 static inline void intel_register_dsm_handler(void) { return; }
3432 static inline void intel_unregister_dsm_handler(void) { return; }
3433 #endif /* CONFIG_ACPI */
3435 /* intel_device_info.c */
3436 static inline struct intel_device_info *
3437 mkwrite_device_info(struct drm_i915_private *dev_priv)
3439 return (struct intel_device_info *)&dev_priv->info;
3443 extern void intel_modeset_init_hw(struct drm_device *dev);
3444 extern int intel_modeset_init(struct drm_device *dev);
3445 extern void intel_modeset_cleanup(struct drm_device *dev);
3446 extern int intel_connector_register(struct drm_connector *);
3447 extern void intel_connector_unregister(struct drm_connector *);
3448 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3450 extern void intel_display_resume(struct drm_device *dev);
3451 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3452 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3453 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3454 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3455 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3456 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3458 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3461 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3462 struct drm_file *file);
3465 extern struct intel_overlay_error_state *
3466 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3467 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3468 struct intel_overlay_error_state *error);
3470 extern struct intel_display_error_state *
3471 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3472 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3473 struct intel_display_error_state *error);
3475 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3476 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3477 u32 val, int fast_timeout_us,
3478 int slow_timeout_ms);
3479 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3480 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3482 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3483 u32 reply_mask, u32 reply, int timeout_base_ms);
3485 /* intel_sideband.c */
3486 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3487 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3488 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3489 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3490 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3491 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3492 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3493 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3494 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3495 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3496 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3497 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3498 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3499 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3500 enum intel_sbi_destination destination);
3501 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3502 enum intel_sbi_destination destination);
3503 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3504 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3506 /* intel_dpio_phy.c */
3507 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3508 enum dpio_phy *phy, enum dpio_channel *ch);
3509 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3510 enum port port, u32 margin, u32 scale,
3511 u32 enable, u32 deemphasis);
3512 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3513 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3514 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3516 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3518 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3519 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3520 uint8_t lane_lat_optim_mask);
3521 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3523 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3524 u32 deemph_reg_value, u32 margin_reg_value,
3525 bool uniq_trans_scale);
3526 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3527 const struct intel_crtc_state *crtc_state,
3529 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3530 const struct intel_crtc_state *crtc_state);
3531 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3532 const struct intel_crtc_state *crtc_state);
3533 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3534 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3535 const struct intel_crtc_state *old_crtc_state);
3537 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3538 u32 demph_reg_value, u32 preemph_reg_value,
3539 u32 uniqtranscale_reg_value, u32 tx3_demph);
3540 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *crtc_state);
3542 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3543 const struct intel_crtc_state *crtc_state);
3544 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3545 const struct intel_crtc_state *old_crtc_state);
3547 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3548 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3549 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3550 const i915_reg_t reg);
3552 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3554 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3555 const i915_reg_t reg)
3557 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3560 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3561 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3563 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3564 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3565 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3566 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3568 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3569 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3570 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3571 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3573 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3574 * will be implemented using 2 32-bit writes in an arbitrary order with
3575 * an arbitrary delay between them. This can cause the hardware to
3576 * act upon the intermediate value, possibly leading to corruption and
3577 * machine death. For this reason we do not support I915_WRITE64, or
3578 * dev_priv->uncore.funcs.mmio_writeq.
3580 * When reading a 64-bit value as two 32-bit values, the delay may cause
3581 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3582 * occasionally a 64-bit register does not actualy support a full readq
3583 * and must be read using two 32-bit reads.
3585 * You have been warned.
3587 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3589 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3590 u32 upper, lower, old_upper, loop = 0; \
3591 upper = I915_READ(upper_reg); \
3593 old_upper = upper; \
3594 lower = I915_READ(lower_reg); \
3595 upper = I915_READ(upper_reg); \
3596 } while (upper != old_upper && loop++ < 2); \
3597 (u64)upper << 32 | lower; })
3599 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3600 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3602 #define __raw_read(x, s) \
3603 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3606 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3609 #define __raw_write(x, s) \
3610 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3611 i915_reg_t reg, uint##x##_t val) \
3613 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3628 /* These are untraced mmio-accessors that are only valid to be used inside
3629 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3632 * Think twice, and think again, before using these.
3634 * As an example, these accessors can possibly be used between:
3636 * spin_lock_irq(&dev_priv->uncore.lock);
3637 * intel_uncore_forcewake_get__locked();
3641 * intel_uncore_forcewake_put__locked();
3642 * spin_unlock_irq(&dev_priv->uncore.lock);
3645 * Note: some registers may not need forcewake held, so
3646 * intel_uncore_forcewake_{get,put} can be omitted, see
3647 * intel_uncore_forcewake_for_reg().
3649 * Certain architectures will die if the same cacheline is concurrently accessed
3650 * by different clients (e.g. on Ivybridge). Access to registers should
3651 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3652 * a more localised lock guarding all access to that bank of registers.
3654 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3655 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3656 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3657 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3659 /* "Broadcast RGB" property */
3660 #define INTEL_BROADCAST_RGB_AUTO 0
3661 #define INTEL_BROADCAST_RGB_FULL 1
3662 #define INTEL_BROADCAST_RGB_LIMITED 2
3664 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3666 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3667 return VLV_VGACNTRL;
3668 else if (INTEL_GEN(dev_priv) >= 5)
3669 return CPU_VGACNTRL;
3674 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3676 unsigned long j = msecs_to_jiffies(m);
3678 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3681 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3683 /* nsecs_to_jiffies64() does not guard against overflow */
3684 if (NSEC_PER_SEC % HZ &&
3685 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3686 return MAX_JIFFY_OFFSET;
3688 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3692 * If you need to wait X milliseconds between events A and B, but event B
3693 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3694 * when event A happened, then just before event B you call this function and
3695 * pass the timestamp as the first argument, and X as the second argument.
3698 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3700 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3703 * Don't re-read the value of "jiffies" every time since it may change
3704 * behind our back and break the math.
3706 tmp_jiffies = jiffies;
3707 target_jiffies = timestamp_jiffies +
3708 msecs_to_jiffies_timeout(to_wait_ms);
3710 if (time_after(target_jiffies, tmp_jiffies)) {
3711 remaining_jiffies = target_jiffies - tmp_jiffies;
3712 while (remaining_jiffies)
3714 schedule_timeout_uninterruptible(remaining_jiffies);
3719 __i915_request_irq_complete(const struct i915_request *rq)
3721 struct intel_engine_cs *engine = rq->engine;
3724 /* Note that the engine may have wrapped around the seqno, and
3725 * so our request->global_seqno will be ahead of the hardware,
3726 * even though it completed the request before wrapping. We catch
3727 * this by kicking all the waiters before resetting the seqno
3728 * in hardware, and also signal the fence.
3730 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3733 /* The request was dequeued before we were awoken. We check after
3734 * inspecting the hw to confirm that this was the same request
3735 * that generated the HWS update. The memory barriers within
3736 * the request execution are sufficient to ensure that a check
3737 * after reading the value from hw matches this request.
3739 seqno = i915_request_global_seqno(rq);
3743 /* Before we do the heavier coherent read of the seqno,
3744 * check the value (hopefully) in the CPU cacheline.
3746 if (__i915_request_completed(rq, seqno))
3749 /* Ensure our read of the seqno is coherent so that we
3750 * do not "miss an interrupt" (i.e. if this is the last
3751 * request and the seqno write from the GPU is not visible
3752 * by the time the interrupt fires, we will see that the
3753 * request is incomplete and go back to sleep awaiting
3754 * another interrupt that will never come.)
3756 * Strictly, we only need to do this once after an interrupt,
3757 * but it is easier and safer to do it every time the waiter
3760 if (engine->irq_seqno_barrier &&
3761 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3762 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3764 /* The ordering of irq_posted versus applying the barrier
3765 * is crucial. The clearing of the current irq_posted must
3766 * be visible before we perform the barrier operation,
3767 * such that if a subsequent interrupt arrives, irq_posted
3768 * is reasserted and our task rewoken (which causes us to
3769 * do another __i915_request_irq_complete() immediately
3770 * and reapply the barrier). Conversely, if the clear
3771 * occurs after the barrier, then an interrupt that arrived
3772 * whilst we waited on the barrier would not trigger a
3773 * barrier on the next pass, and the read may not see the
3776 engine->irq_seqno_barrier(engine);
3778 /* If we consume the irq, but we are no longer the bottom-half,
3779 * the real bottom-half may not have serialised their own
3780 * seqno check with the irq-barrier (i.e. may have inspected
3781 * the seqno before we believe it coherent since they see
3782 * irq_posted == false but we are still running).
3784 spin_lock_irq(&b->irq_lock);
3785 if (b->irq_wait && b->irq_wait->tsk != current)
3786 /* Note that if the bottom-half is changed as we
3787 * are sending the wake-up, the new bottom-half will
3788 * be woken by whomever made the change. We only have
3789 * to worry about when we steal the irq-posted for
3792 wake_up_process(b->irq_wait->tsk);
3793 spin_unlock_irq(&b->irq_lock);
3795 if (__i915_request_completed(rq, seqno))
3802 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3803 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3805 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3806 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3807 * perform the operation. To check beforehand, pass in the parameters to
3808 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3809 * you only need to pass in the minor offsets, page-aligned pointers are
3812 * For just checking for SSE4.1, in the foreknowledge that the future use
3813 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3815 #define i915_can_memcpy_from_wc(dst, src, len) \
3816 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3818 #define i915_has_memcpy_from_wc() \
3819 i915_memcpy_from_wc(NULL, NULL, 0)
3822 int remap_io_mapping(struct vm_area_struct *vma,
3823 unsigned long addr, unsigned long pfn, unsigned long size,
3824 struct io_mapping *iomap);
3826 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3828 if (INTEL_GEN(i915) >= 10)
3829 return CNL_HWS_CSB_WRITE_INDEX;
3831 return I915_HWS_CSB_WRITE_INDEX;