2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Brad Volkin <bradley.d.volkin@intel.com>
29 #include "intel_ringbuffer.h"
32 * DOC: batch buffer command parser
35 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
36 * require userspace code to submit batches containing commands such as
37 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
38 * generations of the hardware will noop these commands in "unsecure" batches
39 * (which includes all userspace batches submitted via i915) even though the
40 * commands may be safe and represent the intended programming model of the
43 * The software command parser is similar in operation to the command parsing
44 * done in hardware for unsecure batches. However, the software parser allows
45 * some operations that would be noop'd by hardware, if the parser determines
46 * the operation is safe, and submits the batch as "secure" to prevent hardware
50 * At a high level, the hardware (and software) checks attempt to prevent
51 * granting userspace undue privileges. There are three categories of privilege.
53 * First, commands which are explicitly defined as privileged or which should
54 * only be used by the kernel driver. The parser rejects such commands
56 * Second, commands which access registers. To support correct/enhanced
57 * userspace functionality, particularly certain OpenGL extensions, the parser
58 * provides a whitelist of registers which userspace may safely access
60 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
61 * The parser always rejects such commands.
63 * The majority of the problematic commands fall in the MI_* range, with only a
64 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
67 * Each engine maintains tables of commands and registers which the parser
68 * uses in scanning batch buffers submitted to that engine.
70 * Since the set of commands that the parser must check for is significantly
71 * smaller than the number of commands supported, the parser tables contain only
72 * those commands required by the parser. This generally works because command
73 * opcode ranges have standard command length encodings. So for commands that
74 * the parser does not need to check, it can easily skip them. This is
75 * implemented via a per-engine length decoding vfunc.
77 * Unfortunately, there are a number of commands that do not follow the standard
78 * length encoding for their opcode range, primarily amongst the MI_* commands.
79 * To handle this, the parser provides a way to define explicit "skip" entries
80 * in the per-engine command tables.
82 * Other command table entries map fairly directly to high level categories
83 * mentioned above: rejected, register whitelist. The parser implements a number
84 * of checks, including the privileged memory checks, via a general bitmasking
89 * A command that requires special handling by the command parser.
91 struct drm_i915_cmd_descriptor {
93 * Flags describing how the command parser processes the command.
95 * CMD_DESC_FIXED: The command has a fixed length if this is set,
96 * a length mask if not set
97 * CMD_DESC_SKIP: The command is allowed but does not follow the
98 * standard length encoding for the opcode range in
100 * CMD_DESC_REJECT: The command is never allowed
101 * CMD_DESC_REGISTER: The command should be checked against the
102 * register whitelist for the appropriate ring
105 #define CMD_DESC_FIXED (1<<0)
106 #define CMD_DESC_SKIP (1<<1)
107 #define CMD_DESC_REJECT (1<<2)
108 #define CMD_DESC_REGISTER (1<<3)
109 #define CMD_DESC_BITMASK (1<<4)
112 * The command's unique identification bits and the bitmask to get them.
113 * This isn't strictly the opcode field as defined in the spec and may
114 * also include type, subtype, and/or subop fields.
122 * The command's length. The command is either fixed length (i.e. does
123 * not include a length field) or has a length field mask. The flag
124 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
125 * a length mask. All command entries in a command table must include
126 * length information.
134 * Describes where to find a register address in the command to check
135 * against the ring's register whitelist. Only valid if flags has the
136 * CMD_DESC_REGISTER bit set.
138 * A non-zero step value implies that the command may access multiple
139 * registers in sequence (e.g. LRI), in that case step gives the
140 * distance in dwords between individual offset fields.
148 #define MAX_CMD_DESC_BITMASKS 3
150 * Describes command checks where a particular dword is masked and
151 * compared against an expected value. If the command does not match
152 * the expected value, the parser rejects it. Only valid if flags has
153 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
156 * If the check specifies a non-zero condition_mask then the parser
157 * only performs the check when the bits specified by condition_mask
164 u32 condition_offset;
166 } bits[MAX_CMD_DESC_BITMASKS];
170 * A table of commands requiring special handling by the command parser.
172 * Each engine has an array of tables. Each table consists of an array of
173 * command descriptors, which must be sorted with command opcodes in
176 struct drm_i915_cmd_table {
177 const struct drm_i915_cmd_descriptor *table;
181 #define STD_MI_OPCODE_SHIFT (32 - 9)
182 #define STD_3D_OPCODE_SHIFT (32 - 16)
183 #define STD_2D_OPCODE_SHIFT (32 - 10)
184 #define STD_MFX_OPCODE_SHIFT (32 - 16)
185 #define MIN_OPCODE_SHIFT 16
187 #define CMD(op, opm, f, lm, fl, ...) \
189 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
190 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \
191 .length = { (lm) }, \
195 /* Convenience macros to compress the tables */
196 #define SMI STD_MI_OPCODE_SHIFT
197 #define S3D STD_3D_OPCODE_SHIFT
198 #define S2D STD_2D_OPCODE_SHIFT
199 #define SMFX STD_MFX_OPCODE_SHIFT
201 #define S CMD_DESC_SKIP
202 #define R CMD_DESC_REJECT
203 #define W CMD_DESC_REGISTER
204 #define B CMD_DESC_BITMASK
206 /* Command Mask Fixed Len Action
207 ---------------------------------------------------------- */
208 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
209 CMD( MI_NOOP, SMI, F, 1, S ),
210 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
211 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
212 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
213 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
214 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
215 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
216 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
217 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
218 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
219 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
220 .reg = { .offset = 1, .mask = 0x007FFFFC },
223 .mask = MI_GLOBAL_GTT,
226 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
227 .reg = { .offset = 1, .mask = 0x007FFFFC },
230 .mask = MI_GLOBAL_GTT,
234 * MI_BATCH_BUFFER_START requires some special handling. It's not
235 * really a 'skip' action but it doesn't seem like it's worth adding
236 * a new action. See i915_parse_cmds().
238 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
241 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
242 CMD( MI_FLUSH, SMI, F, 1, S ),
243 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
244 CMD( MI_PREDICATE, SMI, F, 1, S ),
245 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
246 CMD( MI_SET_APPID, SMI, F, 1, S ),
247 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
248 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
249 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
250 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
253 .mask = MI_GLOBAL_GTT,
256 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
257 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
260 .mask = MI_GLOBAL_GTT,
263 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
266 .mask = MI_REPORT_PERF_COUNT_GGTT,
269 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
272 .mask = MI_GLOBAL_GTT,
275 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
276 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
277 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
280 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
283 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
284 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
285 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
286 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
289 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
294 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
295 PIPE_CONTROL_STORE_DATA_INDEX),
297 .condition_offset = 1,
298 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
302 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
303 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
304 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
305 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
306 CMD( MI_SET_APPID, SMI, F, 1, S ),
307 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
308 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
309 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
310 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
311 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
312 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
313 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
314 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
315 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
316 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
318 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
319 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
320 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
321 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
322 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
325 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
326 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
327 CMD( MI_SET_APPID, SMI, F, 1, S ),
328 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
331 .mask = MI_GLOBAL_GTT,
334 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
335 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
338 .mask = MI_FLUSH_DW_NOTIFY,
343 .mask = MI_FLUSH_DW_USE_GTT,
345 .condition_offset = 0,
346 .condition_mask = MI_FLUSH_DW_OP_MASK,
350 .mask = MI_FLUSH_DW_STORE_INDEX,
352 .condition_offset = 0,
353 .condition_mask = MI_FLUSH_DW_OP_MASK,
355 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
358 .mask = MI_GLOBAL_GTT,
362 * MFX_WAIT doesn't fit the way we handle length for most commands.
363 * It has a length field but it uses a non-standard length bias.
364 * It is always 1 dword though, so just treat it as fixed length.
366 CMD( MFX_WAIT, SMFX, F, 1, S ),
369 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
370 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
371 CMD( MI_SET_APPID, SMI, F, 1, S ),
372 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
375 .mask = MI_GLOBAL_GTT,
378 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
379 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
382 .mask = MI_FLUSH_DW_NOTIFY,
387 .mask = MI_FLUSH_DW_USE_GTT,
389 .condition_offset = 0,
390 .condition_mask = MI_FLUSH_DW_OP_MASK,
394 .mask = MI_FLUSH_DW_STORE_INDEX,
396 .condition_offset = 0,
397 .condition_mask = MI_FLUSH_DW_OP_MASK,
399 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
402 .mask = MI_GLOBAL_GTT,
407 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
408 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
409 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
412 .mask = MI_GLOBAL_GTT,
415 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
416 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
419 .mask = MI_FLUSH_DW_NOTIFY,
424 .mask = MI_FLUSH_DW_USE_GTT,
426 .condition_offset = 0,
427 .condition_mask = MI_FLUSH_DW_OP_MASK,
431 .mask = MI_FLUSH_DW_STORE_INDEX,
433 .condition_offset = 0,
434 .condition_mask = MI_FLUSH_DW_OP_MASK,
436 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
437 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
440 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
441 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
442 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
446 * For Gen9 we can still rely on the h/w to enforce cmd security, and only
447 * need to re-enforce the register access checks. We therefore only need to
448 * teach the cmdparser how to find the end of each command, and identify
449 * register accesses. The table doesn't need to reject any commands, and so
450 * the only commands listed here are:
451 * 1) Those that touch registers
452 * 2) Those that do not have the default 8-bit length
454 * Note that the default MI length mask chosen for this table is 0xFF, not
455 * the 0x3F used on older devices. This is because the vast majority of MI
456 * cmds on Gen9 use a standard 8-bit Length field.
457 * All the Gen9 blitter instructions are standard 0xFF length mask, and
458 * none allow access to non-general registers, so in fact no BLT cmds are
459 * included in the table at all.
462 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = {
463 CMD( MI_NOOP, SMI, F, 1, S ),
464 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
465 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
466 CMD( MI_FLUSH, SMI, F, 1, S ),
467 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
468 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
469 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
470 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
471 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),
472 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),
473 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
474 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
475 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
476 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),
477 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,
478 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
479 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
480 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,
481 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
482 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
483 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
486 * We allow BB_START but apply further checks. We just sanitize the
489 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
490 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1)
491 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,
494 .mask = MI_BB_START_OPERAND_MASK,
495 .expected = MI_BB_START_OPERAND_EXPECT,
499 static const struct drm_i915_cmd_descriptor noop_desc =
500 CMD(MI_NOOP, SMI, F, 1, S);
513 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
514 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
515 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
518 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
519 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
520 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
521 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
524 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
525 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
526 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
529 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
530 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
531 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
534 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
535 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
536 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
539 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
540 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
541 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
542 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
545 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = {
546 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) },
551 * Register whitelists, sorted by increasing register offset.
555 * An individual whitelist entry granting access to register addr. If
556 * mask is non-zero the argument of immediate register writes will be
557 * AND-ed with mask, and the command will be rejected if the result
558 * doesn't match value.
560 * Registers with non-zero mask are only allowed to be written using
563 struct drm_i915_reg_descriptor {
569 /* Convenience macro for adding 32-bit registers. */
570 #define REG32(_reg, ...) \
571 { .addr = (_reg), __VA_ARGS__ }
573 #define REG32_IDX(_reg, idx) \
574 { .addr = _reg(idx) }
577 * Convenience macro for adding 64-bit registers.
579 * Some registers that userspace accesses are 64 bits. The register
580 * access commands only allow 32-bit accesses. Hence, we have to include
581 * entries for both halves of the 64-bit registers.
583 #define REG64(_reg) \
585 { .addr = _reg ## _UDW }
587 #define REG64_IDX(_reg, idx) \
588 { .addr = _reg(idx) }, \
589 { .addr = _reg ## _UDW(idx) }
591 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
592 REG64(GPGPU_THREADS_DISPATCHED),
593 REG64(HS_INVOCATION_COUNT),
594 REG64(DS_INVOCATION_COUNT),
595 REG64(IA_VERTICES_COUNT),
596 REG64(IA_PRIMITIVES_COUNT),
597 REG64(VS_INVOCATION_COUNT),
598 REG64(GS_INVOCATION_COUNT),
599 REG64(GS_PRIMITIVES_COUNT),
600 REG64(CL_INVOCATION_COUNT),
601 REG64(CL_PRIMITIVES_COUNT),
602 REG64(PS_INVOCATION_COUNT),
603 REG64(PS_DEPTH_COUNT),
604 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
605 REG64(MI_PREDICATE_SRC0),
606 REG64(MI_PREDICATE_SRC1),
607 REG32(GEN7_3DPRIM_END_OFFSET),
608 REG32(GEN7_3DPRIM_START_VERTEX),
609 REG32(GEN7_3DPRIM_VERTEX_COUNT),
610 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
611 REG32(GEN7_3DPRIM_START_INSTANCE),
612 REG32(GEN7_3DPRIM_BASE_VERTEX),
613 REG32(GEN7_GPGPU_DISPATCHDIMX),
614 REG32(GEN7_GPGPU_DISPATCHDIMY),
615 REG32(GEN7_GPGPU_DISPATCHDIMZ),
616 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
617 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
618 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
619 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
620 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
621 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
622 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
623 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
624 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
625 REG32(GEN7_SO_WRITE_OFFSET(0)),
626 REG32(GEN7_SO_WRITE_OFFSET(1)),
627 REG32(GEN7_SO_WRITE_OFFSET(2)),
628 REG32(GEN7_SO_WRITE_OFFSET(3)),
629 REG32(GEN7_L3SQCREG1),
630 REG32(GEN7_L3CNTLREG2),
631 REG32(GEN7_L3CNTLREG3),
632 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
635 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
636 REG64_IDX(HSW_CS_GPR, 0),
637 REG64_IDX(HSW_CS_GPR, 1),
638 REG64_IDX(HSW_CS_GPR, 2),
639 REG64_IDX(HSW_CS_GPR, 3),
640 REG64_IDX(HSW_CS_GPR, 4),
641 REG64_IDX(HSW_CS_GPR, 5),
642 REG64_IDX(HSW_CS_GPR, 6),
643 REG64_IDX(HSW_CS_GPR, 7),
644 REG64_IDX(HSW_CS_GPR, 8),
645 REG64_IDX(HSW_CS_GPR, 9),
646 REG64_IDX(HSW_CS_GPR, 10),
647 REG64_IDX(HSW_CS_GPR, 11),
648 REG64_IDX(HSW_CS_GPR, 12),
649 REG64_IDX(HSW_CS_GPR, 13),
650 REG64_IDX(HSW_CS_GPR, 14),
651 REG64_IDX(HSW_CS_GPR, 15),
653 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
655 REG32(HSW_ROW_CHICKEN3,
656 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
657 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
661 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
662 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
663 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
665 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
668 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
669 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
670 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
672 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
673 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
674 REG64_IDX(BCS_GPR, 0),
675 REG64_IDX(BCS_GPR, 1),
676 REG64_IDX(BCS_GPR, 2),
677 REG64_IDX(BCS_GPR, 3),
678 REG64_IDX(BCS_GPR, 4),
679 REG64_IDX(BCS_GPR, 5),
680 REG64_IDX(BCS_GPR, 6),
681 REG64_IDX(BCS_GPR, 7),
682 REG64_IDX(BCS_GPR, 8),
683 REG64_IDX(BCS_GPR, 9),
684 REG64_IDX(BCS_GPR, 10),
685 REG64_IDX(BCS_GPR, 11),
686 REG64_IDX(BCS_GPR, 12),
687 REG64_IDX(BCS_GPR, 13),
688 REG64_IDX(BCS_GPR, 14),
689 REG64_IDX(BCS_GPR, 15),
695 struct drm_i915_reg_table {
696 const struct drm_i915_reg_descriptor *regs;
700 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
701 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
704 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
705 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
708 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
709 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
710 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) },
713 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
714 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
717 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = {
718 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) },
721 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
723 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
725 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
727 if (client == INSTR_MI_CLIENT)
729 else if (client == INSTR_RC_CLIENT) {
730 if (subclient == INSTR_MEDIA_SUBCLIENT)
736 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
740 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
742 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
744 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
745 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
747 if (client == INSTR_MI_CLIENT)
749 else if (client == INSTR_RC_CLIENT) {
750 if (subclient == INSTR_MEDIA_SUBCLIENT) {
759 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
763 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
765 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
767 if (client == INSTR_MI_CLIENT)
769 else if (client == INSTR_BC_CLIENT)
772 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
776 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)
778 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
780 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT)
783 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
787 static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
788 const struct drm_i915_cmd_table *cmd_tables,
794 if (!cmd_tables || cmd_table_count == 0)
797 for (i = 0; i < cmd_table_count; i++) {
798 const struct drm_i915_cmd_table *table = &cmd_tables[i];
802 for (j = 0; j < table->count; j++) {
803 const struct drm_i915_cmd_descriptor *desc =
805 u32 curr = desc->cmd.value & desc->cmd.mask;
807 if (curr < previous) {
808 DRM_ERROR("CMD: %s [%d] command table not sorted: "
809 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
810 engine->name, engine->id,
811 i, j, curr, previous);
822 static bool check_sorted(const struct intel_engine_cs *engine,
823 const struct drm_i915_reg_descriptor *reg_table,
830 for (i = 0; i < reg_count; i++) {
831 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
833 if (curr < previous) {
834 DRM_ERROR("CMD: %s [%d] register table not sorted: "
835 "entry=%d reg=0x%08X prev=0x%08X\n",
836 engine->name, engine->id,
847 static bool validate_regs_sorted(struct intel_engine_cs *engine)
850 const struct drm_i915_reg_table *table;
852 for (i = 0; i < engine->reg_table_count; i++) {
853 table = &engine->reg_tables[i];
854 if (!check_sorted(engine, table->regs, table->num_regs))
862 const struct drm_i915_cmd_descriptor *desc;
863 struct hlist_node node;
867 * Different command ranges have different numbers of bits for the opcode. For
868 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
869 * problem is that, for example, MI commands use bits 22:16 for other fields
870 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
871 * we mask a command from a batch it could hash to the wrong bucket due to
872 * non-opcode bits being set. But if we don't include those bits, some 3D
873 * commands may hash to the same bucket due to not including opcode bits that
874 * make the command unique. For now, we will risk hashing to the same bucket.
876 static inline u32 cmd_header_key(u32 x)
878 switch (x >> INSTR_CLIENT_SHIFT) {
880 case INSTR_MI_CLIENT:
881 return x >> STD_MI_OPCODE_SHIFT;
882 case INSTR_RC_CLIENT:
883 return x >> STD_3D_OPCODE_SHIFT;
884 case INSTR_BC_CLIENT:
885 return x >> STD_2D_OPCODE_SHIFT;
889 static int init_hash_table(struct intel_engine_cs *engine,
890 const struct drm_i915_cmd_table *cmd_tables,
895 hash_init(engine->cmd_hash);
897 for (i = 0; i < cmd_table_count; i++) {
898 const struct drm_i915_cmd_table *table = &cmd_tables[i];
900 for (j = 0; j < table->count; j++) {
901 const struct drm_i915_cmd_descriptor *desc =
903 struct cmd_node *desc_node =
904 kmalloc(sizeof(*desc_node), GFP_KERNEL);
909 desc_node->desc = desc;
910 hash_add(engine->cmd_hash, &desc_node->node,
911 cmd_header_key(desc->cmd.value));
918 static void fini_hash_table(struct intel_engine_cs *engine)
920 struct hlist_node *tmp;
921 struct cmd_node *desc_node;
924 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
925 hash_del(&desc_node->node);
931 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
932 * @engine: the engine to initialize
934 * Optionally initializes fields related to batch buffer command parsing in the
935 * struct intel_engine_cs based on whether the platform requires software
938 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
940 const struct drm_i915_cmd_table *cmd_tables;
944 if (!IS_GEN7(engine->i915) && !(IS_GEN9(engine->i915) &&
948 switch (engine->id) {
950 if (IS_HASWELL(engine->i915)) {
951 cmd_tables = hsw_render_ring_cmd_table;
953 ARRAY_SIZE(hsw_render_ring_cmd_table);
955 cmd_tables = gen7_render_cmd_table;
956 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
959 if (IS_HASWELL(engine->i915)) {
960 engine->reg_tables = hsw_render_reg_tables;
961 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
963 engine->reg_tables = ivb_render_reg_tables;
964 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
966 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
969 cmd_tables = gen7_video_cmd_table;
970 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
971 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
974 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
975 if (IS_GEN9(engine->i915)) {
976 cmd_tables = gen9_blt_cmd_table;
977 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
978 engine->get_cmd_length_mask =
979 gen9_blt_get_cmd_length_mask;
981 /* BCS Engine unsafe without parser */
982 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
983 } else if (IS_HASWELL(engine->i915)) {
984 cmd_tables = hsw_blt_ring_cmd_table;
985 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
987 cmd_tables = gen7_blt_cmd_table;
988 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
991 if (IS_GEN9(engine->i915)) {
992 engine->reg_tables = gen9_blt_reg_tables;
993 engine->reg_table_count =
994 ARRAY_SIZE(gen9_blt_reg_tables);
995 } else if (IS_HASWELL(engine->i915)) {
996 engine->reg_tables = hsw_blt_reg_tables;
997 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
999 engine->reg_tables = ivb_blt_reg_tables;
1000 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
1004 cmd_tables = hsw_vebox_cmd_table;
1005 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
1006 /* VECS can use the same length_mask function as VCS */
1007 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
1010 MISSING_CASE(engine->id);
1014 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
1015 DRM_ERROR("%s: command descriptions are not sorted\n",
1019 if (!validate_regs_sorted(engine)) {
1020 DRM_ERROR("%s: registers are not sorted\n", engine->name);
1024 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
1026 DRM_ERROR("%s: initialised failed!\n", engine->name);
1027 fini_hash_table(engine);
1031 engine->flags |= I915_ENGINE_USING_CMD_PARSER;
1035 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1036 * @engine: the engine to clean up
1038 * Releases any resources related to command parsing that may have been
1039 * initialized for the specified engine.
1041 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
1043 if (!intel_engine_using_cmd_parser(engine))
1046 fini_hash_table(engine);
1049 static const struct drm_i915_cmd_descriptor*
1050 find_cmd_in_table(struct intel_engine_cs *engine,
1053 struct cmd_node *desc_node;
1055 hash_for_each_possible(engine->cmd_hash, desc_node, node,
1056 cmd_header_key(cmd_header)) {
1057 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
1058 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1066 * Returns a pointer to a descriptor for the command specified by cmd_header.
1068 * The caller must supply space for a default descriptor via the default_desc
1069 * parameter. If no descriptor for the specified command exists in the engine's
1070 * command parser tables, this function fills in default_desc based on the
1071 * engine's default length encoding and returns default_desc.
1073 static const struct drm_i915_cmd_descriptor*
1074 find_cmd(struct intel_engine_cs *engine,
1076 const struct drm_i915_cmd_descriptor *desc,
1077 struct drm_i915_cmd_descriptor *default_desc)
1081 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1084 desc = find_cmd_in_table(engine, cmd_header);
1088 mask = engine->get_cmd_length_mask(cmd_header);
1092 default_desc->cmd.value = cmd_header;
1093 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1094 default_desc->length.mask = mask;
1095 default_desc->flags = CMD_DESC_SKIP;
1096 return default_desc;
1099 static const struct drm_i915_reg_descriptor *
1100 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1102 int start = 0, end = count;
1103 while (start < end) {
1104 int mid = start + (end - start) / 2;
1105 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1116 static const struct drm_i915_reg_descriptor *
1117 find_reg(const struct intel_engine_cs *engine, u32 addr)
1119 const struct drm_i915_reg_table *table = engine->reg_tables;
1120 const struct drm_i915_reg_descriptor *reg = NULL;
1121 int count = engine->reg_table_count;
1123 for (; !reg && (count > 0); ++table, --count)
1124 reg = __find_reg(table->regs, table->num_regs, addr);
1129 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1130 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1131 struct drm_i915_gem_object *src_obj,
1132 u32 batch_start_offset,
1134 bool *needs_clflush_after)
1136 unsigned int src_needs_clflush;
1137 unsigned int dst_needs_clflush;
1141 ret = i915_gem_obj_prepare_shmem_read(src_obj, &src_needs_clflush);
1143 return ERR_PTR(ret);
1145 ret = i915_gem_obj_prepare_shmem_write(dst_obj, &dst_needs_clflush);
1151 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);
1155 src = ERR_PTR(-ENODEV);
1156 if (src_needs_clflush &&
1157 i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {
1158 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1160 i915_memcpy_from_wc(dst,
1161 src + batch_start_offset,
1162 ALIGN(batch_len, 16));
1163 i915_gem_object_unpin_map(src_obj);
1170 offset = offset_in_page(batch_start_offset);
1172 /* We can avoid clflushing partial cachelines before the write
1173 * if we only every write full cache-lines. Since we know that
1174 * both the source and destination are in multiples of
1175 * PAGE_SIZE, we can simply round up to the next cacheline.
1176 * We don't care about copying too much here as we only
1177 * validate up to the end of the batch.
1179 if (dst_needs_clflush & CLFLUSH_BEFORE)
1180 batch_len = roundup(batch_len,
1181 boot_cpu_data.x86_clflush_size);
1184 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) {
1185 int len = min_t(int, batch_len, PAGE_SIZE - offset);
1187 src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1188 if (src_needs_clflush)
1189 drm_clflush_virt_range(src + offset, len);
1190 memcpy(ptr, src + offset, len);
1199 /* dst_obj is returned with vmap pinned */
1200 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1203 i915_gem_obj_finish_shmem_access(dst_obj);
1205 i915_gem_obj_finish_shmem_access(src_obj);
1209 static bool check_cmd(const struct intel_engine_cs *engine,
1210 const struct drm_i915_cmd_descriptor *desc,
1211 const u32 *cmd, u32 length)
1213 if (desc->flags & CMD_DESC_SKIP)
1216 if (desc->flags & CMD_DESC_REJECT) {
1217 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1221 if (desc->flags & CMD_DESC_REGISTER) {
1223 * Get the distance between individual register offset
1224 * fields if the command can perform more than one
1227 const u32 step = desc->reg.step ? desc->reg.step : length;
1230 for (offset = desc->reg.offset; offset < length;
1232 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1233 const struct drm_i915_reg_descriptor *reg =
1234 find_reg(engine, reg_addr);
1237 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1238 reg_addr, *cmd, engine->name);
1243 * Check the value written to the register against the
1244 * allowed mask/value pair given in the whitelist entry.
1247 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1248 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1253 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1254 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
1259 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1260 (offset + 2 > length ||
1261 (cmd[offset + 1] & reg->mask) != reg->value)) {
1262 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1270 if (desc->flags & CMD_DESC_BITMASK) {
1273 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1276 if (desc->bits[i].mask == 0)
1279 if (desc->bits[i].condition_mask != 0) {
1281 desc->bits[i].condition_offset;
1282 u32 condition = cmd[offset] &
1283 desc->bits[i].condition_mask;
1289 if (desc->bits[i].offset >= length) {
1290 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1291 *cmd, engine->name);
1295 dword = cmd[desc->bits[i].offset] &
1298 if (dword != desc->bits[i].expected) {
1299 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1302 desc->bits[i].expected,
1303 dword, engine->name);
1312 static int check_bbstart(const struct i915_gem_context *ctx,
1313 u32 *cmd, u32 offset, u32 length,
1316 u64 shadow_batch_start)
1318 u64 jump_offset, jump_target;
1319 u32 target_cmd_offset, target_cmd_index;
1321 /* For igt compatibility on older platforms */
1322 if (CMDPARSER_USES_GGTT(ctx->i915)) {
1323 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n");
1328 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n",
1333 jump_target = *(u64*)(cmd+1);
1334 jump_offset = jump_target - batch_start;
1337 * Any underflow of jump_target is guaranteed to be outside the range
1338 * of a u32, so >= test catches both too large and too small
1340 if (jump_offset >= batch_len) {
1341 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n",
1347 * This cannot overflow a u32 because we already checked jump_offset
1348 * is within the BB, and the batch_len is a u32
1350 target_cmd_offset = lower_32_bits(jump_offset);
1351 target_cmd_index = target_cmd_offset / sizeof(u32);
1353 *(u64*)(cmd + 1) = shadow_batch_start + target_cmd_offset;
1355 if (target_cmd_index == offset)
1358 if (ctx->jump_whitelist_cmds <= target_cmd_index) {
1359 DRM_DEBUG("CMD: Rejecting BB_START - truncated whitelist array\n");
1361 } else if (!test_bit(target_cmd_index, ctx->jump_whitelist)) {
1362 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1370 static void init_whitelist(struct i915_gem_context *ctx, u32 batch_len)
1372 const u32 batch_cmds = DIV_ROUND_UP(batch_len, sizeof(u32));
1373 const u32 exact_size = BITS_TO_LONGS(batch_cmds);
1374 u32 next_size = BITS_TO_LONGS(roundup_pow_of_two(batch_cmds));
1375 unsigned long *next_whitelist;
1377 if (CMDPARSER_USES_GGTT(ctx->i915))
1380 if (batch_cmds <= ctx->jump_whitelist_cmds) {
1381 bitmap_zero(ctx->jump_whitelist, batch_cmds);
1386 next_whitelist = kcalloc(next_size, sizeof(long), GFP_KERNEL);
1387 if (next_whitelist) {
1388 kfree(ctx->jump_whitelist);
1389 ctx->jump_whitelist = next_whitelist;
1390 ctx->jump_whitelist_cmds =
1391 next_size * BITS_PER_BYTE * sizeof(long);
1395 if (next_size > exact_size) {
1396 next_size = exact_size;
1400 DRM_DEBUG("CMD: Failed to extend whitelist. BB_START may be disallowed\n");
1401 bitmap_zero(ctx->jump_whitelist, ctx->jump_whitelist_cmds);
1406 #define LENGTH_BIAS 2
1409 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1410 * @ctx: the context in which the batch is to execute
1411 * @engine: the engine on which the batch is to execute
1412 * @batch_obj: the batch buffer in question
1413 * @batch_start: Canonical base address of batch
1414 * @batch_start_offset: byte offset in the batch at which execution starts
1415 * @batch_len: length of the commands in batch_obj
1416 * @shadow_batch_obj: copy of the batch buffer in question
1417 * @shadow_batch_start: Canonical base address of shadow_batch_obj
1419 * Parses the specified batch buffer looking for privilege violations as
1420 * described in the overview.
1422 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1423 * if the batch appears legal but should use hardware parsing
1426 int intel_engine_cmd_parser(struct i915_gem_context *ctx,
1427 struct intel_engine_cs *engine,
1428 struct drm_i915_gem_object *batch_obj,
1430 u32 batch_start_offset,
1432 struct drm_i915_gem_object *shadow_batch_obj,
1433 u64 shadow_batch_start)
1435 u32 *cmd, *batch_end, offset = 0;
1436 struct drm_i915_cmd_descriptor default_desc = noop_desc;
1437 const struct drm_i915_cmd_descriptor *desc = &default_desc;
1438 bool needs_clflush_after = false;
1441 cmd = copy_batch(shadow_batch_obj, batch_obj,
1442 batch_start_offset, batch_len,
1443 &needs_clflush_after);
1445 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1446 return PTR_ERR(cmd);
1449 init_whitelist(ctx, batch_len);
1452 * We use the batch length as size because the shadow object is as
1453 * large or larger and copy_batch() will write MI_NOPs to the extra
1454 * space. Parsing should be faster in some cases this way.
1456 batch_end = cmd + (batch_len / sizeof(*batch_end));
1460 if (*cmd == MI_BATCH_BUFFER_END)
1463 desc = find_cmd(engine, *cmd, desc, &default_desc);
1465 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1471 if (desc->flags & CMD_DESC_FIXED)
1472 length = desc->length.fixed;
1474 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1476 if ((batch_end - cmd) < length) {
1477 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1485 if (!check_cmd(engine, desc, cmd, length)) {
1490 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1491 ret = check_bbstart(ctx, cmd, offset, length,
1492 batch_len, batch_start,
1493 shadow_batch_start);
1500 if (ctx->jump_whitelist_cmds > offset)
1501 set_bit(offset, ctx->jump_whitelist);
1505 if (cmd >= batch_end) {
1506 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1512 if (needs_clflush_after) {
1513 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);
1515 drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr);
1519 i915_gem_object_unpin_map(shadow_batch_obj);
1524 * i915_cmd_parser_get_version() - get the cmd parser version number
1525 * @dev_priv: i915 device private
1527 * The cmd parser maintains a simple increasing integer version number suitable
1528 * for passing to userspace clients to determine what operations are permitted.
1530 * Return: the current version number of the cmd parser
1532 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1534 struct intel_engine_cs *engine;
1535 enum intel_engine_id id;
1536 bool active = false;
1538 /* If the command parser is not enabled, report 0 - unsupported */
1539 for_each_engine(engine, dev_priv, id) {
1540 if (intel_engine_using_cmd_parser(engine)) {
1549 * Command parser version history
1551 * 1. Initial version. Checks batches and reports violations, but leaves
1552 * hardware parsing enabled (so does not allow new use cases).
1553 * 2. Allow access to the MI_PREDICATE_SRC0 and
1554 * MI_PREDICATE_SRC1 registers.
1555 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1556 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1557 * 5. GPGPU dispatch compute indirect registers.
1558 * 6. TIMESTAMP register and Haswell CS GPR registers
1559 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1560 * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1561 * rely on the HW to NOOP disallowed commands as it would without
1562 * the parser enabled.
1563 * 9. Don't whitelist or handle oacontrol specially, as ownership
1564 * for oacontrol state is moving to i915-perf.
1565 * 10. Support for Gen9 BCS Parsing