1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2012 Lantiq GmbH
8 #include <linux/interrupt.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
15 #include <lantiq_soc.h>
18 /* the magic ID byte of the core */
19 #define GPTU_MAGIC 0x59
20 /* clock control register */
24 /* interrupt node enable */
25 #define GPTU_IRNEN 0xf4
26 /* interrupt control register */
27 #define GPTU_IRCR 0xf8
28 /* interrupt capture register */
29 #define GPTU_IRNCR 0xfc
30 /* there are 3 identical blocks of 2 timers. calculate register offsets */
31 #define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
32 #define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
33 /* timer control register */
34 #define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
35 /* timer auto reload register */
36 #define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
37 /* timer manual reload register */
38 #define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
39 /* timer count register */
40 #define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
43 #define CON_CNT BIT(2)
44 #define CON_EDGE_ANY (BIT(7) | BIT(6))
45 #define CON_SYNC BIT(8)
46 #define CON_CLK_INT BIT(10)
49 #define RUN_SEN BIT(0)
52 /* set clock to runmode */
53 #define CLC_RMC BIT(8)
54 /* bring core out of suspend */
55 #define CLC_SUSPEND BIT(4)
57 #define CLC_DISABLE BIT(0)
59 #define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y))
60 #define gptu_r32(x) ltq_r32(gptu_membase + (x))
71 static void __iomem *gptu_membase;
72 static struct resource irqres[6];
74 static irqreturn_t timer_irq_handler(int irq, void *priv)
76 int timer = irq - irqres[0].start;
77 gptu_w32(1 << timer, GPTU_IRNCR);
81 static void gptu_hwinit(void)
83 gptu_w32(0x00, GPTU_IRNEN);
84 gptu_w32(0xff, GPTU_IRNCR);
85 gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
88 static void gptu_hwexit(void)
90 gptu_w32(0x00, GPTU_IRNEN);
91 gptu_w32(0xff, GPTU_IRNCR);
92 gptu_w32(CLC_DISABLE, GPTU_CLC);
95 static int gptu_enable(struct clk *clk)
97 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
98 IRQF_TIMER, "gtpu", NULL);
100 pr_err("gptu: failed to request irq\n");
104 gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
105 GPTU_CON(clk->bits));
106 gptu_w32(1, GPTU_RLD(clk->bits));
107 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
108 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
112 static void gptu_disable(struct clk *clk)
114 gptu_w32(0, GPTU_RUN(clk->bits));
115 gptu_w32(0, GPTU_CON(clk->bits));
116 gptu_w32(0, GPTU_RLD(clk->bits));
117 gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
118 free_irq(irqres[clk->bits].start, NULL);
121 static inline void clkdev_add_gptu(struct device *dev, const char *con,
124 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
128 clk->cl.dev_id = dev_name(dev);
129 clk->cl.con_id = con;
131 clk->enable = gptu_enable;
132 clk->disable = gptu_disable;
134 clkdev_add(&clk->cl);
137 static int gptu_probe(struct platform_device *pdev)
141 if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
142 dev_err(&pdev->dev, "Failed to get IRQ list\n");
146 /* remap gptu register range */
147 gptu_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
148 if (IS_ERR(gptu_membase))
149 return PTR_ERR(gptu_membase);
151 /* enable our clock */
152 clk = clk_get(&pdev->dev, NULL);
154 dev_err(&pdev->dev, "Failed to get clock\n");
159 /* power up the core */
162 /* the gptu has a ID register */
163 if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
164 dev_err(&pdev->dev, "Failed to find magic\n");
171 /* register the clocks */
172 clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
173 clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
174 clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
175 clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
176 clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
177 clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
179 dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
184 static const struct of_device_id gptu_match[] = {
185 { .compatible = "lantiq,gptu-xway" },
189 static struct platform_driver dma_driver = {
193 .of_match_table = gptu_match,
197 int __init gptu_init(void)
199 int ret = platform_driver_register(&dma_driver);
202 pr_info("gptu: Error registering platform driver\n");
206 arch_initcall(gptu_init);