2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008 Intel Corporation
7 #include <linux/string.h>
8 #include <linux/bitops.h>
12 #include "i915_gem_ioctls.h"
13 #include "i915_gem_mman.h"
14 #include "i915_gem_object.h"
17 * DOC: buffer object tiling
19 * i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
20 * interface to declare fence register requirements.
22 * In principle GEM doesn't care at all about the internal data layout of an
23 * object, and hence it also doesn't care about tiling or swizzling. There's two
26 * - For X and Y tiling the hardware provides detilers for CPU access, so called
27 * fences. Since there's only a limited amount of them the kernel must manage
28 * these, and therefore userspace must tell the kernel the object tiling if it
29 * wants to use fences for detiling.
30 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
31 * depends upon the physical page frame number. When swapping such objects the
32 * page frame number might change and the kernel must be able to fix this up
33 * and hence now the tiling. Note that on a subset of platforms with
34 * asymmetric memory channel population the swizzling pattern changes in an
35 * unknown way, and for those the kernel simply forbids swapping completely.
37 * Since neither of this applies for new tiling layouts on modern platforms like
38 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
39 * Anything else can be handled in userspace entirely without the kernel's
44 * i915_gem_fence_size - required global GTT size for a fence
47 * @tiling: tiling mode
48 * @stride: tiling stride
50 * Return the required global GTT size for a fence (view of a tiled object),
51 * taking into account potential fence register mapping.
53 u32 i915_gem_fence_size(struct drm_i915_private *i915,
54 u32 size, unsigned int tiling, unsigned int stride)
60 if (tiling == I915_TILING_NONE)
65 if (INTEL_GEN(i915) >= 4) {
66 stride *= i915_gem_tile_height(tiling);
67 GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
68 return roundup(size, stride);
71 /* Previous chips need a power-of-two fence region when tiling */
73 ggtt_size = 1024*1024;
77 while (ggtt_size < size)
84 * i915_gem_fence_alignment - required global GTT alignment for a fence
87 * @tiling: tiling mode
88 * @stride: tiling stride
90 * Return the required global GTT alignment for a fence (a view of a tiled
91 * object), taking into account potential fence register mapping.
93 u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
94 unsigned int tiling, unsigned int stride)
99 * Minimum alignment is 4k (GTT page size), but might be greater
100 * if a fence register is needed for the object.
102 if (tiling == I915_TILING_NONE)
103 return I915_GTT_MIN_ALIGNMENT;
105 if (INTEL_GEN(i915) >= 4)
106 return I965_FENCE_PAGE;
109 * Previous chips need to be aligned to the size of the smallest
110 * fence register that can contain the object.
112 return i915_gem_fence_size(i915, size, tiling, stride);
115 /* Check pitch constriants for all chips & tiling formats */
117 i915_tiling_ok(struct drm_i915_gem_object *obj,
118 unsigned int tiling, unsigned int stride)
120 struct drm_i915_private *i915 = to_i915(obj->base.dev);
121 unsigned int tile_width;
123 /* Linear is always fine */
124 if (tiling == I915_TILING_NONE)
127 if (tiling > I915_TILING_LAST)
130 /* check maximum stride & object size */
131 /* i965+ stores the end address of the gtt mapping in the fence
132 * reg, so dont bother to check the size */
133 if (INTEL_GEN(i915) >= 7) {
134 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
136 } else if (INTEL_GEN(i915) >= 4) {
137 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
143 if (!is_power_of_2(stride))
147 if (IS_GEN(i915, 2) ||
148 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
153 if (!stride || !IS_ALIGNED(stride, tile_width))
159 static bool i915_vma_fence_prepare(struct i915_vma *vma,
160 int tiling_mode, unsigned int stride)
162 struct drm_i915_private *i915 = vma->vm->i915;
165 if (!i915_vma_is_map_and_fenceable(vma))
168 size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
169 if (vma->node.size < size)
172 alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
173 if (!IS_ALIGNED(vma->node.start, alignment))
179 /* Make the current GTT allocation valid for the change in tiling. */
181 i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
182 int tiling_mode, unsigned int stride)
184 struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
185 struct i915_vma *vma, *vn;
189 if (tiling_mode == I915_TILING_NONE)
192 mutex_lock(&ggtt->vm.mutex);
194 spin_lock(&obj->vma.lock);
195 for_each_ggtt_vma(vma, obj) {
196 GEM_BUG_ON(vma->vm != &ggtt->vm);
198 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
201 list_move(&vma->vm_link, &unbind);
203 spin_unlock(&obj->vma.lock);
205 list_for_each_entry_safe(vma, vn, &unbind, vm_link) {
206 ret = __i915_vma_unbind(vma);
208 /* Restore the remaining vma on an error */
209 list_splice(&unbind, &ggtt->vm.bound_list);
214 mutex_unlock(&ggtt->vm.mutex);
220 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
221 unsigned int tiling, unsigned int stride)
223 struct drm_i915_private *i915 = to_i915(obj->base.dev);
224 struct i915_vma *vma;
227 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
228 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
230 GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
231 GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
233 if ((tiling | stride) == obj->tiling_and_stride)
236 if (i915_gem_object_is_framebuffer(obj))
239 /* We need to rebind the object if its current allocation
240 * no longer meets the alignment restrictions for its new
241 * tiling mode. Otherwise we can just leave it alone, but
242 * need to ensure that any fence register is updated before
243 * the next fenced (either through the GTT or by the BLT unit
244 * on older GPUs) access.
246 * After updating the tiling parameters, we then flag whether
247 * we need to update an associated fence register. Note this
248 * has to also include the unfenced register the GPU uses
249 * whilst executing a fenced command for an untiled object.
252 i915_gem_object_lock(obj, NULL);
253 if (i915_gem_object_is_framebuffer(obj)) {
254 i915_gem_object_unlock(obj);
258 err = i915_gem_object_fence_prepare(obj, tiling, stride);
260 i915_gem_object_unlock(obj);
264 /* If the memory has unknown (i.e. varying) swizzling, we pin the
265 * pages to prevent them being swapped out and causing corruption
266 * due to the change in swizzling.
268 mutex_lock(&obj->mm.lock);
269 if (i915_gem_object_has_pages(obj) &&
270 obj->mm.madv == I915_MADV_WILLNEED &&
271 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
272 if (tiling == I915_TILING_NONE) {
273 GEM_BUG_ON(!obj->mm.quirked);
274 __i915_gem_object_unpin_pages(obj);
275 obj->mm.quirked = false;
277 if (!i915_gem_object_is_tiled(obj)) {
278 GEM_BUG_ON(obj->mm.quirked);
279 __i915_gem_object_pin_pages(obj);
280 obj->mm.quirked = true;
283 mutex_unlock(&obj->mm.lock);
285 spin_lock(&obj->vma.lock);
286 for_each_ggtt_vma(vma, obj) {
288 i915_gem_fence_size(i915, vma->size, tiling, stride);
289 vma->fence_alignment =
290 i915_gem_fence_alignment(i915,
291 vma->size, tiling, stride);
294 vma->fence->dirty = true;
296 spin_unlock(&obj->vma.lock);
298 obj->tiling_and_stride = tiling | stride;
300 /* Try to preallocate memory required to save swizzling on put-pages */
301 if (i915_gem_object_needs_bit17_swizzle(obj)) {
303 obj->bit_17 = bitmap_zalloc(obj->base.size >> PAGE_SHIFT,
307 bitmap_free(obj->bit_17);
311 i915_gem_object_unlock(obj);
313 /* Force the fence to be reacquired for GTT access */
314 i915_gem_object_release_mmap_gtt(obj);
320 * i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
322 * @data: data pointer for the ioctl
323 * @file: DRM file for the ioctl call
325 * Sets the tiling mode of an object, returning the required swizzling of
326 * bit 6 of addresses in the object.
328 * Called by the user via ioctl.
331 * Zero on success, negative errno on failure.
334 i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
335 struct drm_file *file)
337 struct drm_i915_private *dev_priv = to_i915(dev);
338 struct drm_i915_gem_set_tiling *args = data;
339 struct drm_i915_gem_object *obj;
342 if (!dev_priv->ggtt.num_fences)
345 obj = i915_gem_object_lookup(file, args->handle);
350 * The tiling mode of proxy objects is handled by its generator, and
351 * not allowed to be changed by userspace.
353 if (i915_gem_object_is_proxy(obj)) {
358 if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
363 if (args->tiling_mode == I915_TILING_NONE) {
364 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
367 if (args->tiling_mode == I915_TILING_X)
368 args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_x;
370 args->swizzle_mode = to_i915(dev)->ggtt.bit_6_swizzle_y;
372 /* Hide bit 17 swizzling from the user. This prevents old Mesa
373 * from aborting the application on sw fallbacks to bit 17,
374 * and we use the pread/pwrite bit17 paths to swizzle for it.
375 * If there was a user that was relying on the swizzle
376 * information for drm_intel_bo_map()ed reads/writes this would
377 * break it, but we don't have any of those.
379 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
380 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
381 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
382 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
384 /* If we can't handle the swizzling, make it untiled. */
385 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
386 args->tiling_mode = I915_TILING_NONE;
387 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
392 err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
394 /* We have to maintain this existing ABI... */
395 args->stride = i915_gem_object_get_stride(obj);
396 args->tiling_mode = i915_gem_object_get_tiling(obj);
399 i915_gem_object_put(obj);
404 * i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
406 * @data: data pointer for the ioctl
407 * @file: DRM file for the ioctl call
409 * Returns the current tiling mode and required bit 6 swizzling for the object.
411 * Called by the user via ioctl.
414 * Zero on success, negative errno on failure.
417 i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
418 struct drm_file *file)
420 struct drm_i915_gem_get_tiling *args = data;
421 struct drm_i915_private *dev_priv = to_i915(dev);
422 struct drm_i915_gem_object *obj;
425 if (!dev_priv->ggtt.num_fences)
429 obj = i915_gem_object_lookup_rcu(file, args->handle);
432 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
439 switch (args->tiling_mode) {
441 args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
444 args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
447 case I915_TILING_NONE:
448 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
452 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
453 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
454 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
456 args->phys_swizzle_mode = args->swizzle_mode;
457 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
458 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
459 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
460 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;