gem/i915_gem_domain.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2016 Intel Corporation
   5  */
   6
   7 #include "display/intel_frontbuffer.h"
   8
   9 #include "i915_drv.h"
  10 #include "i915_gem_clflush.h"
  11 #include "i915_gem_gtt.h"
  12 #include "i915_gem_ioctls.h"
  13 #include "i915_gem_object.h"
  14 #include "i915_vma.h"
  15 #include "i915_gem_lmem.h"
  16 #include "i915_gem_mman.h"
  17
  18 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
  19 {
  20         /*
  21          * We manually flush the CPU domain so that we can override and
  22          * force the flush for the display, and perform it asyncrhonously.
  23          */
  24         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
  25         if (obj->cache_dirty)
  26                 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
  27         obj->write_domain = 0;
  28 }
  29
  30 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
  31 {
  32         if (!i915_gem_object_is_framebuffer(obj))
  33                 return;
  34
  35         i915_gem_object_lock(obj, NULL);
  36         __i915_gem_object_flush_for_display(obj);
  37         i915_gem_object_unlock(obj);
  38 }
  39
  40 void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
  41 {
  42         if (i915_gem_object_is_framebuffer(obj))
  43                 __i915_gem_object_flush_for_display(obj);
  44 }
  45
  46 /**
  47  * Moves a single object to the WC read, and possibly write domain.
  48  * @obj: object to act on
  49  * @write: ask for write access or read only
  50  *
  51  * This function returns when the move is complete, including waiting on
  52  * flushes to occur.
  53  */
  54 int
  55 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
  56 {
  57         int ret;
  58
  59         assert_object_held(obj);
  60
  61         ret = i915_gem_object_wait(obj,
  62                                    I915_WAIT_INTERRUPTIBLE |
  63                                    (write ? I915_WAIT_ALL : 0),
  64                                    MAX_SCHEDULE_TIMEOUT);
  65         if (ret)
  66                 return ret;
  67
  68         if (obj->write_domain == I915_GEM_DOMAIN_WC)
  69                 return 0;
  70
  71         /* Flush and acquire obj->pages so that we are coherent through
  72          * direct access in memory with previous cached writes through
  73          * shmemfs and that our cache domain tracking remains valid.
  74          * For example, if the obj->filp was moved to swap without us
  75          * being notified and releasing the pages, we would mistakenly
  76          * continue to assume that the obj remained out of the CPU cached
  77          * domain.
  78          */
  79         ret = i915_gem_object_pin_pages(obj);
  80         if (ret)
  81                 return ret;
  82
  83         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
  84
  85         /* Serialise direct access to this object with the barriers for
  86          * coherent writes from the GPU, by effectively invalidating the
  87          * WC domain upon first access.
  88          */
  89         if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0)
  90                 mb();
  91
  92         /* It should now be out of any other write domains, and we can update
  93          * the domain values for our changes.
  94          */
  95         GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0);
  96         obj->read_domains |= I915_GEM_DOMAIN_WC;
  97         if (write) {
  98                 obj->read_domains = I915_GEM_DOMAIN_WC;
  99                 obj->write_domain = I915_GEM_DOMAIN_WC;
 100                 obj->mm.dirty = true;
 101         }
 102
 103         i915_gem_object_unpin_pages(obj);
 104         return 0;
 105 }
 106
 107 /**
 108  * Moves a single object to the GTT read, and possibly write domain.
 109  * @obj: object to act on
 110  * @write: ask for write access or read only
 111  *
 112  * This function returns when the move is complete, including waiting on
 113  * flushes to occur.
 114  */
 115 int
 116 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
 117 {
 118         int ret;
 119
 120         assert_object_held(obj);
 121
 122         ret = i915_gem_object_wait(obj,
 123                                    I915_WAIT_INTERRUPTIBLE |
 124                                    (write ? I915_WAIT_ALL : 0),
 125                                    MAX_SCHEDULE_TIMEOUT);
 126         if (ret)
 127                 return ret;
 128
 129         if (obj->write_domain == I915_GEM_DOMAIN_GTT)
 130                 return 0;
 131
 132         /* Flush and acquire obj->pages so that we are coherent through
 133          * direct access in memory with previous cached writes through
 134          * shmemfs and that our cache domain tracking remains valid.
 135          * For example, if the obj->filp was moved to swap without us
 136          * being notified and releasing the pages, we would mistakenly
 137          * continue to assume that the obj remained out of the CPU cached
 138          * domain.
 139          */
 140         ret = i915_gem_object_pin_pages(obj);
 141         if (ret)
 142                 return ret;
 143
 144         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
 145
 146         /* Serialise direct access to this object with the barriers for
 147          * coherent writes from the GPU, by effectively invalidating the
 148          * GTT domain upon first access.
 149          */
 150         if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0)
 151                 mb();
 152
 153         /* It should now be out of any other write domains, and we can update
 154          * the domain values for our changes.
 155          */
 156         GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
 157         obj->read_domains |= I915_GEM_DOMAIN_GTT;
 158         if (write) {
 159                 struct i915_vma *vma;
 160
 161                 obj->read_domains = I915_GEM_DOMAIN_GTT;
 162                 obj->write_domain = I915_GEM_DOMAIN_GTT;
 163                 obj->mm.dirty = true;
 164
 165                 spin_lock(&obj->vma.lock);
 166                 for_each_ggtt_vma(vma, obj)
 167                         if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
 168                                 i915_vma_set_ggtt_write(vma);
 169                 spin_unlock(&obj->vma.lock);
 170         }
 171
 172         i915_gem_object_unpin_pages(obj);
 173         return 0;
 174 }
 175
 176 /**
 177  * Changes the cache-level of an object across all VMA.
 178  * @obj: object to act on
 179  * @cache_level: new cache level to set for the object
 180  *
 181  * After this function returns, the object will be in the new cache-level
 182  * across all GTT and the contents of the backing storage will be coherent,
 183  * with respect to the new cache-level. In order to keep the backing storage
 184  * coherent for all users, we only allow a single cache level to be set
 185  * globally on the object and prevent it from being changed whilst the
 186  * hardware is reading from the object. That is if the object is currently
 187  * on the scanout it will be set to uncached (or equivalent display
 188  * cache coherency) and all non-MOCS GPU access will also be uncached so
 189  * that all direct access to the scanout remains coherent.
 190  */
 191 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 192                                     enum i915_cache_level cache_level)
 193 {
 194         int ret;
 195
 196         if (obj->cache_level == cache_level)
 197                 return 0;
 198
 199         ret = i915_gem_object_wait(obj,
 200                                    I915_WAIT_INTERRUPTIBLE |
 201                                    I915_WAIT_ALL,
 202                                    MAX_SCHEDULE_TIMEOUT);
 203         if (ret)
 204                 return ret;
 205
 206         /* Always invalidate stale cachelines */
 207         if (obj->cache_level != cache_level) {
 208                 i915_gem_object_set_cache_coherency(obj, cache_level);
 209                 obj->cache_dirty = true;
 210         }
 211
 212         /* The cache-level will be applied when each vma is rebound. */
 213         return i915_gem_object_unbind(obj,
 214                                       I915_GEM_OBJECT_UNBIND_ACTIVE |
 215                                       I915_GEM_OBJECT_UNBIND_BARRIER);
 216 }
 217
 218 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
 219                                struct drm_file *file)
 220 {
 221         struct drm_i915_gem_caching *args = data;
 222         struct drm_i915_gem_object *obj;
 223         int err = 0;
 224
 225         rcu_read_lock();
 226         obj = i915_gem_object_lookup_rcu(file, args->handle);
 227         if (!obj) {
 228                 err = -ENOENT;
 229                 goto out;
 230         }
 231
 232         switch (obj->cache_level) {
 233         case I915_CACHE_LLC:
 234         case I915_CACHE_L3_LLC:
 235                 args->caching = I915_CACHING_CACHED;
 236                 break;
 237
 238         case I915_CACHE_WT:
 239                 args->caching = I915_CACHING_DISPLAY;
 240                 break;
 241
 242         default:
 243                 args->caching = I915_CACHING_NONE;
 244                 break;
 245         }
 246 out:
 247         rcu_read_unlock();
 248         return err;
 249 }
 250
 251 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 252                                struct drm_file *file)
 253 {
 254         struct drm_i915_private *i915 = to_i915(dev);
 255         struct drm_i915_gem_caching *args = data;
 256         struct drm_i915_gem_object *obj;
 257         enum i915_cache_level level;
 258         int ret = 0;
 259
 260         switch (args->caching) {
 261         case I915_CACHING_NONE:
 262                 level = I915_CACHE_NONE;
 263                 break;
 264         case I915_CACHING_CACHED:
 265                 /*
 266                  * Due to a HW issue on BXT A stepping, GPU stores via a
 267                  * snooped mapping may leave stale data in a corresponding CPU
 268                  * cacheline, whereas normally such cachelines would get
 269                  * invalidated.
 270                  */
 271                 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
 272                         return -ENODEV;
 273
 274                 level = I915_CACHE_LLC;
 275                 break;
 276         case I915_CACHING_DISPLAY:
 277                 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         obj = i915_gem_object_lookup(file, args->handle);
 284         if (!obj)
 285                 return -ENOENT;
 286
 287         /*
 288          * The caching mode of proxy object is handled by its generator, and
 289          * not allowed to be changed by userspace.
 290          */
 291         if (i915_gem_object_is_proxy(obj)) {
 292                 ret = -ENXIO;
 293                 goto out;
 294         }
 295
 296         ret = i915_gem_object_lock_interruptible(obj, NULL);
 297         if (ret)
 298                 goto out;
 299
 300         ret = i915_gem_object_set_cache_level(obj, level);
 301         i915_gem_object_unlock(obj);
 302
 303 out:
 304         i915_gem_object_put(obj);
 305         return ret;
 306 }
 307
 308 /*
 309  * Prepare buffer for display plane (scanout, cursors, etc). Can be called from
 310  * an uninterruptible phase (modesetting) and allows any flushes to be pipelined
 311  * (for pageflips). We only flush the caches while preparing the buffer for
 312  * display, the callers are responsible for frontbuffer flush.
 313  */
 314 struct i915_vma *
 315 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 316                                      u32 alignment,
 317                                      const struct i915_ggtt_view *view,
 318                                      unsigned int flags)
 319 {
 320         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 321         struct i915_gem_ww_ctx ww;
 322         struct i915_vma *vma;
 323         int ret;
 324
 325         /* Frame buffer must be in LMEM (no migration yet) */
 326         if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
 327                 return ERR_PTR(-EINVAL);
 328
 329         i915_gem_ww_ctx_init(&ww, true);
 330 retry:
 331         ret = i915_gem_object_lock(obj, &ww);
 332         if (ret)
 333                 goto err;
 334         /*
 335          * The display engine is not coherent with the LLC cache on gen6.  As
 336          * a result, we make sure that the pinning that is about to occur is
 337          * done with uncached PTEs. This is lowest common denominator for all
 338          * chipsets.
 339          *
 340          * However for gen6+, we could do better by using the GFDT bit instead
 341          * of uncaching, which would allow us to flush all the LLC-cached data
 342          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
 343          */
 344         ret = i915_gem_object_set_cache_level(obj,
 345                                               HAS_WT(i915) ?
 346                                               I915_CACHE_WT : I915_CACHE_NONE);
 347         if (ret)
 348                 goto err;
 349
 350         /*
 351          * As the user may map the buffer once pinned in the display plane
 352          * (e.g. libkms for the bootup splash), we have to ensure that we
 353          * always use map_and_fenceable for all scanout buffers. However,
 354          * it may simply be too big to fit into mappable, in which case
 355          * put it anyway and hope that userspace can cope (but always first
 356          * try to preserve the existing ABI).
 357          */
 358         vma = ERR_PTR(-ENOSPC);
 359         if ((flags & PIN_MAPPABLE) == 0 &&
 360             (!view || view->type == I915_GGTT_VIEW_NORMAL))
 361                 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, alignment,
 362                                                   flags | PIN_MAPPABLE |
 363                                                   PIN_NONBLOCK);
 364         if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
 365                 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0,
 366                                                   alignment, flags);
 367         if (IS_ERR(vma)) {
 368                 ret = PTR_ERR(vma);
 369                 goto err;
 370         }
 371
 372         vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
 373
 374         i915_gem_object_flush_if_display_locked(obj);
 375
 376 err:
 377         if (ret == -EDEADLK) {
 378                 ret = i915_gem_ww_ctx_backoff(&ww);
 379                 if (!ret)
 380                         goto retry;
 381         }
 382         i915_gem_ww_ctx_fini(&ww);
 383
 384         if (ret)
 385                 return ERR_PTR(ret);
 386
 387         return vma;
 388 }
 389
 390 /**
 391  * Moves a single object to the CPU read, and possibly write domain.
 392  * @obj: object to act on
 393  * @write: requesting write or read-only access
 394  *
 395  * This function returns when the move is complete, including waiting on
 396  * flushes to occur.
 397  */
 398 int
 399 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
 400 {
 401         int ret;
 402
 403         assert_object_held(obj);
 404
 405         ret = i915_gem_object_wait(obj,
 406                                    I915_WAIT_INTERRUPTIBLE |
 407                                    (write ? I915_WAIT_ALL : 0),
 408                                    MAX_SCHEDULE_TIMEOUT);
 409         if (ret)
 410                 return ret;
 411
 412         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
 413
 414         /* Flush the CPU cache if it's still invalid. */
 415         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
 416                 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
 417                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
 418         }
 419
 420         /* It should now be out of any other write domains, and we can update
 421          * the domain values for our changes.
 422          */
 423         GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
 424
 425         /* If we're writing through the CPU, then the GPU read domains will
 426          * need to be invalidated at next use.
 427          */
 428         if (write)
 429                 __start_cpu_write(obj);
 430
 431         return 0;
 432 }
 433
 434 /**
 435  * Called when user space prepares to use an object with the CPU, either
 436  * through the mmap ioctl's mapping or a GTT mapping.
 437  * @dev: drm device
 438  * @data: ioctl data blob
 439  * @file: drm file
 440  */
 441 int
 442 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 443                           struct drm_file *file)
 444 {
 445         struct drm_i915_gem_set_domain *args = data;
 446         struct drm_i915_gem_object *obj;
 447         u32 read_domains = args->read_domains;
 448         u32 write_domain = args->write_domain;
 449         int err;
 450
 451         /* Only handle setting domains to types used by the CPU. */
 452         if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
 453                 return -EINVAL;
 454
 455         /*
 456          * Having something in the write domain implies it's in the read
 457          * domain, and only that read domain.  Enforce that in the request.
 458          */
 459         if (write_domain && read_domains != write_domain)
 460                 return -EINVAL;
 461
 462         if (!read_domains)
 463                 return 0;
 464
 465         obj = i915_gem_object_lookup(file, args->handle);
 466         if (!obj)
 467                 return -ENOENT;
 468
 469         /*
 470          * Try to flush the object off the GPU without holding the lock.
 471          * We will repeat the flush holding the lock in the normal manner
 472          * to catch cases where we are gazumped.
 473          */
 474         err = i915_gem_object_wait(obj,
 475                                    I915_WAIT_INTERRUPTIBLE |
 476                                    I915_WAIT_PRIORITY |
 477                                    (write_domain ? I915_WAIT_ALL : 0),
 478                                    MAX_SCHEDULE_TIMEOUT);
 479         if (err)
 480                 goto out;
 481
 482         /*
 483          * Proxy objects do not control access to the backing storage, ergo
 484          * they cannot be used as a means to manipulate the cache domain
 485          * tracking for that backing storage. The proxy object is always
 486          * considered to be outside of any cache domain.
 487          */
 488         if (i915_gem_object_is_proxy(obj)) {
 489                 err = -ENXIO;
 490                 goto out;
 491         }
 492
 493         /*
 494          * Flush and acquire obj->pages so that we are coherent through
 495          * direct access in memory with previous cached writes through
 496          * shmemfs and that our cache domain tracking remains valid.
 497          * For example, if the obj->filp was moved to swap without us
 498          * being notified and releasing the pages, we would mistakenly
 499          * continue to assume that the obj remained out of the CPU cached
 500          * domain.
 501          */
 502         err = i915_gem_object_pin_pages(obj);
 503         if (err)
 504                 goto out;
 505
 506         /*
 507          * Already in the desired write domain? Nothing for us to do!
 508          *
 509          * We apply a little bit of cunning here to catch a broader set of
 510          * no-ops. If obj->write_domain is set, we must be in the same
 511          * obj->read_domains, and only that domain. Therefore, if that
 512          * obj->write_domain matches the request read_domains, we are
 513          * already in the same read/write domain and can skip the operation,
 514          * without having to further check the requested write_domain.
 515          */
 516         if (READ_ONCE(obj->write_domain) == read_domains)
 517                 goto out_unpin;
 518
 519         err = i915_gem_object_lock_interruptible(obj, NULL);
 520         if (err)
 521                 goto out_unpin;
 522
 523         if (read_domains & I915_GEM_DOMAIN_WC)
 524                 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
 525         else if (read_domains & I915_GEM_DOMAIN_GTT)
 526                 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
 527         else
 528                 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
 529
 530         i915_gem_object_unlock(obj);
 531
 532         if (write_domain)
 533                 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
 534
 535 out_unpin:
 536         i915_gem_object_unpin_pages(obj);
 537 out:
 538         i915_gem_object_put(obj);
 539         return err;
 540 }
 541
 542 /*
 543  * Pins the specified object's pages and synchronizes the object with
 544  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 545  * flush the object from the CPU cache.
 546  */
 547 int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
 548                                  unsigned int *needs_clflush)
 549 {
 550         int ret;
 551
 552         *needs_clflush = 0;
 553         if (!i915_gem_object_has_struct_page(obj))
 554                 return -ENODEV;
 555
 556         assert_object_held(obj);
 557
 558         ret = i915_gem_object_wait(obj,
 559                                    I915_WAIT_INTERRUPTIBLE,
 560                                    MAX_SCHEDULE_TIMEOUT);
 561         if (ret)
 562                 return ret;
 563
 564         ret = i915_gem_object_pin_pages(obj);
 565         if (ret)
 566                 return ret;
 567
 568         if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
 569             !static_cpu_has(X86_FEATURE_CLFLUSH)) {
 570                 ret = i915_gem_object_set_to_cpu_domain(obj, false);
 571                 if (ret)
 572                         goto err_unpin;
 573                 else
 574                         goto out;
 575         }
 576
 577         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
 578
 579         /* If we're not in the cpu read domain, set ourself into the gtt
 580          * read domain and manually flush cachelines (if required). This
 581          * optimizes for the case when the gpu will dirty the data
 582          * anyway again before the next pread happens.
 583          */
 584         if (!obj->cache_dirty &&
 585             !(obj->read_domains & I915_GEM_DOMAIN_CPU))
 586                 *needs_clflush = CLFLUSH_BEFORE;
 587
 588 out:
 589         /* return with the pages pinned */
 590         return 0;
 591
 592 err_unpin:
 593         i915_gem_object_unpin_pages(obj);
 594         return ret;
 595 }
 596
 597 int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
 598                                   unsigned int *needs_clflush)
 599 {
 600         int ret;
 601
 602         *needs_clflush = 0;
 603         if (!i915_gem_object_has_struct_page(obj))
 604                 return -ENODEV;
 605
 606         assert_object_held(obj);
 607
 608         ret = i915_gem_object_wait(obj,
 609                                    I915_WAIT_INTERRUPTIBLE |
 610                                    I915_WAIT_ALL,
 611                                    MAX_SCHEDULE_TIMEOUT);
 612         if (ret)
 613                 return ret;
 614
 615         ret = i915_gem_object_pin_pages(obj);
 616         if (ret)
 617                 return ret;
 618
 619         if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
 620             !static_cpu_has(X86_FEATURE_CLFLUSH)) {
 621                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
 622                 if (ret)
 623                         goto err_unpin;
 624                 else
 625                         goto out;
 626         }
 627
 628         i915_gem_object_flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
 629
 630         /* If we're not in the cpu write domain, set ourself into the
 631          * gtt write domain and manually flush cachelines (as required).
 632          * This optimizes for the case when the gpu will use the data
 633          * right away and we therefore have to clflush anyway.
 634          */
 635         if (!obj->cache_dirty) {
 636                 *needs_clflush |= CLFLUSH_AFTER;
 637
 638                 /*
 639                  * Same trick applies to invalidate partially written
 640                  * cachelines read before writing.
 641                  */
 642                 if (!(obj->read_domains & I915_GEM_DOMAIN_CPU))
 643                         *needs_clflush |= CLFLUSH_BEFORE;
 644         }
 645
 646 out:
 647         i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
 648         obj->mm.dirty = true;
 649         /* return with the pages pinned */
 650         return 0;
 651
 652 err_unpin:
 653         i915_gem_object_unpin_pages(obj);
 654         return ret;
 655 }