1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Ltd.
7 #include <linux/bitops.h>
8 #include <linux/clk-provider.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
24 #include "clk-regmap.h"
42 static struct pll_vco trion_vco[] = {
43 { 249600000, 2000000000, 0 },
46 static struct clk_alpha_pll gpll0 = {
48 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
49 .vco_table = trion_vco,
50 .num_vco = ARRAY_SIZE(trion_vco),
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
54 .hw.init = &(struct clk_init_data){
56 .parent_data = &(const struct clk_parent_data){
60 .ops = &clk_alpha_pll_fixed_trion_ops,
65 static const struct clk_div_table post_div_table_trion_even[] = {
73 static struct clk_alpha_pll_postdiv gpll0_out_even = {
76 .post_div_table = post_div_table_trion_even,
77 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
80 .clkr.hw.init = &(struct clk_init_data){
81 .name = "gpll0_out_even",
82 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
84 .ops = &clk_alpha_pll_postdiv_trion_ops,
88 static struct clk_alpha_pll gpll1 = {
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
91 .vco_table = trion_vco,
92 .num_vco = ARRAY_SIZE(trion_vco),
94 .enable_reg = 0x52000,
95 .enable_mask = BIT(1),
96 .hw.init = &(struct clk_init_data){
98 .parent_data = &(const struct clk_parent_data){
102 .ops = &clk_alpha_pll_fixed_trion_ops,
107 static struct clk_alpha_pll gpll4 = {
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
110 .vco_table = trion_vco,
111 .num_vco = ARRAY_SIZE(trion_vco),
113 .enable_reg = 0x52000,
114 .enable_mask = BIT(4),
115 .hw.init = &(struct clk_init_data){
117 .parent_data = &(const struct clk_parent_data){
118 .fw_name = "bi_tcxo",
121 .ops = &clk_alpha_pll_fixed_trion_ops,
126 static struct clk_alpha_pll gpll7 = {
128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
129 .vco_table = trion_vco,
130 .num_vco = ARRAY_SIZE(trion_vco),
132 .enable_reg = 0x52000,
133 .enable_mask = BIT(7),
134 .hw.init = &(struct clk_init_data){
136 .parent_data = &(const struct clk_parent_data){
137 .fw_name = "bi_tcxo",
140 .ops = &clk_alpha_pll_fixed_trion_ops,
145 static const struct parent_map gcc_parent_map_0[] = {
147 { P_GPLL0_OUT_MAIN, 1 },
148 { P_GPLL0_OUT_EVEN, 6 },
151 static const struct clk_parent_data gcc_parents_0[] = {
152 { .fw_name = "bi_tcxo" },
153 { .hw = &gpll0.clkr.hw },
154 { .hw = &gpll0_out_even.clkr.hw },
157 static const struct parent_map gcc_parent_map_1[] = {
159 { P_GPLL0_OUT_MAIN, 1 },
161 { P_GPLL0_OUT_EVEN, 6 },
164 static const struct clk_parent_data gcc_parents_1[] = {
165 { .fw_name = "bi_tcxo", },
166 { .hw = &gpll0.clkr.hw },
167 { .fw_name = "sleep_clk", },
168 { .hw = &gpll0_out_even.clkr.hw },
171 static const struct parent_map gcc_parent_map_2[] = {
176 static const struct clk_parent_data gcc_parents_2[] = {
177 { .fw_name = "bi_tcxo", },
178 { .fw_name = "sleep_clk", },
181 static const struct parent_map gcc_parent_map_3[] = {
183 { P_GPLL0_OUT_MAIN, 1 },
184 { P_GPLL2_OUT_MAIN, 2 },
185 { P_GPLL5_OUT_MAIN, 3 },
186 { P_GPLL1_OUT_MAIN, 4 },
187 { P_GPLL4_OUT_MAIN, 5 },
188 { P_GPLL0_OUT_EVEN, 6 },
191 static const struct clk_parent_data gcc_parents_3[] = {
192 { .fw_name = "bi_tcxo", },
193 { .hw = &gpll0.clkr.hw },
196 { .hw = &gpll1.clkr.hw },
197 { .hw = &gpll4.clkr.hw },
198 { .hw = &gpll0_out_even.clkr.hw },
201 static const struct parent_map gcc_parent_map_4[] = {
205 static const struct clk_parent_data gcc_parents_4[] = {
206 { .fw_name = "bi_tcxo", },
209 static const struct parent_map gcc_parent_map_5[] = {
211 { P_GPLL0_OUT_MAIN, 1 },
214 static const struct clk_parent_data gcc_parents_5[] = {
215 { .fw_name = "bi_tcxo", },
216 { .hw = &gpll0.clkr.hw },
219 static const struct parent_map gcc_parent_map_6[] = {
221 { P_GPLL0_OUT_MAIN, 1 },
222 { P_GPLL7_OUT_MAIN, 3 },
223 { P_GPLL0_OUT_EVEN, 6 },
226 static const struct clk_parent_data gcc_parents_6[] = {
227 { .fw_name = "bi_tcxo", },
228 { .hw = &gpll0.clkr.hw },
229 { .hw = &gpll7.clkr.hw },
230 { .hw = &gpll0_out_even.clkr.hw },
233 static const struct parent_map gcc_parent_map_7[] = {
235 { P_GPLL0_OUT_MAIN, 1 },
236 { P_GPLL9_OUT_MAIN, 2 },
237 { P_GPLL4_OUT_MAIN, 5 },
238 { P_GPLL0_OUT_EVEN, 6 },
241 static const struct clk_parent_data gcc_parents_7[] = {
242 { .fw_name = "bi_tcxo", },
243 { .hw = &gpll0.clkr.hw },
245 { .hw = &gpll4.clkr.hw },
246 { .hw = &gpll0_out_even.clkr.hw },
249 static const struct parent_map gcc_parent_map_8[] = {
251 { P_GPLL0_OUT_MAIN, 1 },
252 { P_AUD_REF_CLK, 2 },
253 { P_GPLL0_OUT_EVEN, 6 },
256 static const struct clk_parent_data gcc_parents_8[] = {
257 { .fw_name = "bi_tcxo", },
258 { .hw = &gpll0.clkr.hw },
259 { .name = "aud_ref_clk" },
260 { .hw = &gpll0_out_even.clkr.hw },
263 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
264 F(19200000, P_BI_TCXO, 1, 0, 0),
265 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
266 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
270 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
274 .parent_map = gcc_parent_map_0,
275 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "gcc_cpuss_ahb_clk_src",
278 .parent_data = gcc_parents_0,
279 .num_parents = ARRAY_SIZE(gcc_parents_0),
280 .flags = CLK_SET_RATE_PARENT,
281 .ops = &clk_rcg2_ops,
285 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
286 F(19200000, P_BI_TCXO, 1, 0, 0),
287 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
288 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
289 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
293 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
297 .parent_map = gcc_parent_map_6,
298 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
299 .clkr.hw.init = &(struct clk_init_data){
300 .name = "gcc_emac_ptp_clk_src",
301 .parent_data = gcc_parents_6,
302 .num_parents = ARRAY_SIZE(gcc_parents_6),
303 .flags = CLK_SET_RATE_PARENT,
304 .ops = &clk_rcg2_ops,
308 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
309 F(2500000, P_BI_TCXO, 1, 25, 192),
310 F(5000000, P_BI_TCXO, 1, 25, 96),
311 F(19200000, P_BI_TCXO, 1, 0, 0),
312 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
313 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
314 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
315 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
319 static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
323 .parent_map = gcc_parent_map_6,
324 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "gcc_emac_rgmii_clk_src",
327 .parent_data = gcc_parents_6,
328 .num_parents = ARRAY_SIZE(gcc_parents_6),
329 .flags = CLK_SET_RATE_PARENT,
330 .ops = &clk_rcg2_ops,
334 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
335 F(19200000, P_BI_TCXO, 1, 0, 0),
336 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
337 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
338 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
339 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
343 static struct clk_rcg2 gcc_gp1_clk_src = {
347 .parent_map = gcc_parent_map_1,
348 .freq_tbl = ftbl_gcc_gp1_clk_src,
349 .clkr.hw.init = &(struct clk_init_data){
350 .name = "gcc_gp1_clk_src",
351 .parent_data = gcc_parents_1,
352 .num_parents = ARRAY_SIZE(gcc_parents_1),
353 .flags = CLK_SET_RATE_PARENT,
354 .ops = &clk_rcg2_ops,
358 static struct clk_rcg2 gcc_gp2_clk_src = {
362 .parent_map = gcc_parent_map_1,
363 .freq_tbl = ftbl_gcc_gp1_clk_src,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "gcc_gp2_clk_src",
366 .parent_data = gcc_parents_1,
367 .num_parents = ARRAY_SIZE(gcc_parents_1),
368 .flags = CLK_SET_RATE_PARENT,
369 .ops = &clk_rcg2_ops,
373 static struct clk_rcg2 gcc_gp3_clk_src = {
377 .parent_map = gcc_parent_map_1,
378 .freq_tbl = ftbl_gcc_gp1_clk_src,
379 .clkr.hw.init = &(struct clk_init_data){
380 .name = "gcc_gp3_clk_src",
381 .parent_data = gcc_parents_1,
382 .num_parents = ARRAY_SIZE(gcc_parents_1),
383 .flags = CLK_SET_RATE_PARENT,
384 .ops = &clk_rcg2_ops,
388 static struct clk_rcg2 gcc_gp4_clk_src = {
392 .parent_map = gcc_parent_map_1,
393 .freq_tbl = ftbl_gcc_gp1_clk_src,
394 .clkr.hw.init = &(struct clk_init_data){
395 .name = "gcc_gp4_clk_src",
396 .parent_data = gcc_parents_1,
397 .num_parents = ARRAY_SIZE(gcc_parents_1),
398 .flags = CLK_SET_RATE_PARENT,
399 .ops = &clk_rcg2_ops,
403 static struct clk_rcg2 gcc_gp5_clk_src = {
407 .parent_map = gcc_parent_map_1,
408 .freq_tbl = ftbl_gcc_gp1_clk_src,
409 .clkr.hw.init = &(struct clk_init_data){
410 .name = "gcc_gp5_clk_src",
411 .parent_data = gcc_parents_1,
412 .num_parents = ARRAY_SIZE(gcc_parents_1),
413 .flags = CLK_SET_RATE_PARENT,
414 .ops = &clk_rcg2_ops,
418 static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {
419 F(19200000, P_BI_TCXO, 1, 0, 0),
420 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
421 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
422 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
423 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
424 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
425 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
429 static struct clk_rcg2 gcc_npu_axi_clk_src = {
433 .parent_map = gcc_parent_map_3,
434 .freq_tbl = ftbl_gcc_npu_axi_clk_src,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "gcc_npu_axi_clk_src",
437 .parent_data = gcc_parents_3,
438 .num_parents = ARRAY_SIZE(gcc_parents_3),
439 .flags = CLK_SET_RATE_PARENT,
440 .ops = &clk_rcg2_ops,
444 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
445 F(9600000, P_BI_TCXO, 2, 0, 0),
446 F(19200000, P_BI_TCXO, 1, 0, 0),
450 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
454 .parent_map = gcc_parent_map_2,
455 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "gcc_pcie_0_aux_clk_src",
458 .parent_data = gcc_parents_2,
459 .num_parents = ARRAY_SIZE(gcc_parents_2),
460 .flags = CLK_SET_RATE_PARENT,
461 .ops = &clk_rcg2_ops,
465 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
469 .parent_map = gcc_parent_map_2,
470 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "gcc_pcie_1_aux_clk_src",
473 .parent_data = gcc_parents_2,
474 .num_parents = ARRAY_SIZE(gcc_parents_2),
475 .flags = CLK_SET_RATE_PARENT,
476 .ops = &clk_rcg2_ops,
480 static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
484 .parent_map = gcc_parent_map_2,
485 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
486 .clkr.hw.init = &(struct clk_init_data){
487 .name = "gcc_pcie_2_aux_clk_src",
488 .parent_data = gcc_parents_2,
489 .num_parents = ARRAY_SIZE(gcc_parents_2),
490 .flags = CLK_SET_RATE_PARENT,
491 .ops = &clk_rcg2_ops,
495 static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
499 .parent_map = gcc_parent_map_2,
500 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
501 .clkr.hw.init = &(struct clk_init_data){
502 .name = "gcc_pcie_3_aux_clk_src",
503 .parent_data = gcc_parents_2,
504 .num_parents = ARRAY_SIZE(gcc_parents_2),
505 .flags = CLK_SET_RATE_PARENT,
506 .ops = &clk_rcg2_ops,
510 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
511 F(19200000, P_BI_TCXO, 1, 0, 0),
512 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
516 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
520 .parent_map = gcc_parent_map_0,
521 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
522 .clkr.hw.init = &(struct clk_init_data){
523 .name = "gcc_pcie_phy_refgen_clk_src",
524 .parent_data = gcc_parents_0,
525 .num_parents = ARRAY_SIZE(gcc_parents_0),
526 .flags = CLK_SET_RATE_PARENT,
527 .ops = &clk_rcg2_ops,
531 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
532 F(9600000, P_BI_TCXO, 2, 0, 0),
533 F(19200000, P_BI_TCXO, 1, 0, 0),
534 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
538 static struct clk_rcg2 gcc_pdm2_clk_src = {
542 .parent_map = gcc_parent_map_0,
543 .freq_tbl = ftbl_gcc_pdm2_clk_src,
544 .clkr.hw.init = &(struct clk_init_data){
545 .name = "gcc_pdm2_clk_src",
546 .parent_data = gcc_parents_0,
547 .num_parents = ARRAY_SIZE(gcc_parents_0),
548 .flags = CLK_SET_RATE_PARENT,
549 .ops = &clk_rcg2_ops,
553 static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = {
554 F(19200000, P_BI_TCXO, 1, 0, 0),
555 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
556 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
557 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
561 static struct clk_rcg2 gcc_qspi_1_core_clk_src = {
565 .parent_map = gcc_parent_map_0,
566 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "gcc_qspi_1_core_clk_src",
569 .parent_data = gcc_parents_0,
570 .num_parents = ARRAY_SIZE(gcc_parents_0),
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_rcg2_ops,
576 static struct clk_rcg2 gcc_qspi_core_clk_src = {
580 .parent_map = gcc_parent_map_0,
581 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
582 .clkr.hw.init = &(struct clk_init_data){
583 .name = "gcc_qspi_core_clk_src",
584 .parent_data = gcc_parents_0,
585 .num_parents = ARRAY_SIZE(gcc_parents_0),
586 .flags = CLK_SET_RATE_PARENT,
587 .ops = &clk_rcg2_ops,
591 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
592 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
593 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
594 F(19200000, P_BI_TCXO, 1, 0, 0),
595 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
596 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
597 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
598 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
599 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
600 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
601 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
602 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
603 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
604 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
605 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
606 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
607 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
608 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
612 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
616 .parent_map = gcc_parent_map_0,
617 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
618 .clkr.hw.init = &(struct clk_init_data){
619 .name = "gcc_qupv3_wrap0_s0_clk_src",
620 .parent_data = gcc_parents_0,
621 .num_parents = ARRAY_SIZE(gcc_parents_0),
622 .flags = CLK_SET_RATE_PARENT,
623 .ops = &clk_rcg2_ops,
627 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
631 .parent_map = gcc_parent_map_0,
632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
633 .clkr.hw.init = &(struct clk_init_data){
634 .name = "gcc_qupv3_wrap0_s1_clk_src",
635 .parent_data = gcc_parents_0,
636 .num_parents = ARRAY_SIZE(gcc_parents_0),
637 .flags = CLK_SET_RATE_PARENT,
638 .ops = &clk_rcg2_ops,
642 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
646 .parent_map = gcc_parent_map_0,
647 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "gcc_qupv3_wrap0_s2_clk_src",
650 .parent_data = gcc_parents_0,
651 .num_parents = ARRAY_SIZE(gcc_parents_0),
652 .flags = CLK_SET_RATE_PARENT,
653 .ops = &clk_rcg2_ops,
657 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
661 .parent_map = gcc_parent_map_0,
662 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
663 .clkr.hw.init = &(struct clk_init_data){
664 .name = "gcc_qupv3_wrap0_s3_clk_src",
665 .parent_data = gcc_parents_0,
666 .num_parents = ARRAY_SIZE(gcc_parents_0),
667 .flags = CLK_SET_RATE_PARENT,
668 .ops = &clk_rcg2_ops,
672 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
676 .parent_map = gcc_parent_map_0,
677 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "gcc_qupv3_wrap0_s4_clk_src",
680 .parent_data = gcc_parents_0,
681 .num_parents = ARRAY_SIZE(gcc_parents_0),
682 .flags = CLK_SET_RATE_PARENT,
683 .ops = &clk_rcg2_ops,
687 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
691 .parent_map = gcc_parent_map_0,
692 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "gcc_qupv3_wrap0_s5_clk_src",
695 .parent_data = gcc_parents_0,
696 .num_parents = ARRAY_SIZE(gcc_parents_0),
697 .flags = CLK_SET_RATE_PARENT,
698 .ops = &clk_rcg2_ops,
702 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
706 .parent_map = gcc_parent_map_0,
707 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "gcc_qupv3_wrap0_s6_clk_src",
710 .parent_data = gcc_parents_0,
711 .num_parents = ARRAY_SIZE(gcc_parents_0),
712 .flags = CLK_SET_RATE_PARENT,
713 .ops = &clk_rcg2_ops,
717 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
721 .parent_map = gcc_parent_map_0,
722 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "gcc_qupv3_wrap0_s7_clk_src",
725 .parent_data = gcc_parents_0,
726 .num_parents = ARRAY_SIZE(gcc_parents_0),
727 .flags = CLK_SET_RATE_PARENT,
728 .ops = &clk_rcg2_ops,
732 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
736 .parent_map = gcc_parent_map_0,
737 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "gcc_qupv3_wrap1_s0_clk_src",
740 .parent_data = gcc_parents_0,
741 .num_parents = ARRAY_SIZE(gcc_parents_0),
742 .flags = CLK_SET_RATE_PARENT,
743 .ops = &clk_rcg2_ops,
747 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
751 .parent_map = gcc_parent_map_0,
752 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
753 .clkr.hw.init = &(struct clk_init_data){
754 .name = "gcc_qupv3_wrap1_s1_clk_src",
755 .parent_data = gcc_parents_0,
756 .num_parents = ARRAY_SIZE(gcc_parents_0),
757 .flags = CLK_SET_RATE_PARENT,
758 .ops = &clk_rcg2_ops,
762 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
766 .parent_map = gcc_parent_map_0,
767 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "gcc_qupv3_wrap1_s2_clk_src",
770 .parent_data = gcc_parents_0,
771 .num_parents = ARRAY_SIZE(gcc_parents_0),
772 .flags = CLK_SET_RATE_PARENT,
773 .ops = &clk_rcg2_ops,
777 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
781 .parent_map = gcc_parent_map_0,
782 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "gcc_qupv3_wrap1_s3_clk_src",
785 .parent_data = gcc_parents_0,
786 .num_parents = ARRAY_SIZE(gcc_parents_0),
787 .flags = CLK_SET_RATE_PARENT,
788 .ops = &clk_rcg2_ops,
792 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
796 .parent_map = gcc_parent_map_0,
797 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "gcc_qupv3_wrap1_s4_clk_src",
800 .parent_data = gcc_parents_0,
801 .num_parents = ARRAY_SIZE(gcc_parents_0),
802 .flags = CLK_SET_RATE_PARENT,
803 .ops = &clk_rcg2_ops,
807 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
811 .parent_map = gcc_parent_map_0,
812 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "gcc_qupv3_wrap1_s5_clk_src",
815 .parent_data = gcc_parents_0,
816 .num_parents = ARRAY_SIZE(gcc_parents_0),
817 .flags = CLK_SET_RATE_PARENT,
818 .ops = &clk_rcg2_ops,
822 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
826 .parent_map = gcc_parent_map_0,
827 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
828 .clkr.hw.init = &(struct clk_init_data){
829 .name = "gcc_qupv3_wrap2_s0_clk_src",
830 .parent_data = gcc_parents_0,
831 .num_parents = ARRAY_SIZE(gcc_parents_0),
832 .flags = CLK_SET_RATE_PARENT,
833 .ops = &clk_rcg2_ops,
837 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
841 .parent_map = gcc_parent_map_0,
842 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
843 .clkr.hw.init = &(struct clk_init_data){
844 .name = "gcc_qupv3_wrap2_s1_clk_src",
845 .parent_data = gcc_parents_0,
846 .num_parents = ARRAY_SIZE(gcc_parents_0),
847 .flags = CLK_SET_RATE_PARENT,
848 .ops = &clk_rcg2_ops,
852 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
856 .parent_map = gcc_parent_map_0,
857 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "gcc_qupv3_wrap2_s2_clk_src",
860 .parent_data = gcc_parents_0,
861 .num_parents = ARRAY_SIZE(gcc_parents_0),
862 .flags = CLK_SET_RATE_PARENT,
863 .ops = &clk_rcg2_ops,
867 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
871 .parent_map = gcc_parent_map_0,
872 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "gcc_qupv3_wrap2_s3_clk_src",
875 .parent_data = gcc_parents_0,
876 .num_parents = ARRAY_SIZE(gcc_parents_0),
877 .flags = CLK_SET_RATE_PARENT,
878 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
886 .parent_map = gcc_parent_map_0,
887 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "gcc_qupv3_wrap2_s4_clk_src",
890 .parent_data = gcc_parents_0,
891 .num_parents = ARRAY_SIZE(gcc_parents_0),
892 .flags = CLK_SET_RATE_PARENT,
893 .ops = &clk_rcg2_ops,
897 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
901 .parent_map = gcc_parent_map_0,
902 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "gcc_qupv3_wrap2_s5_clk_src",
905 .parent_data = gcc_parents_0,
906 .num_parents = ARRAY_SIZE(gcc_parents_0),
907 .flags = CLK_SET_RATE_PARENT,
908 .ops = &clk_rcg2_ops,
912 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
913 F(400000, P_BI_TCXO, 12, 1, 4),
914 F(9600000, P_BI_TCXO, 2, 0, 0),
915 F(19200000, P_BI_TCXO, 1, 0, 0),
916 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
917 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
918 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
919 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
923 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
927 .parent_map = gcc_parent_map_7,
928 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "gcc_sdcc2_apps_clk_src",
931 .parent_data = gcc_parents_7,
932 .num_parents = ARRAY_SIZE(gcc_parents_7),
933 .flags = CLK_SET_RATE_PARENT,
934 .ops = &clk_rcg2_floor_ops,
938 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
939 F(400000, P_BI_TCXO, 12, 1, 4),
940 F(9600000, P_BI_TCXO, 2, 0, 0),
941 F(19200000, P_BI_TCXO, 1, 0, 0),
942 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
943 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
944 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
948 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
952 .parent_map = gcc_parent_map_5,
953 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
954 .clkr.hw.init = &(struct clk_init_data){
955 .name = "gcc_sdcc4_apps_clk_src",
956 .parent_data = gcc_parents_5,
957 .num_parents = ARRAY_SIZE(gcc_parents_5),
958 .flags = CLK_SET_RATE_PARENT,
959 .ops = &clk_rcg2_floor_ops,
963 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
964 F(105495, P_BI_TCXO, 2, 1, 91),
968 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
972 .parent_map = gcc_parent_map_8,
973 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_tsif_ref_clk_src",
976 .parent_data = gcc_parents_8,
977 .num_parents = ARRAY_SIZE(gcc_parents_8),
978 .flags = CLK_SET_RATE_PARENT,
979 .ops = &clk_rcg2_ops,
983 static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = {
984 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
985 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
986 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
987 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
991 static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = {
995 .parent_map = gcc_parent_map_0,
996 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "gcc_ufs_card_2_axi_clk_src",
999 .parent_data = gcc_parents_0,
1000 .num_parents = ARRAY_SIZE(gcc_parents_0),
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_rcg2_ops,
1006 static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = {
1007 .cmd_rcgr = 0xa2060,
1010 .parent_map = gcc_parent_map_0,
1011 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1012 .clkr.hw.init = &(struct clk_init_data){
1013 .name = "gcc_ufs_card_2_ice_core_clk_src",
1014 .parent_data = gcc_parents_0,
1015 .num_parents = ARRAY_SIZE(gcc_parents_0),
1016 .flags = CLK_SET_RATE_PARENT,
1017 .ops = &clk_rcg2_ops,
1021 static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = {
1022 F(19200000, P_BI_TCXO, 1, 0, 0),
1026 static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = {
1027 .cmd_rcgr = 0xa2094,
1030 .parent_map = gcc_parent_map_4,
1031 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1032 .clkr.hw.init = &(struct clk_init_data){
1033 .name = "gcc_ufs_card_2_phy_aux_clk_src",
1034 .parent_data = gcc_parents_4,
1035 .num_parents = ARRAY_SIZE(gcc_parents_4),
1036 .flags = CLK_SET_RATE_PARENT,
1037 .ops = &clk_rcg2_ops,
1041 static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = {
1042 .cmd_rcgr = 0xa2078,
1045 .parent_map = gcc_parent_map_0,
1046 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1047 .clkr.hw.init = &(struct clk_init_data){
1048 .name = "gcc_ufs_card_2_unipro_core_clk_src",
1049 .parent_data = gcc_parents_0,
1050 .num_parents = ARRAY_SIZE(gcc_parents_0),
1051 .flags = CLK_SET_RATE_PARENT,
1052 .ops = &clk_rcg2_ops,
1056 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1057 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1058 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1059 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1060 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1061 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1065 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1066 .cmd_rcgr = 0x75020,
1069 .parent_map = gcc_parent_map_0,
1070 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1071 .clkr.hw.init = &(struct clk_init_data){
1072 .name = "gcc_ufs_card_axi_clk_src",
1073 .parent_data = gcc_parents_0,
1074 .num_parents = ARRAY_SIZE(gcc_parents_0),
1075 .flags = CLK_SET_RATE_PARENT,
1076 .ops = &clk_rcg2_ops,
1080 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1081 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1082 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1083 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1087 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1088 .cmd_rcgr = 0x75060,
1091 .parent_map = gcc_parent_map_0,
1092 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "gcc_ufs_card_ice_core_clk_src",
1095 .parent_data = gcc_parents_0,
1096 .num_parents = ARRAY_SIZE(gcc_parents_0),
1097 .flags = CLK_SET_RATE_PARENT,
1098 .ops = &clk_rcg2_ops,
1102 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1103 .cmd_rcgr = 0x75094,
1106 .parent_map = gcc_parent_map_4,
1107 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1108 .clkr.hw.init = &(struct clk_init_data){
1109 .name = "gcc_ufs_card_phy_aux_clk_src",
1110 .parent_data = gcc_parents_4,
1111 .num_parents = ARRAY_SIZE(gcc_parents_4),
1112 .flags = CLK_SET_RATE_PARENT,
1113 .ops = &clk_rcg2_ops,
1117 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
1118 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1119 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1120 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1124 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1125 .cmd_rcgr = 0x75078,
1128 .parent_map = gcc_parent_map_0,
1129 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
1130 .clkr.hw.init = &(struct clk_init_data){
1131 .name = "gcc_ufs_card_unipro_core_clk_src",
1132 .parent_data = gcc_parents_0,
1133 .num_parents = ARRAY_SIZE(gcc_parents_0),
1134 .flags = CLK_SET_RATE_PARENT,
1135 .ops = &clk_rcg2_ops,
1139 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1140 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1141 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1142 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1143 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1144 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1148 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1149 .cmd_rcgr = 0x77020,
1152 .parent_map = gcc_parent_map_0,
1153 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1154 .clkr.hw.init = &(struct clk_init_data){
1155 .name = "gcc_ufs_phy_axi_clk_src",
1156 .parent_data = gcc_parents_0,
1157 .num_parents = ARRAY_SIZE(gcc_parents_0),
1158 .flags = CLK_SET_RATE_PARENT,
1159 .ops = &clk_rcg2_ops,
1163 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1164 .cmd_rcgr = 0x77060,
1167 .parent_map = gcc_parent_map_0,
1168 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1169 .clkr.hw.init = &(struct clk_init_data){
1170 .name = "gcc_ufs_phy_ice_core_clk_src",
1171 .parent_data = gcc_parents_0,
1172 .num_parents = ARRAY_SIZE(gcc_parents_0),
1173 .flags = CLK_SET_RATE_PARENT,
1174 .ops = &clk_rcg2_ops,
1178 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1179 .cmd_rcgr = 0x77094,
1182 .parent_map = gcc_parent_map_4,
1183 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1184 .clkr.hw.init = &(struct clk_init_data){
1185 .name = "gcc_ufs_phy_phy_aux_clk_src",
1186 .parent_data = gcc_parents_4,
1187 .num_parents = ARRAY_SIZE(gcc_parents_4),
1188 .flags = CLK_SET_RATE_PARENT,
1189 .ops = &clk_rcg2_ops,
1193 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1194 .cmd_rcgr = 0x77078,
1197 .parent_map = gcc_parent_map_0,
1198 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1199 .clkr.hw.init = &(struct clk_init_data){
1200 .name = "gcc_ufs_phy_unipro_core_clk_src",
1201 .parent_data = gcc_parents_0,
1202 .num_parents = ARRAY_SIZE(gcc_parents_0),
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_rcg2_ops,
1208 static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1209 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1210 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1211 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1212 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1213 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1217 static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1218 .cmd_rcgr = 0xa601c,
1221 .parent_map = gcc_parent_map_0,
1222 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1223 .clkr.hw.init = &(struct clk_init_data){
1224 .name = "gcc_usb30_mp_master_clk_src",
1225 .parent_data = gcc_parents_0,
1226 .num_parents = ARRAY_SIZE(gcc_parents_0),
1227 .flags = CLK_SET_RATE_PARENT,
1228 .ops = &clk_rcg2_ops,
1232 static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = {
1233 F(19200000, P_BI_TCXO, 1, 0, 0),
1234 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1235 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1236 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1240 static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1241 .cmd_rcgr = 0xa6034,
1244 .parent_map = gcc_parent_map_0,
1245 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1246 .clkr.hw.init = &(struct clk_init_data){
1247 .name = "gcc_usb30_mp_mock_utmi_clk_src",
1248 .parent_data = gcc_parents_0,
1249 .num_parents = ARRAY_SIZE(gcc_parents_0),
1250 .flags = CLK_SET_RATE_PARENT,
1251 .ops = &clk_rcg2_ops,
1255 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1259 .parent_map = gcc_parent_map_0,
1260 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1261 .clkr.hw.init = &(struct clk_init_data){
1262 .name = "gcc_usb30_prim_master_clk_src",
1263 .parent_data = gcc_parents_0,
1264 .num_parents = ARRAY_SIZE(gcc_parents_0),
1265 .flags = CLK_SET_RATE_PARENT,
1266 .ops = &clk_rcg2_ops,
1270 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1274 .parent_map = gcc_parent_map_0,
1275 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1276 .clkr.hw.init = &(struct clk_init_data){
1277 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1278 .parent_data = gcc_parents_0,
1279 .num_parents = ARRAY_SIZE(gcc_parents_0),
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_rcg2_ops,
1285 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1286 .cmd_rcgr = 0x1001c,
1289 .parent_map = gcc_parent_map_0,
1290 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1291 .clkr.hw.init = &(struct clk_init_data){
1292 .name = "gcc_usb30_sec_master_clk_src",
1293 .parent_data = gcc_parents_0,
1294 .num_parents = ARRAY_SIZE(gcc_parents_0),
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_rcg2_ops,
1300 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1301 .cmd_rcgr = 0x10034,
1304 .parent_map = gcc_parent_map_0,
1305 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1306 .clkr.hw.init = &(struct clk_init_data){
1307 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1308 .parent_data = gcc_parents_0,
1309 .num_parents = ARRAY_SIZE(gcc_parents_0),
1310 .flags = CLK_SET_RATE_PARENT,
1311 .ops = &clk_rcg2_ops,
1315 static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1316 .cmd_rcgr = 0xa6068,
1319 .parent_map = gcc_parent_map_2,
1320 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1321 .clkr.hw.init = &(struct clk_init_data){
1322 .name = "gcc_usb3_mp_phy_aux_clk_src",
1323 .parent_data = gcc_parents_2,
1324 .num_parents = ARRAY_SIZE(gcc_parents_2),
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_rcg2_ops,
1330 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1334 .parent_map = gcc_parent_map_2,
1335 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1336 .clkr.hw.init = &(struct clk_init_data){
1337 .name = "gcc_usb3_prim_phy_aux_clk_src",
1338 .parent_data = gcc_parents_2,
1339 .num_parents = ARRAY_SIZE(gcc_parents_2),
1340 .flags = CLK_SET_RATE_PARENT,
1341 .ops = &clk_rcg2_ops,
1345 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1346 .cmd_rcgr = 0x10060,
1349 .parent_map = gcc_parent_map_2,
1350 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1351 .clkr.hw.init = &(struct clk_init_data){
1352 .name = "gcc_usb3_sec_phy_aux_clk_src",
1353 .parent_data = gcc_parents_2,
1354 .num_parents = ARRAY_SIZE(gcc_parents_2),
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_rcg2_ops,
1360 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1361 .halt_reg = 0x90018,
1362 .halt_check = BRANCH_HALT,
1364 .enable_reg = 0x90018,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "gcc_aggre_noc_pcie_tbu_clk",
1368 .ops = &clk_branch2_ops,
1373 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1374 .halt_reg = 0x750c0,
1375 .halt_check = BRANCH_HALT,
1376 .hwcg_reg = 0x750c0,
1379 .enable_reg = 0x750c0,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_aggre_ufs_card_axi_clk",
1383 .parent_hws = (const struct clk_hw *[]){
1384 &gcc_ufs_card_axi_clk_src.clkr.hw
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1393 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1394 .halt_reg = 0x750c0,
1395 .halt_check = BRANCH_HALT,
1396 .hwcg_reg = 0x750c0,
1399 .enable_reg = 0x750c0,
1400 .enable_mask = BIT(1),
1401 .hw.init = &(struct clk_init_data){
1402 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1403 .parent_hws = (const struct clk_hw *[]){
1404 &gcc_aggre_ufs_card_axi_clk.clkr.hw
1407 .flags = CLK_SET_RATE_PARENT,
1408 .ops = &clk_branch_simple_ops,
1413 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1414 .halt_reg = 0x770c0,
1415 .halt_check = BRANCH_HALT,
1416 .hwcg_reg = 0x770c0,
1419 .enable_reg = 0x770c0,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_aggre_ufs_phy_axi_clk",
1423 .parent_hws = (const struct clk_hw *[]){
1424 &gcc_ufs_phy_axi_clk_src.clkr.hw
1427 .flags = CLK_SET_RATE_PARENT,
1428 .ops = &clk_branch2_ops,
1433 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1434 .halt_reg = 0x770c0,
1435 .halt_check = BRANCH_HALT,
1436 .hwcg_reg = 0x770c0,
1439 .enable_reg = 0x770c0,
1440 .enable_mask = BIT(1),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1443 .parent_hws = (const struct clk_hw *[]){
1444 &gcc_aggre_ufs_phy_axi_clk.clkr.hw
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch_simple_ops,
1453 static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
1454 .halt_reg = 0xa6084,
1455 .halt_check = BRANCH_HALT,
1457 .enable_reg = 0xa6084,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "gcc_aggre_usb3_mp_axi_clk",
1461 .parent_hws = (const struct clk_hw *[]){
1462 &gcc_usb30_mp_master_clk_src.clkr.hw
1465 .flags = CLK_SET_RATE_PARENT,
1466 .ops = &clk_branch2_ops,
1471 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1473 .halt_check = BRANCH_HALT,
1475 .enable_reg = 0xf07c,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_aggre_usb3_prim_axi_clk",
1479 .parent_hws = (const struct clk_hw *[]){
1480 &gcc_usb30_prim_master_clk_src.clkr.hw
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1490 .halt_reg = 0x1007c,
1491 .halt_check = BRANCH_HALT,
1493 .enable_reg = 0x1007c,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_aggre_usb3_sec_axi_clk",
1497 .parent_hws = (const struct clk_hw *[]){
1498 &gcc_usb30_sec_master_clk_src.clkr.hw
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch gcc_boot_rom_ahb_clk = {
1508 .halt_reg = 0x38004,
1509 .halt_check = BRANCH_HALT_VOTED,
1510 .hwcg_reg = 0x38004,
1513 .enable_reg = 0x52004,
1514 .enable_mask = BIT(10),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_boot_rom_ahb_clk",
1517 .ops = &clk_branch2_ops,
1522 static struct clk_branch gcc_camera_hf_axi_clk = {
1524 .halt_check = BRANCH_HALT,
1526 .enable_reg = 0xb030,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "gcc_camera_hf_axi_clk",
1530 .ops = &clk_branch2_ops,
1535 static struct clk_branch gcc_camera_sf_axi_clk = {
1537 .halt_check = BRANCH_HALT,
1539 .enable_reg = 0xb034,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "gcc_camera_sf_axi_clk",
1543 .ops = &clk_branch2_ops,
1548 static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
1549 .halt_reg = 0xa609c,
1550 .halt_check = BRANCH_HALT,
1552 .enable_reg = 0xa609c,
1553 .enable_mask = BIT(0),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "gcc_cfg_noc_usb3_mp_axi_clk",
1556 .parent_hws = (const struct clk_hw *[]){
1557 &gcc_usb30_mp_master_clk_src.clkr.hw
1560 .flags = CLK_SET_RATE_PARENT,
1561 .ops = &clk_branch2_ops,
1566 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1568 .halt_check = BRANCH_HALT,
1570 .enable_reg = 0xf078,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1574 .parent_hws = (const struct clk_hw *[]){
1575 &gcc_usb30_prim_master_clk_src.clkr.hw
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1584 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1585 .halt_reg = 0x10078,
1586 .halt_check = BRANCH_HALT,
1588 .enable_reg = 0x10078,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1592 .parent_hws = (const struct clk_hw *[]){
1593 &gcc_usb30_sec_master_clk_src.clkr.hw
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1602 /* For CPUSS functionality the AHB clock needs to be left enabled */
1603 static struct clk_branch gcc_cpuss_ahb_clk = {
1604 .halt_reg = 0x48000,
1605 .halt_check = BRANCH_HALT_VOTED,
1607 .enable_reg = 0x52004,
1608 .enable_mask = BIT(21),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_cpuss_ahb_clk",
1611 .parent_hws = (const struct clk_hw *[]){
1612 &gcc_cpuss_ahb_clk_src.clkr.hw
1615 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1622 .halt_reg = 0x48008,
1623 .halt_check = BRANCH_HALT,
1625 .enable_reg = 0x48008,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "gcc_cpuss_rbcpr_clk",
1629 .ops = &clk_branch2_ops,
1634 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1635 .halt_reg = 0x71154,
1636 .halt_check = BRANCH_VOTED,
1638 .enable_reg = 0x71154,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_ddrss_gpu_axi_clk",
1642 .ops = &clk_branch2_ops,
1647 static struct clk_branch gcc_disp_hf_axi_clk = {
1649 .halt_check = BRANCH_HALT,
1651 .enable_reg = 0xb038,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_disp_hf_axi_clk",
1655 .ops = &clk_branch2_ops,
1660 static struct clk_branch gcc_disp_sf_axi_clk = {
1662 .halt_check = BRANCH_HALT,
1664 .enable_reg = 0xb03c,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_disp_sf_axi_clk",
1668 .ops = &clk_branch2_ops,
1673 static struct clk_branch gcc_emac_axi_clk = {
1675 .halt_check = BRANCH_HALT,
1677 .enable_reg = 0x6010,
1678 .enable_mask = BIT(0),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "gcc_emac_axi_clk",
1681 .ops = &clk_branch2_ops,
1686 static struct clk_branch gcc_emac_ptp_clk = {
1688 .halt_check = BRANCH_HALT,
1690 .enable_reg = 0x6034,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "gcc_emac_ptp_clk",
1694 .parent_hws = (const struct clk_hw *[]){
1695 &gcc_emac_ptp_clk_src.clkr.hw
1698 .flags = CLK_SET_RATE_PARENT,
1699 .ops = &clk_branch2_ops,
1704 static struct clk_branch gcc_emac_rgmii_clk = {
1706 .halt_check = BRANCH_HALT,
1708 .enable_reg = 0x6018,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_emac_rgmii_clk",
1712 .parent_hws = (const struct clk_hw *[]){
1713 &gcc_emac_rgmii_clk_src.clkr.hw
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1722 static struct clk_branch gcc_emac_slv_ahb_clk = {
1724 .halt_check = BRANCH_HALT,
1728 .enable_reg = 0x6014,
1729 .enable_mask = BIT(0),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "gcc_emac_slv_ahb_clk",
1732 .ops = &clk_branch2_ops,
1737 static struct clk_branch gcc_gp1_clk = {
1738 .halt_reg = 0x64000,
1739 .halt_check = BRANCH_HALT,
1741 .enable_reg = 0x64000,
1742 .enable_mask = BIT(0),
1743 .hw.init = &(struct clk_init_data){
1744 .name = "gcc_gp1_clk",
1745 .parent_hws = (const struct clk_hw *[]){
1746 &gcc_gp1_clk_src.clkr.hw
1749 .flags = CLK_SET_RATE_PARENT,
1750 .ops = &clk_branch2_ops,
1755 static struct clk_branch gcc_gp2_clk = {
1756 .halt_reg = 0x65000,
1757 .halt_check = BRANCH_HALT,
1759 .enable_reg = 0x65000,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_gp2_clk",
1763 .parent_hws = (const struct clk_hw *[]){
1764 &gcc_gp2_clk_src.clkr.hw
1767 .flags = CLK_SET_RATE_PARENT,
1768 .ops = &clk_branch2_ops,
1773 static struct clk_branch gcc_gp3_clk = {
1774 .halt_reg = 0x66000,
1775 .halt_check = BRANCH_HALT,
1777 .enable_reg = 0x66000,
1778 .enable_mask = BIT(0),
1779 .hw.init = &(struct clk_init_data){
1780 .name = "gcc_gp3_clk",
1781 .parent_hws = (const struct clk_hw *[]){
1782 &gcc_gp3_clk_src.clkr.hw
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch gcc_gp4_clk = {
1792 .halt_reg = 0xbe000,
1793 .halt_check = BRANCH_HALT,
1795 .enable_reg = 0xbe000,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_gp4_clk",
1799 .parent_hws = (const struct clk_hw *[]){
1800 &gcc_gp4_clk_src.clkr.hw
1803 .flags = CLK_SET_RATE_PARENT,
1804 .ops = &clk_branch2_ops,
1809 static struct clk_branch gcc_gp5_clk = {
1810 .halt_reg = 0xbf000,
1811 .halt_check = BRANCH_HALT,
1813 .enable_reg = 0xbf000,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "gcc_gp5_clk",
1817 .parent_hws = (const struct clk_hw *[]){
1818 &gcc_gp5_clk_src.clkr.hw
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1828 .halt_check = BRANCH_HALT_DELAY,
1830 .enable_reg = 0x52004,
1831 .enable_mask = BIT(15),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "gcc_gpu_gpll0_clk_src",
1834 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1842 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1843 .halt_check = BRANCH_HALT_DELAY,
1845 .enable_reg = 0x52004,
1846 .enable_mask = BIT(16),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "gcc_gpu_gpll0_div_clk_src",
1849 .parent_hws = (const struct clk_hw *[]){
1850 &gpll0_out_even.clkr.hw
1853 .flags = CLK_SET_RATE_PARENT,
1854 .ops = &clk_branch2_ops,
1859 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1860 .halt_reg = 0x7100c,
1861 .halt_check = BRANCH_VOTED,
1863 .enable_reg = 0x7100c,
1864 .enable_mask = BIT(0),
1865 .hw.init = &(struct clk_init_data){
1866 .name = "gcc_gpu_memnoc_gfx_clk",
1867 .ops = &clk_branch2_ops,
1872 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1873 .halt_reg = 0x71018,
1874 .halt_check = BRANCH_HALT,
1876 .enable_reg = 0x71018,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data){
1879 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1880 .ops = &clk_branch2_ops,
1885 static struct clk_branch gcc_npu_at_clk = {
1886 .halt_reg = 0x4d010,
1887 .halt_check = BRANCH_VOTED,
1889 .enable_reg = 0x4d010,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "gcc_npu_at_clk",
1893 .ops = &clk_branch2_ops,
1898 static struct clk_branch gcc_npu_axi_clk = {
1899 .halt_reg = 0x4d008,
1900 .halt_check = BRANCH_VOTED,
1902 .enable_reg = 0x4d008,
1903 .enable_mask = BIT(0),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "gcc_npu_axi_clk",
1906 .parent_hws = (const struct clk_hw *[]){
1907 &gcc_npu_axi_clk_src.clkr.hw
1910 .flags = CLK_SET_RATE_PARENT,
1911 .ops = &clk_branch2_ops,
1916 static struct clk_branch gcc_npu_gpll0_clk_src = {
1917 .halt_check = BRANCH_HALT_DELAY,
1919 .enable_reg = 0x52004,
1920 .enable_mask = BIT(18),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_npu_gpll0_clk_src",
1923 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1932 .halt_check = BRANCH_HALT_DELAY,
1934 .enable_reg = 0x52004,
1935 .enable_mask = BIT(19),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_npu_gpll0_div_clk_src",
1938 .parent_hws = (const struct clk_hw *[]){
1939 &gpll0_out_even.clkr.hw
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_npu_trig_clk = {
1949 .halt_reg = 0x4d00c,
1950 .halt_check = BRANCH_VOTED,
1952 .enable_reg = 0x4d00c,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_npu_trig_clk",
1956 .ops = &clk_branch2_ops,
1961 static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1962 .halt_reg = 0x6f02c,
1963 .halt_check = BRANCH_HALT,
1965 .enable_reg = 0x6f02c,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "gcc_pcie0_phy_refgen_clk",
1969 .parent_hws = (const struct clk_hw *[]){
1970 &gcc_pcie_phy_refgen_clk_src.clkr.hw
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1979 static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1980 .halt_reg = 0x6f030,
1981 .halt_check = BRANCH_HALT,
1983 .enable_reg = 0x6f030,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "gcc_pcie1_phy_refgen_clk",
1987 .parent_hws = (const struct clk_hw *[]){
1988 &gcc_pcie_phy_refgen_clk_src.clkr.hw
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1997 static struct clk_branch gcc_pcie2_phy_refgen_clk = {
1998 .halt_reg = 0x6f034,
1999 .halt_check = BRANCH_HALT,
2001 .enable_reg = 0x6f034,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_pcie2_phy_refgen_clk",
2005 .parent_hws = (const struct clk_hw *[]){
2006 &gcc_pcie_phy_refgen_clk_src.clkr.hw
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2015 static struct clk_branch gcc_pcie3_phy_refgen_clk = {
2016 .halt_reg = 0x6f038,
2017 .halt_check = BRANCH_HALT,
2019 .enable_reg = 0x6f038,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "gcc_pcie3_phy_refgen_clk",
2023 .parent_hws = (const struct clk_hw *[]){
2024 &gcc_pcie_phy_refgen_clk_src.clkr.hw
2027 .flags = CLK_SET_RATE_PARENT,
2028 .ops = &clk_branch2_ops,
2033 static struct clk_branch gcc_pcie_0_aux_clk = {
2034 .halt_reg = 0x6b020,
2035 .halt_check = BRANCH_HALT_VOTED,
2037 .enable_reg = 0x5200c,
2038 .enable_mask = BIT(3),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gcc_pcie_0_aux_clk",
2041 .parent_hws = (const struct clk_hw *[]){
2042 &gcc_pcie_0_aux_clk_src.clkr.hw
2045 .flags = CLK_SET_RATE_PARENT,
2046 .ops = &clk_branch2_ops,
2051 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2052 .halt_reg = 0x6b01c,
2053 .halt_check = BRANCH_HALT_VOTED,
2054 .hwcg_reg = 0x6b01c,
2057 .enable_reg = 0x5200c,
2058 .enable_mask = BIT(2),
2059 .hw.init = &(struct clk_init_data){
2060 .name = "gcc_pcie_0_cfg_ahb_clk",
2061 .ops = &clk_branch2_ops,
2066 static struct clk_branch gcc_pcie_0_clkref_clk = {
2067 .halt_reg = 0x8c00c,
2068 .halt_check = BRANCH_HALT,
2070 .enable_reg = 0x8c00c,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "gcc_pcie_0_clkref_clk",
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2080 .halt_reg = 0x6b018,
2081 .halt_check = BRANCH_HALT_VOTED,
2083 .enable_reg = 0x5200c,
2084 .enable_mask = BIT(1),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_pcie_0_mstr_axi_clk",
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch gcc_pcie_0_pipe_clk = {
2093 .halt_reg = 0x6b024,
2094 .halt_check = BRANCH_HALT_SKIP,
2096 .enable_reg = 0x5200c,
2097 .enable_mask = BIT(4),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "gcc_pcie_0_pipe_clk",
2100 .ops = &clk_branch2_ops,
2105 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2106 .halt_reg = 0x6b014,
2107 .halt_check = BRANCH_HALT_VOTED,
2108 .hwcg_reg = 0x6b014,
2111 .enable_reg = 0x5200c,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "gcc_pcie_0_slv_axi_clk",
2115 .ops = &clk_branch2_ops,
2120 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2121 .halt_reg = 0x6b010,
2122 .halt_check = BRANCH_HALT_VOTED,
2124 .enable_reg = 0x5200c,
2125 .enable_mask = BIT(5),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "gcc_pcie_0_slv_q2a_axi_clk",
2128 .ops = &clk_branch2_ops,
2133 static struct clk_branch gcc_pcie_1_aux_clk = {
2134 .halt_reg = 0x8d020,
2135 .halt_check = BRANCH_HALT_VOTED,
2137 .enable_reg = 0x52004,
2138 .enable_mask = BIT(29),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "gcc_pcie_1_aux_clk",
2141 .parent_hws = (const struct clk_hw *[]){
2142 &gcc_pcie_1_aux_clk_src.clkr.hw
2145 .flags = CLK_SET_RATE_PARENT,
2146 .ops = &clk_branch2_ops,
2151 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2152 .halt_reg = 0x8d01c,
2153 .halt_check = BRANCH_HALT_VOTED,
2154 .hwcg_reg = 0x8d01c,
2157 .enable_reg = 0x52004,
2158 .enable_mask = BIT(28),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "gcc_pcie_1_cfg_ahb_clk",
2161 .ops = &clk_branch2_ops,
2166 static struct clk_branch gcc_pcie_1_clkref_clk = {
2167 .halt_reg = 0x8c02c,
2168 .halt_check = BRANCH_HALT,
2170 .enable_reg = 0x8c02c,
2171 .enable_mask = BIT(0),
2172 .hw.init = &(struct clk_init_data){
2173 .name = "gcc_pcie_1_clkref_clk",
2174 .ops = &clk_branch2_ops,
2179 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2180 .halt_reg = 0x8d018,
2181 .halt_check = BRANCH_HALT_VOTED,
2183 .enable_reg = 0x52004,
2184 .enable_mask = BIT(27),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_pcie_1_mstr_axi_clk",
2187 .ops = &clk_branch2_ops,
2192 static struct clk_branch gcc_pcie_1_pipe_clk = {
2193 .halt_reg = 0x8d024,
2194 .halt_check = BRANCH_HALT_SKIP,
2196 .enable_reg = 0x52004,
2197 .enable_mask = BIT(30),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "gcc_pcie_1_pipe_clk",
2200 .ops = &clk_branch2_ops,
2205 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2206 .halt_reg = 0x8d014,
2207 .halt_check = BRANCH_HALT_VOTED,
2208 .hwcg_reg = 0x8d014,
2211 .enable_reg = 0x52004,
2212 .enable_mask = BIT(26),
2213 .hw.init = &(struct clk_init_data){
2214 .name = "gcc_pcie_1_slv_axi_clk",
2215 .ops = &clk_branch2_ops,
2220 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2221 .halt_reg = 0x8d010,
2222 .halt_check = BRANCH_HALT_VOTED,
2224 .enable_reg = 0x52004,
2225 .enable_mask = BIT(25),
2226 .hw.init = &(struct clk_init_data){
2227 .name = "gcc_pcie_1_slv_q2a_axi_clk",
2228 .ops = &clk_branch2_ops,
2233 static struct clk_branch gcc_pcie_2_aux_clk = {
2234 .halt_reg = 0x9d020,
2235 .halt_check = BRANCH_HALT_VOTED,
2237 .enable_reg = 0x52014,
2238 .enable_mask = BIT(14),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "gcc_pcie_2_aux_clk",
2241 .parent_hws = (const struct clk_hw *[]){
2242 &gcc_pcie_2_aux_clk_src.clkr.hw
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2251 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2252 .halt_reg = 0x9d01c,
2253 .halt_check = BRANCH_HALT_VOTED,
2254 .hwcg_reg = 0x9d01c,
2257 .enable_reg = 0x52014,
2258 .enable_mask = BIT(13),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "gcc_pcie_2_cfg_ahb_clk",
2261 .ops = &clk_branch2_ops,
2266 static struct clk_branch gcc_pcie_2_clkref_clk = {
2267 .halt_reg = 0x8c014,
2268 .halt_check = BRANCH_HALT,
2270 .enable_reg = 0x8c014,
2271 .enable_mask = BIT(0),
2272 .hw.init = &(struct clk_init_data){
2273 .name = "gcc_pcie_2_clkref_clk",
2274 .ops = &clk_branch2_ops,
2279 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2280 .halt_reg = 0x9d018,
2281 .halt_check = BRANCH_HALT_VOTED,
2283 .enable_reg = 0x52014,
2284 .enable_mask = BIT(12),
2285 .hw.init = &(struct clk_init_data){
2286 .name = "gcc_pcie_2_mstr_axi_clk",
2287 .ops = &clk_branch2_ops,
2292 static struct clk_branch gcc_pcie_2_pipe_clk = {
2293 .halt_reg = 0x9d024,
2294 .halt_check = BRANCH_HALT_SKIP,
2296 .enable_reg = 0x52014,
2297 .enable_mask = BIT(15),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "gcc_pcie_2_pipe_clk",
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2306 .halt_reg = 0x9d014,
2307 .halt_check = BRANCH_HALT_VOTED,
2308 .hwcg_reg = 0x9d014,
2311 .enable_reg = 0x52014,
2312 .enable_mask = BIT(11),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "gcc_pcie_2_slv_axi_clk",
2315 .ops = &clk_branch2_ops,
2320 static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
2321 .halt_reg = 0x9d010,
2322 .halt_check = BRANCH_HALT_VOTED,
2324 .enable_reg = 0x52014,
2325 .enable_mask = BIT(10),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gcc_pcie_2_slv_q2a_axi_clk",
2328 .ops = &clk_branch2_ops,
2333 static struct clk_branch gcc_pcie_3_aux_clk = {
2334 .halt_reg = 0xa3020,
2335 .halt_check = BRANCH_HALT_VOTED,
2337 .enable_reg = 0x52014,
2338 .enable_mask = BIT(20),
2339 .hw.init = &(struct clk_init_data){
2340 .name = "gcc_pcie_3_aux_clk",
2341 .parent_hws = (const struct clk_hw *[]){
2342 &gcc_pcie_3_aux_clk_src.clkr.hw
2345 .flags = CLK_SET_RATE_PARENT,
2346 .ops = &clk_branch2_ops,
2351 static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
2352 .halt_reg = 0xa301c,
2353 .halt_check = BRANCH_HALT_VOTED,
2354 .hwcg_reg = 0xa301c,
2357 .enable_reg = 0x52014,
2358 .enable_mask = BIT(19),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "gcc_pcie_3_cfg_ahb_clk",
2361 .ops = &clk_branch2_ops,
2366 static struct clk_branch gcc_pcie_3_clkref_clk = {
2367 .halt_reg = 0x8c018,
2368 .halt_check = BRANCH_HALT,
2370 .enable_reg = 0x8c018,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_pcie_3_clkref_clk",
2374 .ops = &clk_branch2_ops,
2379 static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
2380 .halt_reg = 0xa3018,
2381 .halt_check = BRANCH_HALT_VOTED,
2383 .enable_reg = 0x52014,
2384 .enable_mask = BIT(18),
2385 .hw.init = &(struct clk_init_data){
2386 .name = "gcc_pcie_3_mstr_axi_clk",
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch gcc_pcie_3_pipe_clk = {
2393 .halt_reg = 0xa3024,
2394 .halt_check = BRANCH_HALT_SKIP,
2396 .enable_reg = 0x52014,
2397 .enable_mask = BIT(21),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gcc_pcie_3_pipe_clk",
2400 .ops = &clk_branch2_ops,
2405 static struct clk_branch gcc_pcie_3_slv_axi_clk = {
2406 .halt_reg = 0xa3014,
2407 .halt_check = BRANCH_HALT_VOTED,
2408 .hwcg_reg = 0xa3014,
2411 .enable_reg = 0x52014,
2412 .enable_mask = BIT(17),
2413 .hw.init = &(struct clk_init_data){
2414 .name = "gcc_pcie_3_slv_axi_clk",
2415 .ops = &clk_branch2_ops,
2420 static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
2421 .halt_reg = 0xa3010,
2422 .halt_check = BRANCH_HALT_VOTED,
2424 .enable_reg = 0x52014,
2425 .enable_mask = BIT(16),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_pcie_3_slv_q2a_axi_clk",
2428 .ops = &clk_branch2_ops,
2433 static struct clk_branch gcc_pcie_phy_aux_clk = {
2434 .halt_reg = 0x6f004,
2435 .halt_check = BRANCH_HALT,
2437 .enable_reg = 0x6f004,
2438 .enable_mask = BIT(0),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "gcc_pcie_phy_aux_clk",
2441 .parent_hws = (const struct clk_hw *[]){
2442 &gcc_pcie_0_aux_clk_src.clkr.hw
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2451 static struct clk_branch gcc_pdm2_clk = {
2452 .halt_reg = 0x3300c,
2453 .halt_check = BRANCH_HALT,
2455 .enable_reg = 0x3300c,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_pdm2_clk",
2459 .parent_hws = (const struct clk_hw *[]){
2460 &gcc_pdm2_clk_src.clkr.hw
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2469 static struct clk_branch gcc_pdm_ahb_clk = {
2470 .halt_reg = 0x33004,
2471 .halt_check = BRANCH_HALT,
2472 .hwcg_reg = 0x33004,
2475 .enable_reg = 0x33004,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_pdm_ahb_clk",
2479 .ops = &clk_branch2_ops,
2484 static struct clk_branch gcc_pdm_xo4_clk = {
2485 .halt_reg = 0x33008,
2486 .halt_check = BRANCH_HALT,
2488 .enable_reg = 0x33008,
2489 .enable_mask = BIT(0),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "gcc_pdm_xo4_clk",
2492 .ops = &clk_branch2_ops,
2497 static struct clk_branch gcc_prng_ahb_clk = {
2498 .halt_reg = 0x34004,
2499 .halt_check = BRANCH_HALT_VOTED,
2501 .enable_reg = 0x52004,
2502 .enable_mask = BIT(13),
2503 .hw.init = &(struct clk_init_data){
2504 .name = "gcc_prng_ahb_clk",
2505 .ops = &clk_branch2_ops,
2510 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2512 .halt_check = BRANCH_HALT,
2516 .enable_reg = 0xb018,
2517 .enable_mask = BIT(0),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "gcc_qmip_camera_nrt_ahb_clk",
2520 .ops = &clk_branch2_ops,
2525 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2527 .halt_check = BRANCH_HALT,
2531 .enable_reg = 0xb01c,
2532 .enable_mask = BIT(0),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "gcc_qmip_camera_rt_ahb_clk",
2535 .ops = &clk_branch2_ops,
2540 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2542 .halt_check = BRANCH_HALT,
2546 .enable_reg = 0xb020,
2547 .enable_mask = BIT(0),
2548 .hw.init = &(struct clk_init_data){
2549 .name = "gcc_qmip_disp_ahb_clk",
2550 .ops = &clk_branch2_ops,
2555 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2557 .halt_check = BRANCH_HALT,
2561 .enable_reg = 0xb010,
2562 .enable_mask = BIT(0),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gcc_qmip_video_cvp_ahb_clk",
2565 .ops = &clk_branch2_ops,
2570 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2572 .halt_check = BRANCH_HALT,
2576 .enable_reg = 0xb014,
2577 .enable_mask = BIT(0),
2578 .hw.init = &(struct clk_init_data){
2579 .name = "gcc_qmip_video_vcodec_ahb_clk",
2580 .ops = &clk_branch2_ops,
2585 static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = {
2586 .halt_reg = 0x4a004,
2587 .halt_check = BRANCH_HALT,
2589 .enable_reg = 0x4a004,
2590 .enable_mask = BIT(0),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "gcc_qspi_1_cnoc_periph_ahb_clk",
2593 .ops = &clk_branch2_ops,
2598 static struct clk_branch gcc_qspi_1_core_clk = {
2599 .halt_reg = 0x4a008,
2600 .halt_check = BRANCH_HALT,
2602 .enable_reg = 0x4a008,
2603 .enable_mask = BIT(0),
2604 .hw.init = &(struct clk_init_data){
2605 .name = "gcc_qspi_1_core_clk",
2606 .parent_hws = (const struct clk_hw *[]){
2607 &gcc_qspi_1_core_clk_src.clkr.hw
2610 .flags = CLK_SET_RATE_PARENT,
2611 .ops = &clk_branch2_ops,
2616 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2617 .halt_reg = 0x4b000,
2618 .halt_check = BRANCH_HALT,
2620 .enable_reg = 0x4b000,
2621 .enable_mask = BIT(0),
2622 .hw.init = &(struct clk_init_data){
2623 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2624 .ops = &clk_branch2_ops,
2629 static struct clk_branch gcc_qspi_core_clk = {
2630 .halt_reg = 0x4b004,
2631 .halt_check = BRANCH_HALT,
2633 .enable_reg = 0x4b004,
2634 .enable_mask = BIT(0),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "gcc_qspi_core_clk",
2637 .parent_hws = (const struct clk_hw *[]){
2638 &gcc_qspi_core_clk_src.clkr.hw
2641 .flags = CLK_SET_RATE_PARENT,
2642 .ops = &clk_branch2_ops,
2647 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2648 .halt_reg = 0x17144,
2649 .halt_check = BRANCH_HALT_VOTED,
2651 .enable_reg = 0x5200c,
2652 .enable_mask = BIT(10),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gcc_qupv3_wrap0_s0_clk",
2655 .parent_hws = (const struct clk_hw *[]){
2656 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw
2659 .flags = CLK_SET_RATE_PARENT,
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2666 .halt_reg = 0x17274,
2667 .halt_check = BRANCH_HALT_VOTED,
2669 .enable_reg = 0x5200c,
2670 .enable_mask = BIT(11),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_qupv3_wrap0_s1_clk",
2673 .parent_hws = (const struct clk_hw *[]){
2674 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw
2677 .flags = CLK_SET_RATE_PARENT,
2678 .ops = &clk_branch2_ops,
2683 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2684 .halt_reg = 0x173a4,
2685 .halt_check = BRANCH_HALT_VOTED,
2687 .enable_reg = 0x5200c,
2688 .enable_mask = BIT(12),
2689 .hw.init = &(struct clk_init_data){
2690 .name = "gcc_qupv3_wrap0_s2_clk",
2691 .parent_hws = (const struct clk_hw *[]){
2692 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw
2695 .flags = CLK_SET_RATE_PARENT,
2696 .ops = &clk_branch2_ops,
2701 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2702 .halt_reg = 0x174d4,
2703 .halt_check = BRANCH_HALT_VOTED,
2705 .enable_reg = 0x5200c,
2706 .enable_mask = BIT(13),
2707 .hw.init = &(struct clk_init_data){
2708 .name = "gcc_qupv3_wrap0_s3_clk",
2709 .parent_hws = (const struct clk_hw *[]){
2710 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw
2713 .flags = CLK_SET_RATE_PARENT,
2714 .ops = &clk_branch2_ops,
2719 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2720 .halt_reg = 0x17604,
2721 .halt_check = BRANCH_HALT_VOTED,
2723 .enable_reg = 0x5200c,
2724 .enable_mask = BIT(14),
2725 .hw.init = &(struct clk_init_data){
2726 .name = "gcc_qupv3_wrap0_s4_clk",
2727 .parent_hws = (const struct clk_hw *[]){
2728 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw
2731 .flags = CLK_SET_RATE_PARENT,
2732 .ops = &clk_branch2_ops,
2737 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2738 .halt_reg = 0x17734,
2739 .halt_check = BRANCH_HALT_VOTED,
2741 .enable_reg = 0x5200c,
2742 .enable_mask = BIT(15),
2743 .hw.init = &(struct clk_init_data){
2744 .name = "gcc_qupv3_wrap0_s5_clk",
2745 .parent_hws = (const struct clk_hw *[]){
2746 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw
2749 .flags = CLK_SET_RATE_PARENT,
2750 .ops = &clk_branch2_ops,
2755 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2756 .halt_reg = 0x17864,
2757 .halt_check = BRANCH_HALT_VOTED,
2759 .enable_reg = 0x5200c,
2760 .enable_mask = BIT(16),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "gcc_qupv3_wrap0_s6_clk",
2763 .parent_hws = (const struct clk_hw *[]){
2764 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw
2767 .flags = CLK_SET_RATE_PARENT,
2768 .ops = &clk_branch2_ops,
2773 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2774 .halt_reg = 0x17994,
2775 .halt_check = BRANCH_HALT_VOTED,
2777 .enable_reg = 0x5200c,
2778 .enable_mask = BIT(17),
2779 .hw.init = &(struct clk_init_data){
2780 .name = "gcc_qupv3_wrap0_s7_clk",
2781 .parent_hws = (const struct clk_hw *[]){
2782 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw
2785 .flags = CLK_SET_RATE_PARENT,
2786 .ops = &clk_branch2_ops,
2791 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2792 .halt_reg = 0x18144,
2793 .halt_check = BRANCH_HALT_VOTED,
2795 .enable_reg = 0x5200c,
2796 .enable_mask = BIT(22),
2797 .hw.init = &(struct clk_init_data){
2798 .name = "gcc_qupv3_wrap1_s0_clk",
2799 .parent_hws = (const struct clk_hw *[]){
2800 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw
2803 .flags = CLK_SET_RATE_PARENT,
2804 .ops = &clk_branch2_ops,
2809 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2810 .halt_reg = 0x18274,
2811 .halt_check = BRANCH_HALT_VOTED,
2813 .enable_reg = 0x5200c,
2814 .enable_mask = BIT(23),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "gcc_qupv3_wrap1_s1_clk",
2817 .parent_hws = (const struct clk_hw *[]){
2818 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw
2821 .flags = CLK_SET_RATE_PARENT,
2822 .ops = &clk_branch2_ops,
2827 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2828 .halt_reg = 0x183a4,
2829 .halt_check = BRANCH_HALT_VOTED,
2831 .enable_reg = 0x5200c,
2832 .enable_mask = BIT(24),
2833 .hw.init = &(struct clk_init_data){
2834 .name = "gcc_qupv3_wrap1_s2_clk",
2835 .parent_hws = (const struct clk_hw *[]){
2836 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw
2839 .flags = CLK_SET_RATE_PARENT,
2840 .ops = &clk_branch2_ops,
2845 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2846 .halt_reg = 0x184d4,
2847 .halt_check = BRANCH_HALT_VOTED,
2849 .enable_reg = 0x5200c,
2850 .enable_mask = BIT(25),
2851 .hw.init = &(struct clk_init_data){
2852 .name = "gcc_qupv3_wrap1_s3_clk",
2853 .parent_hws = (const struct clk_hw *[]){
2854 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw
2857 .flags = CLK_SET_RATE_PARENT,
2858 .ops = &clk_branch2_ops,
2863 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2864 .halt_reg = 0x18604,
2865 .halt_check = BRANCH_HALT_VOTED,
2867 .enable_reg = 0x5200c,
2868 .enable_mask = BIT(26),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "gcc_qupv3_wrap1_s4_clk",
2871 .parent_hws = (const struct clk_hw *[]){
2872 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2881 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2882 .halt_reg = 0x18734,
2883 .halt_check = BRANCH_HALT_VOTED,
2885 .enable_reg = 0x5200c,
2886 .enable_mask = BIT(27),
2887 .hw.init = &(struct clk_init_data){
2888 .name = "gcc_qupv3_wrap1_s5_clk",
2889 .parent_hws = (const struct clk_hw *[]){
2890 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw
2893 .flags = CLK_SET_RATE_PARENT,
2894 .ops = &clk_branch2_ops,
2899 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2900 .halt_reg = 0x1e144,
2901 .halt_check = BRANCH_HALT_VOTED,
2903 .enable_reg = 0x52014,
2904 .enable_mask = BIT(4),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "gcc_qupv3_wrap2_s0_clk",
2907 .parent_hws = (const struct clk_hw *[]){
2908 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw
2911 .flags = CLK_SET_RATE_PARENT,
2912 .ops = &clk_branch2_ops,
2917 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2918 .halt_reg = 0x1e274,
2919 .halt_check = BRANCH_HALT_VOTED,
2921 .enable_reg = 0x52014,
2922 .enable_mask = BIT(5),
2923 .hw.init = &(struct clk_init_data){
2924 .name = "gcc_qupv3_wrap2_s1_clk",
2925 .parent_hws = (const struct clk_hw *[]){
2926 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw
2929 .flags = CLK_SET_RATE_PARENT,
2930 .ops = &clk_branch2_ops,
2935 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2936 .halt_reg = 0x1e3a4,
2937 .halt_check = BRANCH_HALT_VOTED,
2939 .enable_reg = 0x52014,
2940 .enable_mask = BIT(6),
2941 .hw.init = &(struct clk_init_data){
2942 .name = "gcc_qupv3_wrap2_s2_clk",
2943 .parent_hws = (const struct clk_hw *[]){
2944 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw
2947 .flags = CLK_SET_RATE_PARENT,
2948 .ops = &clk_branch2_ops,
2953 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2954 .halt_reg = 0x1e4d4,
2955 .halt_check = BRANCH_HALT_VOTED,
2957 .enable_reg = 0x52014,
2958 .enable_mask = BIT(7),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "gcc_qupv3_wrap2_s3_clk",
2961 .parent_hws = (const struct clk_hw *[]){
2962 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw
2965 .flags = CLK_SET_RATE_PARENT,
2966 .ops = &clk_branch2_ops,
2971 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2972 .halt_reg = 0x1e604,
2973 .halt_check = BRANCH_HALT_VOTED,
2975 .enable_reg = 0x52014,
2976 .enable_mask = BIT(8),
2977 .hw.init = &(struct clk_init_data){
2978 .name = "gcc_qupv3_wrap2_s4_clk",
2979 .parent_hws = (const struct clk_hw *[]){
2980 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw
2983 .flags = CLK_SET_RATE_PARENT,
2984 .ops = &clk_branch2_ops,
2989 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2990 .halt_reg = 0x1e734,
2991 .halt_check = BRANCH_HALT_VOTED,
2993 .enable_reg = 0x52014,
2994 .enable_mask = BIT(9),
2995 .hw.init = &(struct clk_init_data){
2996 .name = "gcc_qupv3_wrap2_s5_clk",
2997 .parent_hws = (const struct clk_hw *[]){
2998 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw
3001 .flags = CLK_SET_RATE_PARENT,
3002 .ops = &clk_branch2_ops,
3007 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3008 .halt_reg = 0x17004,
3009 .halt_check = BRANCH_HALT_VOTED,
3011 .enable_reg = 0x5200c,
3012 .enable_mask = BIT(6),
3013 .hw.init = &(struct clk_init_data){
3014 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
3015 .ops = &clk_branch2_ops,
3020 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3021 .halt_reg = 0x17008,
3022 .halt_check = BRANCH_HALT_VOTED,
3023 .hwcg_reg = 0x17008,
3026 .enable_reg = 0x5200c,
3027 .enable_mask = BIT(7),
3028 .hw.init = &(struct clk_init_data){
3029 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
3030 .ops = &clk_branch2_ops,
3035 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3036 .halt_reg = 0x18004,
3037 .halt_check = BRANCH_HALT_VOTED,
3039 .enable_reg = 0x5200c,
3040 .enable_mask = BIT(20),
3041 .hw.init = &(struct clk_init_data){
3042 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
3043 .ops = &clk_branch2_ops,
3048 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3049 .halt_reg = 0x18008,
3050 .halt_check = BRANCH_HALT_VOTED,
3051 .hwcg_reg = 0x18008,
3054 .enable_reg = 0x5200c,
3055 .enable_mask = BIT(21),
3056 .hw.init = &(struct clk_init_data){
3057 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
3058 .ops = &clk_branch2_ops,
3063 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
3064 .halt_reg = 0x1e004,
3065 .halt_check = BRANCH_HALT_VOTED,
3067 .enable_reg = 0x52014,
3068 .enable_mask = BIT(2),
3069 .hw.init = &(struct clk_init_data){
3070 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
3071 .ops = &clk_branch2_ops,
3076 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
3077 .halt_reg = 0x1e008,
3078 .halt_check = BRANCH_HALT_VOTED,
3079 .hwcg_reg = 0x1e008,
3082 .enable_reg = 0x52014,
3083 .enable_mask = BIT(1),
3084 .hw.init = &(struct clk_init_data){
3085 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
3086 .ops = &clk_branch2_ops,
3091 static struct clk_branch gcc_sdcc2_ahb_clk = {
3092 .halt_reg = 0x14008,
3093 .halt_check = BRANCH_HALT,
3095 .enable_reg = 0x14008,
3096 .enable_mask = BIT(0),
3097 .hw.init = &(struct clk_init_data){
3098 .name = "gcc_sdcc2_ahb_clk",
3099 .ops = &clk_branch2_ops,
3104 static struct clk_branch gcc_sdcc2_apps_clk = {
3105 .halt_reg = 0x14004,
3106 .halt_check = BRANCH_HALT,
3108 .enable_reg = 0x14004,
3109 .enable_mask = BIT(0),
3110 .hw.init = &(struct clk_init_data){
3111 .name = "gcc_sdcc2_apps_clk",
3112 .parent_hws = (const struct clk_hw *[]){
3113 &gcc_sdcc2_apps_clk_src.clkr.hw
3116 .flags = CLK_SET_RATE_PARENT,
3117 .ops = &clk_branch2_ops,
3122 static struct clk_branch gcc_sdcc4_ahb_clk = {
3123 .halt_reg = 0x16008,
3124 .halt_check = BRANCH_HALT,
3126 .enable_reg = 0x16008,
3127 .enable_mask = BIT(0),
3128 .hw.init = &(struct clk_init_data){
3129 .name = "gcc_sdcc4_ahb_clk",
3130 .ops = &clk_branch2_ops,
3135 static struct clk_branch gcc_sdcc4_apps_clk = {
3136 .halt_reg = 0x16004,
3137 .halt_check = BRANCH_HALT,
3139 .enable_reg = 0x16004,
3140 .enable_mask = BIT(0),
3141 .hw.init = &(struct clk_init_data){
3142 .name = "gcc_sdcc4_apps_clk",
3143 .parent_hws = (const struct clk_hw *[]){
3144 &gcc_sdcc4_apps_clk_src.clkr.hw
3147 .flags = CLK_SET_RATE_PARENT,
3148 .ops = &clk_branch2_ops,
3153 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
3154 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3155 .halt_reg = 0x4819c,
3156 .halt_check = BRANCH_HALT_VOTED,
3158 .enable_reg = 0x52004,
3159 .enable_mask = BIT(0),
3160 .hw.init = &(struct clk_init_data){
3161 .name = "gcc_sys_noc_cpuss_ahb_clk",
3162 .parent_hws = (const struct clk_hw *[]){
3163 &gcc_cpuss_ahb_clk_src.clkr.hw
3166 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
3167 .ops = &clk_branch2_ops,
3172 static struct clk_branch gcc_tsif_ahb_clk = {
3173 .halt_reg = 0x36004,
3174 .halt_check = BRANCH_HALT,
3176 .enable_reg = 0x36004,
3177 .enable_mask = BIT(0),
3178 .hw.init = &(struct clk_init_data){
3179 .name = "gcc_tsif_ahb_clk",
3180 .ops = &clk_branch2_ops,
3185 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
3186 .halt_reg = 0x3600c,
3187 .halt_check = BRANCH_HALT,
3189 .enable_reg = 0x3600c,
3190 .enable_mask = BIT(0),
3191 .hw.init = &(struct clk_init_data){
3192 .name = "gcc_tsif_inactivity_timers_clk",
3193 .ops = &clk_branch2_ops,
3198 static struct clk_branch gcc_tsif_ref_clk = {
3199 .halt_reg = 0x36008,
3200 .halt_check = BRANCH_HALT,
3202 .enable_reg = 0x36008,
3203 .enable_mask = BIT(0),
3204 .hw.init = &(struct clk_init_data){
3205 .name = "gcc_tsif_ref_clk",
3206 .parent_hws = (const struct clk_hw *[]){
3207 &gcc_tsif_ref_clk_src.clkr.hw
3210 .flags = CLK_SET_RATE_PARENT,
3211 .ops = &clk_branch2_ops,
3216 static struct clk_branch gcc_ufs_card_2_ahb_clk = {
3217 .halt_reg = 0xa2014,
3218 .halt_check = BRANCH_HALT,
3219 .hwcg_reg = 0xa2014,
3222 .enable_reg = 0xa2014,
3223 .enable_mask = BIT(0),
3224 .hw.init = &(struct clk_init_data){
3225 .name = "gcc_ufs_card_2_ahb_clk",
3226 .ops = &clk_branch2_ops,
3231 static struct clk_branch gcc_ufs_card_2_axi_clk = {
3232 .halt_reg = 0xa2010,
3233 .halt_check = BRANCH_HALT,
3234 .hwcg_reg = 0xa2010,
3237 .enable_reg = 0xa2010,
3238 .enable_mask = BIT(0),
3239 .hw.init = &(struct clk_init_data){
3240 .name = "gcc_ufs_card_2_axi_clk",
3241 .parent_hws = (const struct clk_hw *[]){
3242 &gcc_ufs_card_2_axi_clk_src.clkr.hw
3245 .flags = CLK_SET_RATE_PARENT,
3246 .ops = &clk_branch2_ops,
3251 static struct clk_branch gcc_ufs_card_2_ice_core_clk = {
3252 .halt_reg = 0xa205c,
3253 .halt_check = BRANCH_HALT,
3254 .hwcg_reg = 0xa205c,
3257 .enable_reg = 0xa205c,
3258 .enable_mask = BIT(0),
3259 .hw.init = &(struct clk_init_data){
3260 .name = "gcc_ufs_card_2_ice_core_clk",
3261 .parent_hws = (const struct clk_hw *[]){
3262 &gcc_ufs_card_2_ice_core_clk_src.clkr.hw
3265 .flags = CLK_SET_RATE_PARENT,
3266 .ops = &clk_branch2_ops,
3271 static struct clk_branch gcc_ufs_card_2_phy_aux_clk = {
3272 .halt_reg = 0xa2090,
3273 .halt_check = BRANCH_HALT,
3274 .hwcg_reg = 0xa2090,
3277 .enable_reg = 0xa2090,
3278 .enable_mask = BIT(0),
3279 .hw.init = &(struct clk_init_data){
3280 .name = "gcc_ufs_card_2_phy_aux_clk",
3281 .parent_hws = (const struct clk_hw *[]){
3282 &gcc_ufs_card_2_phy_aux_clk_src.clkr.hw
3285 .flags = CLK_SET_RATE_PARENT,
3286 .ops = &clk_branch2_ops,
3291 static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = {
3292 .halt_reg = 0xa201c,
3293 .halt_check = BRANCH_HALT,
3295 .enable_reg = 0xa201c,
3296 .enable_mask = BIT(0),
3297 .hw.init = &(struct clk_init_data){
3298 .name = "gcc_ufs_card_2_rx_symbol_0_clk",
3299 .ops = &clk_branch2_ops,
3304 static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = {
3305 .halt_reg = 0xa20ac,
3306 .halt_check = BRANCH_HALT,
3308 .enable_reg = 0xa20ac,
3309 .enable_mask = BIT(0),
3310 .hw.init = &(struct clk_init_data){
3311 .name = "gcc_ufs_card_2_rx_symbol_1_clk",
3312 .ops = &clk_branch2_ops,
3317 static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = {
3318 .halt_reg = 0xa2018,
3319 .halt_check = BRANCH_HALT,
3321 .enable_reg = 0xa2018,
3322 .enable_mask = BIT(0),
3323 .hw.init = &(struct clk_init_data){
3324 .name = "gcc_ufs_card_2_tx_symbol_0_clk",
3325 .ops = &clk_branch2_ops,
3330 static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
3331 .halt_reg = 0xa2058,
3332 .halt_check = BRANCH_HALT,
3333 .hwcg_reg = 0xa2058,
3336 .enable_reg = 0xa2058,
3337 .enable_mask = BIT(0),
3338 .hw.init = &(struct clk_init_data){
3339 .name = "gcc_ufs_card_2_unipro_core_clk",
3340 .parent_hws = (const struct clk_hw *[]){
3341 &gcc_ufs_card_2_unipro_core_clk_src.clkr.hw
3344 .flags = CLK_SET_RATE_PARENT,
3345 .ops = &clk_branch2_ops,
3350 static struct clk_branch gcc_ufs_card_ahb_clk = {
3351 .halt_reg = 0x75014,
3352 .halt_check = BRANCH_HALT,
3353 .hwcg_reg = 0x75014,
3356 .enable_reg = 0x75014,
3357 .enable_mask = BIT(0),
3358 .hw.init = &(struct clk_init_data){
3359 .name = "gcc_ufs_card_ahb_clk",
3360 .ops = &clk_branch2_ops,
3365 static struct clk_branch gcc_ufs_card_axi_clk = {
3366 .halt_reg = 0x75010,
3367 .halt_check = BRANCH_HALT,
3368 .hwcg_reg = 0x75010,
3371 .enable_reg = 0x75010,
3372 .enable_mask = BIT(0),
3373 .hw.init = &(struct clk_init_data){
3374 .name = "gcc_ufs_card_axi_clk",
3375 .parent_hws = (const struct clk_hw *[]){
3376 &gcc_ufs_card_axi_clk_src.clkr.hw
3379 .flags = CLK_SET_RATE_PARENT,
3380 .ops = &clk_branch2_ops,
3385 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
3386 .halt_reg = 0x75010,
3387 .halt_check = BRANCH_HALT,
3388 .hwcg_reg = 0x75010,
3391 .enable_reg = 0x75010,
3392 .enable_mask = BIT(1),
3393 .hw.init = &(struct clk_init_data){
3394 .name = "gcc_ufs_card_axi_hw_ctl_clk",
3395 .parent_hws = (const struct clk_hw *[]){
3396 &gcc_ufs_card_axi_clk.clkr.hw
3399 .flags = CLK_SET_RATE_PARENT,
3400 .ops = &clk_branch_simple_ops,
3405 static struct clk_branch gcc_ufs_card_ice_core_clk = {
3406 .halt_reg = 0x7505c,
3407 .halt_check = BRANCH_HALT,
3408 .hwcg_reg = 0x7505c,
3411 .enable_reg = 0x7505c,
3412 .enable_mask = BIT(0),
3413 .hw.init = &(struct clk_init_data){
3414 .name = "gcc_ufs_card_ice_core_clk",
3415 .parent_hws = (const struct clk_hw *[]){
3416 &gcc_ufs_card_ice_core_clk_src.clkr.hw
3419 .flags = CLK_SET_RATE_PARENT,
3420 .ops = &clk_branch2_ops,
3425 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
3426 .halt_reg = 0x7505c,
3427 .halt_check = BRANCH_HALT,
3428 .hwcg_reg = 0x7505c,
3431 .enable_reg = 0x7505c,
3432 .enable_mask = BIT(1),
3433 .hw.init = &(struct clk_init_data){
3434 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
3435 .parent_hws = (const struct clk_hw *[]){
3436 &gcc_ufs_card_ice_core_clk.clkr.hw
3439 .flags = CLK_SET_RATE_PARENT,
3440 .ops = &clk_branch_simple_ops,
3445 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
3446 .halt_reg = 0x75090,
3447 .halt_check = BRANCH_HALT,
3448 .hwcg_reg = 0x75090,
3451 .enable_reg = 0x75090,
3452 .enable_mask = BIT(0),
3453 .hw.init = &(struct clk_init_data){
3454 .name = "gcc_ufs_card_phy_aux_clk",
3455 .parent_hws = (const struct clk_hw *[]){
3456 &gcc_ufs_card_phy_aux_clk_src.clkr.hw
3459 .flags = CLK_SET_RATE_PARENT,
3460 .ops = &clk_branch2_ops,
3465 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
3466 .halt_reg = 0x75090,
3467 .halt_check = BRANCH_HALT,
3468 .hwcg_reg = 0x75090,
3471 .enable_reg = 0x75090,
3472 .enable_mask = BIT(1),
3473 .hw.init = &(struct clk_init_data){
3474 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
3475 .parent_hws = (const struct clk_hw *[]){
3476 &gcc_ufs_card_phy_aux_clk.clkr.hw
3479 .flags = CLK_SET_RATE_PARENT,
3480 .ops = &clk_branch_simple_ops,
3485 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
3486 .halt_reg = 0x7501c,
3487 .halt_check = BRANCH_HALT_DELAY,
3489 .enable_reg = 0x7501c,
3490 .enable_mask = BIT(0),
3491 .hw.init = &(struct clk_init_data){
3492 .name = "gcc_ufs_card_rx_symbol_0_clk",
3493 .ops = &clk_branch2_ops,
3498 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
3499 .halt_reg = 0x750ac,
3500 .halt_check = BRANCH_HALT_DELAY,
3502 .enable_reg = 0x750ac,
3503 .enable_mask = BIT(0),
3504 .hw.init = &(struct clk_init_data){
3505 .name = "gcc_ufs_card_rx_symbol_1_clk",
3506 .ops = &clk_branch2_ops,
3511 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
3512 .halt_reg = 0x75018,
3513 .halt_check = BRANCH_HALT_DELAY,
3515 .enable_reg = 0x75018,
3516 .enable_mask = BIT(0),
3517 .hw.init = &(struct clk_init_data){
3518 .name = "gcc_ufs_card_tx_symbol_0_clk",
3519 .ops = &clk_branch2_ops,
3524 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
3525 .halt_reg = 0x75058,
3526 .halt_check = BRANCH_HALT,
3527 .hwcg_reg = 0x75058,
3530 .enable_reg = 0x75058,
3531 .enable_mask = BIT(0),
3532 .hw.init = &(struct clk_init_data){
3533 .name = "gcc_ufs_card_unipro_core_clk",
3534 .parent_hws = (const struct clk_hw *[]){
3535 &gcc_ufs_card_unipro_core_clk_src.clkr.hw
3538 .flags = CLK_SET_RATE_PARENT,
3539 .ops = &clk_branch2_ops,
3544 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
3545 .halt_reg = 0x75058,
3546 .halt_check = BRANCH_HALT,
3547 .hwcg_reg = 0x75058,
3550 .enable_reg = 0x75058,
3551 .enable_mask = BIT(1),
3552 .hw.init = &(struct clk_init_data){
3553 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
3554 .parent_hws = (const struct clk_hw *[]){
3555 &gcc_ufs_card_unipro_core_clk.clkr.hw
3558 .flags = CLK_SET_RATE_PARENT,
3559 .ops = &clk_branch_simple_ops,
3564 static struct clk_branch gcc_ufs_phy_ahb_clk = {
3565 .halt_reg = 0x77014,
3566 .halt_check = BRANCH_HALT,
3567 .hwcg_reg = 0x77014,
3570 .enable_reg = 0x77014,
3571 .enable_mask = BIT(0),
3572 .hw.init = &(struct clk_init_data){
3573 .name = "gcc_ufs_phy_ahb_clk",
3574 .ops = &clk_branch2_ops,
3579 static struct clk_branch gcc_ufs_phy_axi_clk = {
3580 .halt_reg = 0x77010,
3581 .halt_check = BRANCH_HALT,
3582 .hwcg_reg = 0x77010,
3585 .enable_reg = 0x77010,
3586 .enable_mask = BIT(0),
3587 .hw.init = &(struct clk_init_data){
3588 .name = "gcc_ufs_phy_axi_clk",
3589 .parent_hws = (const struct clk_hw *[]){
3590 &gcc_ufs_phy_axi_clk_src.clkr.hw
3593 .flags = CLK_SET_RATE_PARENT,
3594 .ops = &clk_branch2_ops,
3599 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3600 .halt_reg = 0x77010,
3601 .halt_check = BRANCH_HALT,
3602 .hwcg_reg = 0x77010,
3605 .enable_reg = 0x77010,
3606 .enable_mask = BIT(1),
3607 .hw.init = &(struct clk_init_data){
3608 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
3609 .parent_hws = (const struct clk_hw *[]){
3610 &gcc_ufs_phy_axi_clk.clkr.hw
3613 .flags = CLK_SET_RATE_PARENT,
3614 .ops = &clk_branch_simple_ops,
3619 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3620 .halt_reg = 0x7705c,
3621 .halt_check = BRANCH_HALT,
3622 .hwcg_reg = 0x7705c,
3625 .enable_reg = 0x7705c,
3626 .enable_mask = BIT(0),
3627 .hw.init = &(struct clk_init_data){
3628 .name = "gcc_ufs_phy_ice_core_clk",
3629 .parent_hws = (const struct clk_hw *[]){
3630 &gcc_ufs_phy_ice_core_clk_src.clkr.hw
3633 .flags = CLK_SET_RATE_PARENT,
3634 .ops = &clk_branch2_ops,
3639 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3640 .halt_reg = 0x7705c,
3641 .halt_check = BRANCH_HALT,
3642 .hwcg_reg = 0x7705c,
3645 .enable_reg = 0x7705c,
3646 .enable_mask = BIT(1),
3647 .hw.init = &(struct clk_init_data){
3648 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3649 .parent_hws = (const struct clk_hw *[]){
3650 &gcc_ufs_phy_ice_core_clk.clkr.hw
3653 .flags = CLK_SET_RATE_PARENT,
3654 .ops = &clk_branch_simple_ops,
3659 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3660 .halt_reg = 0x77090,
3661 .halt_check = BRANCH_HALT,
3662 .hwcg_reg = 0x77090,
3665 .enable_reg = 0x77090,
3666 .enable_mask = BIT(0),
3667 .hw.init = &(struct clk_init_data){
3668 .name = "gcc_ufs_phy_phy_aux_clk",
3669 .parent_hws = (const struct clk_hw *[]){
3670 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw
3673 .flags = CLK_SET_RATE_PARENT,
3674 .ops = &clk_branch2_ops,
3679 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3680 .halt_reg = 0x77090,
3681 .halt_check = BRANCH_HALT,
3682 .hwcg_reg = 0x77090,
3685 .enable_reg = 0x77090,
3686 .enable_mask = BIT(1),
3687 .hw.init = &(struct clk_init_data){
3688 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3689 .parent_hws = (const struct clk_hw *[]){
3690 &gcc_ufs_phy_phy_aux_clk.clkr.hw
3693 .flags = CLK_SET_RATE_PARENT,
3694 .ops = &clk_branch_simple_ops,
3699 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3700 .halt_reg = 0x7701c,
3701 .halt_check = BRANCH_HALT_SKIP,
3703 .enable_reg = 0x7701c,
3704 .enable_mask = BIT(0),
3705 .hw.init = &(struct clk_init_data){
3706 .name = "gcc_ufs_phy_rx_symbol_0_clk",
3707 .ops = &clk_branch2_ops,
3712 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3713 .halt_reg = 0x770ac,
3714 .halt_check = BRANCH_HALT_SKIP,
3716 .enable_reg = 0x770ac,
3717 .enable_mask = BIT(0),
3718 .hw.init = &(struct clk_init_data){
3719 .name = "gcc_ufs_phy_rx_symbol_1_clk",
3720 .ops = &clk_branch2_ops,
3725 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3726 .halt_reg = 0x77018,
3727 .halt_check = BRANCH_HALT_SKIP,
3729 .enable_reg = 0x77018,
3730 .enable_mask = BIT(0),
3731 .hw.init = &(struct clk_init_data){
3732 .name = "gcc_ufs_phy_tx_symbol_0_clk",
3733 .ops = &clk_branch2_ops,
3738 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3739 .halt_reg = 0x77058,
3740 .halt_check = BRANCH_HALT,
3741 .hwcg_reg = 0x77058,
3744 .enable_reg = 0x77058,
3745 .enable_mask = BIT(0),
3746 .hw.init = &(struct clk_init_data){
3747 .name = "gcc_ufs_phy_unipro_core_clk",
3748 .parent_hws = (const struct clk_hw *[]){
3749 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw
3752 .flags = CLK_SET_RATE_PARENT,
3753 .ops = &clk_branch2_ops,
3758 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3759 .halt_reg = 0x77058,
3760 .halt_check = BRANCH_HALT,
3761 .hwcg_reg = 0x77058,
3764 .enable_reg = 0x77058,
3765 .enable_mask = BIT(1),
3766 .hw.init = &(struct clk_init_data){
3767 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3768 .parent_hws = (const struct clk_hw *[]){
3769 &gcc_ufs_phy_unipro_core_clk.clkr.hw
3772 .flags = CLK_SET_RATE_PARENT,
3773 .ops = &clk_branch_simple_ops,
3778 static struct clk_branch gcc_usb30_mp_master_clk = {
3779 .halt_reg = 0xa6010,
3780 .halt_check = BRANCH_HALT,
3782 .enable_reg = 0xa6010,
3783 .enable_mask = BIT(0),
3784 .hw.init = &(struct clk_init_data){
3785 .name = "gcc_usb30_mp_master_clk",
3786 .parent_hws = (const struct clk_hw *[]){
3787 &gcc_usb30_mp_master_clk_src.clkr.hw },
3789 .flags = CLK_SET_RATE_PARENT,
3790 .ops = &clk_branch2_ops,
3795 static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
3796 .halt_reg = 0xa6018,
3797 .halt_check = BRANCH_HALT,
3799 .enable_reg = 0xa6018,
3800 .enable_mask = BIT(0),
3801 .hw.init = &(struct clk_init_data){
3802 .name = "gcc_usb30_mp_mock_utmi_clk",
3803 .parent_hws = (const struct clk_hw *[]){
3804 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw
3807 .flags = CLK_SET_RATE_PARENT,
3808 .ops = &clk_branch2_ops,
3813 static struct clk_branch gcc_usb30_mp_sleep_clk = {
3814 .halt_reg = 0xa6014,
3815 .halt_check = BRANCH_HALT,
3817 .enable_reg = 0xa6014,
3818 .enable_mask = BIT(0),
3819 .hw.init = &(struct clk_init_data){
3820 .name = "gcc_usb30_mp_sleep_clk",
3821 .ops = &clk_branch2_ops,
3826 static struct clk_branch gcc_usb30_prim_master_clk = {
3828 .halt_check = BRANCH_HALT,
3830 .enable_reg = 0xf010,
3831 .enable_mask = BIT(0),
3832 .hw.init = &(struct clk_init_data){
3833 .name = "gcc_usb30_prim_master_clk",
3834 .parent_hws = (const struct clk_hw *[]){
3835 &gcc_usb30_prim_master_clk_src.clkr.hw },
3837 .flags = CLK_SET_RATE_PARENT,
3838 .ops = &clk_branch2_ops,
3843 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3845 .halt_check = BRANCH_HALT,
3847 .enable_reg = 0xf018,
3848 .enable_mask = BIT(0),
3849 .hw.init = &(struct clk_init_data){
3850 .name = "gcc_usb30_prim_mock_utmi_clk",
3851 .parent_hws = (const struct clk_hw *[]){
3852 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw
3855 .flags = CLK_SET_RATE_PARENT,
3856 .ops = &clk_branch2_ops,
3861 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3863 .halt_check = BRANCH_HALT,
3865 .enable_reg = 0xf014,
3866 .enable_mask = BIT(0),
3867 .hw.init = &(struct clk_init_data){
3868 .name = "gcc_usb30_prim_sleep_clk",
3869 .ops = &clk_branch2_ops,
3874 static struct clk_branch gcc_usb30_sec_master_clk = {
3875 .halt_reg = 0x10010,
3876 .halt_check = BRANCH_HALT,
3878 .enable_reg = 0x10010,
3879 .enable_mask = BIT(0),
3880 .hw.init = &(struct clk_init_data){
3881 .name = "gcc_usb30_sec_master_clk",
3882 .parent_hws = (const struct clk_hw *[]){
3883 &gcc_usb30_sec_master_clk_src.clkr.hw },
3885 .flags = CLK_SET_RATE_PARENT,
3886 .ops = &clk_branch2_ops,
3891 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3892 .halt_reg = 0x10018,
3893 .halt_check = BRANCH_HALT,
3895 .enable_reg = 0x10018,
3896 .enable_mask = BIT(0),
3897 .hw.init = &(struct clk_init_data){
3898 .name = "gcc_usb30_sec_mock_utmi_clk",
3899 .parent_hws = (const struct clk_hw *[]){
3900 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw
3903 .flags = CLK_SET_RATE_PARENT,
3904 .ops = &clk_branch2_ops,
3909 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3910 .halt_reg = 0x10014,
3911 .halt_check = BRANCH_HALT,
3913 .enable_reg = 0x10014,
3914 .enable_mask = BIT(0),
3915 .hw.init = &(struct clk_init_data){
3916 .name = "gcc_usb30_sec_sleep_clk",
3917 .ops = &clk_branch2_ops,
3922 static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
3923 .halt_reg = 0xa6050,
3924 .halt_check = BRANCH_HALT,
3926 .enable_reg = 0xa6050,
3927 .enable_mask = BIT(0),
3928 .hw.init = &(struct clk_init_data){
3929 .name = "gcc_usb3_mp_phy_aux_clk",
3930 .parent_hws = (const struct clk_hw *[]){
3931 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3934 .flags = CLK_SET_RATE_PARENT,
3935 .ops = &clk_branch2_ops,
3940 static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
3941 .halt_reg = 0xa6054,
3942 .halt_check = BRANCH_HALT,
3944 .enable_reg = 0xa6054,
3945 .enable_mask = BIT(0),
3946 .hw.init = &(struct clk_init_data){
3947 .name = "gcc_usb3_mp_phy_com_aux_clk",
3948 .parent_hws = (const struct clk_hw *[]){
3949 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3952 .flags = CLK_SET_RATE_PARENT,
3953 .ops = &clk_branch2_ops,
3958 static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
3959 .halt_reg = 0xa6058,
3960 .halt_check = BRANCH_HALT_SKIP,
3962 .enable_reg = 0xa6058,
3963 .enable_mask = BIT(0),
3964 .hw.init = &(struct clk_init_data){
3965 .name = "gcc_usb3_mp_phy_pipe_0_clk",
3966 .ops = &clk_branch2_ops,
3971 static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
3972 .halt_reg = 0xa605c,
3973 .halt_check = BRANCH_HALT_SKIP,
3975 .enable_reg = 0xa605c,
3976 .enable_mask = BIT(0),
3977 .hw.init = &(struct clk_init_data){
3978 .name = "gcc_usb3_mp_phy_pipe_1_clk",
3979 .ops = &clk_branch2_ops,
3984 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3985 .halt_reg = 0x8c008,
3986 .halt_check = BRANCH_HALT,
3988 .enable_reg = 0x8c008,
3989 .enable_mask = BIT(0),
3990 .hw.init = &(struct clk_init_data){
3991 .name = "gcc_usb3_prim_clkref_clk",
3992 .ops = &clk_branch2_ops,
3997 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3999 .halt_check = BRANCH_HALT,
4001 .enable_reg = 0xf050,
4002 .enable_mask = BIT(0),
4003 .hw.init = &(struct clk_init_data){
4004 .name = "gcc_usb3_prim_phy_aux_clk",
4005 .parent_hws = (const struct clk_hw *[]){
4006 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4009 .flags = CLK_SET_RATE_PARENT,
4010 .ops = &clk_branch2_ops,
4015 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
4017 .halt_check = BRANCH_HALT,
4019 .enable_reg = 0xf054,
4020 .enable_mask = BIT(0),
4021 .hw.init = &(struct clk_init_data){
4022 .name = "gcc_usb3_prim_phy_com_aux_clk",
4023 .parent_hws = (const struct clk_hw *[]){
4024 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4027 .flags = CLK_SET_RATE_PARENT,
4028 .ops = &clk_branch2_ops,
4033 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
4035 .halt_check = BRANCH_HALT_SKIP,
4037 .enable_reg = 0xf058,
4038 .enable_mask = BIT(0),
4039 .hw.init = &(struct clk_init_data){
4040 .name = "gcc_usb3_prim_phy_pipe_clk",
4041 .ops = &clk_branch2_ops,
4046 static struct clk_branch gcc_usb3_sec_clkref_clk = {
4047 .halt_reg = 0x8c028,
4048 .halt_check = BRANCH_HALT,
4050 .enable_reg = 0x8c028,
4051 .enable_mask = BIT(0),
4052 .hw.init = &(struct clk_init_data){
4053 .name = "gcc_usb3_sec_clkref_clk",
4054 .ops = &clk_branch2_ops,
4059 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
4060 .halt_reg = 0x10050,
4061 .halt_check = BRANCH_HALT,
4063 .enable_reg = 0x10050,
4064 .enable_mask = BIT(0),
4065 .hw.init = &(struct clk_init_data){
4066 .name = "gcc_usb3_sec_phy_aux_clk",
4067 .parent_hws = (const struct clk_hw *[]){
4068 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4071 .flags = CLK_SET_RATE_PARENT,
4072 .ops = &clk_branch2_ops,
4077 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
4078 .halt_reg = 0x10054,
4079 .halt_check = BRANCH_HALT,
4081 .enable_reg = 0x10054,
4082 .enable_mask = BIT(0),
4083 .hw.init = &(struct clk_init_data){
4084 .name = "gcc_usb3_sec_phy_com_aux_clk",
4085 .parent_hws = (const struct clk_hw *[]){
4086 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4089 .flags = CLK_SET_RATE_PARENT,
4090 .ops = &clk_branch2_ops,
4095 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
4096 .halt_reg = 0x10058,
4097 .halt_check = BRANCH_HALT_SKIP,
4099 .enable_reg = 0x10058,
4100 .enable_mask = BIT(0),
4101 .hw.init = &(struct clk_init_data){
4102 .name = "gcc_usb3_sec_phy_pipe_clk",
4103 .ops = &clk_branch2_ops,
4108 static struct clk_branch gcc_video_axi0_clk = {
4110 .halt_check = BRANCH_HALT,
4112 .enable_reg = 0xb024,
4113 .enable_mask = BIT(0),
4114 .hw.init = &(struct clk_init_data){
4115 .name = "gcc_video_axi0_clk",
4116 .ops = &clk_branch2_ops,
4121 static struct clk_branch gcc_video_axi1_clk = {
4123 .halt_check = BRANCH_HALT,
4125 .enable_reg = 0xb028,
4126 .enable_mask = BIT(0),
4127 .hw.init = &(struct clk_init_data){
4128 .name = "gcc_video_axi1_clk",
4129 .ops = &clk_branch2_ops,
4134 static struct clk_branch gcc_video_axic_clk = {
4136 .halt_check = BRANCH_HALT,
4138 .enable_reg = 0xb02c,
4139 .enable_mask = BIT(0),
4140 .hw.init = &(struct clk_init_data){
4141 .name = "gcc_video_axic_clk",
4142 .ops = &clk_branch2_ops,
4147 static struct gdsc usb30_sec_gdsc = {
4150 .name = "usb30_sec_gdsc",
4152 .pwrsts = PWRSTS_OFF_ON,
4153 .flags = POLL_CFG_GDSCR,
4156 static struct gdsc emac_gdsc = {
4159 .name = "emac_gdsc",
4161 .pwrsts = PWRSTS_OFF_ON,
4162 .flags = POLL_CFG_GDSCR,
4165 static struct gdsc usb30_prim_gdsc = {
4168 .name = "usb30_prim_gdsc",
4170 .pwrsts = PWRSTS_OFF_ON,
4171 .flags = POLL_CFG_GDSCR,
4174 static struct gdsc pcie_0_gdsc = {
4177 .name = "pcie_0_gdsc",
4179 .pwrsts = PWRSTS_OFF_ON,
4180 .flags = POLL_CFG_GDSCR,
4183 static struct gdsc ufs_card_gdsc = {
4186 .name = "ufs_card_gdsc",
4188 .pwrsts = PWRSTS_OFF_ON,
4189 .flags = POLL_CFG_GDSCR,
4192 static struct gdsc ufs_phy_gdsc = {
4195 .name = "ufs_phy_gdsc",
4197 .pwrsts = PWRSTS_OFF_ON,
4198 .flags = POLL_CFG_GDSCR,
4201 static struct gdsc pcie_1_gdsc = {
4204 .name = "pcie_1_gdsc",
4206 .pwrsts = PWRSTS_OFF_ON,
4207 .flags = POLL_CFG_GDSCR,
4210 static struct gdsc pcie_2_gdsc = {
4213 .name = "pcie_2_gdsc",
4215 .pwrsts = PWRSTS_OFF_ON,
4216 .flags = POLL_CFG_GDSCR,
4219 static struct gdsc ufs_card_2_gdsc = {
4222 .name = "ufs_card_2_gdsc",
4224 .pwrsts = PWRSTS_OFF_ON,
4225 .flags = POLL_CFG_GDSCR,
4228 static struct gdsc pcie_3_gdsc = {
4231 .name = "pcie_3_gdsc",
4233 .pwrsts = PWRSTS_OFF_ON,
4234 .flags = POLL_CFG_GDSCR,
4237 static struct gdsc usb30_mp_gdsc = {
4240 .name = "usb30_mp_gdsc",
4242 .pwrsts = PWRSTS_OFF_ON,
4243 .flags = POLL_CFG_GDSCR,
4246 static struct clk_regmap *gcc_sc8180x_clocks[] = {
4247 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
4248 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4249 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
4250 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4251 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
4252 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
4253 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4254 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
4255 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
4256 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
4257 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
4258 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
4259 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
4260 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
4261 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
4262 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
4263 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
4264 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
4265 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
4266 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
4267 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
4268 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
4269 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
4270 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
4271 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
4272 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
4273 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4274 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
4275 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4276 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
4277 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4278 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
4279 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
4280 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
4281 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
4282 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
4283 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
4284 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
4285 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
4286 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
4287 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
4288 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
4289 [GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,
4290 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
4291 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
4292 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
4293 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
4294 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
4295 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
4296 [GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr,
4297 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
4298 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
4299 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
4300 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
4301 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
4302 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
4303 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
4304 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
4305 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
4306 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
4307 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
4308 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
4309 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
4310 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
4311 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
4312 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
4313 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
4314 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
4315 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
4316 [GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,
4317 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
4318 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
4319 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
4320 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
4321 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
4322 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
4323 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
4324 [GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,
4325 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
4326 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
4327 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
4328 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
4329 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
4330 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
4331 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4332 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
4333 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4334 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
4335 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4336 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
4337 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
4338 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
4339 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
4340 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
4341 [GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr,
4342 [GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr,
4343 [GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr,
4344 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
4345 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
4346 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
4347 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
4348 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4349 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4350 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4351 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4352 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4353 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4354 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4355 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4356 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4357 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4358 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4359 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
4360 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
4361 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
4362 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
4363 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4364 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4365 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4366 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4367 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4368 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4369 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4370 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4371 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4372 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4373 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4374 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4375 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
4376 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
4377 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
4378 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
4379 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
4380 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
4381 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
4382 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
4383 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
4384 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
4385 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
4386 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
4387 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4388 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4389 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4390 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4391 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
4392 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
4393 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4394 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4395 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
4396 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
4397 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
4398 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
4399 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
4400 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
4401 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
4402 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
4403 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
4404 [GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr,
4405 [GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr,
4406 [GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr,
4407 [GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr,
4408 [GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr,
4409 [GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr,
4410 [GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr,
4411 [GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr,
4412 [GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr,
4413 [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
4414 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
4415 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
4416 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
4417 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
4418 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
4419 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
4420 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
4421 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
4422 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
4423 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
4424 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
4425 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
4426 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
4427 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
4428 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
4429 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
4430 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
4431 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
4432 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4433 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4434 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4435 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
4436 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4437 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4438 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
4439 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4440 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4441 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
4442 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4443 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
4444 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4445 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4446 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4447 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
4448 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
4449 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
4450 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
4451 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
4452 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
4453 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4454 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4455 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4456 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4457 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4458 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
4459 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
4460 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
4461 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
4462 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
4463 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
4464 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
4465 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
4466 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
4467 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
4468 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
4469 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
4470 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4471 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4472 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4473 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
4474 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
4475 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
4476 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
4477 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
4478 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4479 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
4480 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
4481 [GPLL0] = &gpll0.clkr,
4482 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
4483 [GPLL1] = &gpll1.clkr,
4484 [GPLL4] = &gpll4.clkr,
4485 [GPLL7] = &gpll7.clkr,
4488 static const struct qcom_reset_map gcc_sc8180x_resets[] = {
4489 [GCC_EMAC_BCR] = { 0x6000 },
4490 [GCC_GPU_BCR] = { 0x71000 },
4491 [GCC_MMSS_BCR] = { 0xb000 },
4492 [GCC_NPU_BCR] = { 0x4d000 },
4493 [GCC_PCIE_0_BCR] = { 0x6b000 },
4494 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4495 [GCC_PCIE_1_BCR] = { 0x8d000 },
4496 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4497 [GCC_PCIE_2_BCR] = { 0x9d000 },
4498 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4499 [GCC_PCIE_3_BCR] = { 0xa3000 },
4500 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4501 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
4502 [GCC_PDM_BCR] = { 0x33000 },
4503 [GCC_PRNG_BCR] = { 0x34000 },
4504 [GCC_QSPI_1_BCR] = { 0x4a000 },
4505 [GCC_QSPI_BCR] = { 0x24008 },
4506 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4507 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4508 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4509 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4510 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4511 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4512 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4513 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4514 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4515 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4516 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4517 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4518 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4519 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4520 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4521 [GCC_SDCC2_BCR] = { 0x14000 },
4522 [GCC_SDCC4_BCR] = { 0x16000 },
4523 [GCC_TSIF_BCR] = { 0x36000 },
4524 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4525 [GCC_UFS_CARD_BCR] = { 0x75000 },
4526 [GCC_UFS_PHY_BCR] = { 0x77000 },
4527 [GCC_USB30_MP_BCR] = { 0xa6000 },
4528 [GCC_USB30_PRIM_BCR] = { 0xf000 },
4529 [GCC_USB30_SEC_BCR] = { 0x10000 },
4530 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4531 [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
4532 [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
4533 [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
4536 static struct gdsc *gcc_sc8180x_gdscs[] = {
4537 [EMAC_GDSC] = &emac_gdsc,
4538 [PCIE_0_GDSC] = &pcie_0_gdsc,
4539 [PCIE_1_GDSC] = &pcie_1_gdsc,
4540 [PCIE_2_GDSC] = &pcie_2_gdsc,
4541 [PCIE_3_GDSC] = &pcie_3_gdsc,
4542 [UFS_CARD_GDSC] = &ufs_card_gdsc,
4543 [UFS_CARD_2_GDSC] = &ufs_card_2_gdsc,
4544 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
4545 [USB30_MP_GDSC] = &usb30_mp_gdsc,
4546 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4547 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
4550 static const struct regmap_config gcc_sc8180x_regmap_config = {
4554 .max_register = 0xc0004,
4558 static const struct qcom_cc_desc gcc_sc8180x_desc = {
4559 .config = &gcc_sc8180x_regmap_config,
4560 .clks = gcc_sc8180x_clocks,
4561 .num_clks = ARRAY_SIZE(gcc_sc8180x_clocks),
4562 .resets = gcc_sc8180x_resets,
4563 .num_resets = ARRAY_SIZE(gcc_sc8180x_resets),
4564 .gdscs = gcc_sc8180x_gdscs,
4565 .num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),
4568 static const struct of_device_id gcc_sc8180x_match_table[] = {
4569 { .compatible = "qcom,gcc-sc8180x" },
4572 MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
4574 static int gcc_sc8180x_probe(struct platform_device *pdev)
4576 struct regmap *regmap;
4578 regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
4580 return PTR_ERR(regmap);
4583 * Enable the following always-on clocks:
4584 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
4585 * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK,
4586 * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and
4587 * GCC_GPU_CFG_AHB_CLK
4589 regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0));
4590 regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0));
4591 regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0));
4592 regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0));
4593 regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0));
4594 regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0));
4595 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
4596 regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0));
4597 regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0));
4598 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
4600 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
4601 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
4602 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4604 return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap);
4607 static struct platform_driver gcc_sc8180x_driver = {
4608 .probe = gcc_sc8180x_probe,
4610 .name = "gcc-sc8180x",
4611 .of_match_table = gcc_sc8180x_match_table,
4615 static int __init gcc_sc8180x_init(void)
4617 return platform_driver_register(&gcc_sc8180x_driver);
4619 core_initcall(gcc_sc8180x_init);
4621 static void __exit gcc_sc8180x_exit(void)
4623 platform_driver_unregister(&gcc_sc8180x_driver);
4625 module_exit(gcc_sc8180x_exit);
4627 MODULE_DESCRIPTION("QTI GCC SC8180x driver");
4628 MODULE_LICENSE("GPL v2");