gcc-msm8939.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2020 Linaro Limited
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset-controller.h>
  15
  16 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  17 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "reset.h"
  25 #include "gdsc.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL0_AUX,
  31         P_BIMC,
  32         P_GPLL1,
  33         P_GPLL1_AUX,
  34         P_GPLL2,
  35         P_GPLL2_AUX,
  36         P_GPLL3,
  37         P_GPLL3_AUX,
  38         P_GPLL4,
  39         P_GPLL5,
  40         P_GPLL5_AUX,
  41         P_GPLL5_EARLY,
  42         P_GPLL6,
  43         P_GPLL6_AUX,
  44         P_SLEEP_CLK,
  45         P_DSI0_PHYPLL_BYTE,
  46         P_DSI0_PHYPLL_DSI,
  47         P_EXT_PRI_I2S,
  48         P_EXT_SEC_I2S,
  49         P_EXT_MCLK,
  50 };
  51
  52 static struct clk_pll gpll0 = {
  53         .l_reg = 0x21004,
  54         .m_reg = 0x21008,
  55         .n_reg = 0x2100c,
  56         .config_reg = 0x21010,
  57         .mode_reg = 0x21000,
  58         .status_reg = 0x2101c,
  59         .status_bit = 17,
  60         .clkr.hw.init = &(struct clk_init_data){
  61                 .name = "gpll0",
  62                 .parent_data = &(const struct clk_parent_data) {
  63                         .fw_name = "xo",
  64                 },
  65                 .num_parents = 1,
  66                 .ops = &clk_pll_ops,
  67         },
  68 };
  69
  70 static struct clk_regmap gpll0_vote = {
  71         .enable_reg = 0x45000,
  72         .enable_mask = BIT(0),
  73         .hw.init = &(struct clk_init_data){
  74                 .name = "gpll0_vote",
  75                 .parent_hws = (const struct clk_hw*[]) {
  76                         &gpll0.clkr.hw,
  77                 },
  78                 .num_parents = 1,
  79                 .ops = &clk_pll_vote_ops,
  80         },
  81 };
  82
  83 static struct clk_pll gpll1 = {
  84         .l_reg = 0x20004,
  85         .m_reg = 0x20008,
  86         .n_reg = 0x2000c,
  87         .config_reg = 0x20010,
  88         .mode_reg = 0x20000,
  89         .status_reg = 0x2001c,
  90         .status_bit = 17,
  91         .clkr.hw.init = &(struct clk_init_data){
  92                 .name = "gpll1",
  93                 .parent_data = &(const struct clk_parent_data) {
  94                         .fw_name = "xo",
  95                 },
  96                 .num_parents = 1,
  97                 .ops = &clk_pll_ops,
  98         },
  99 };
 100
 101 static struct clk_regmap gpll1_vote = {
 102         .enable_reg = 0x45000,
 103         .enable_mask = BIT(1),
 104         .hw.init = &(struct clk_init_data){
 105                 .name = "gpll1_vote",
 106                 .parent_hws = (const struct clk_hw*[]) {
 107                         &gpll1.clkr.hw,
 108                 },
 109                 .num_parents = 1,
 110                 .ops = &clk_pll_vote_ops,
 111         },
 112 };
 113
 114 static struct clk_pll gpll2 = {
 115         .l_reg = 0x4a004,
 116         .m_reg = 0x4a008,
 117         .n_reg = 0x4a00c,
 118         .config_reg = 0x4a010,
 119         .mode_reg = 0x4a000,
 120         .status_reg = 0x4a01c,
 121         .status_bit = 17,
 122         .clkr.hw.init = &(struct clk_init_data){
 123                 .name = "gpll2",
 124                 .parent_data = &(const struct clk_parent_data) {
 125                         .fw_name = "xo",
 126                 },
 127                 .num_parents = 1,
 128                 .ops = &clk_pll_ops,
 129         },
 130 };
 131
 132 static struct clk_regmap gpll2_vote = {
 133         .enable_reg = 0x45000,
 134         .enable_mask = BIT(2),
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "gpll2_vote",
 137                 .parent_hws = (const struct clk_hw*[]) {
 138                         &gpll2.clkr.hw,
 139                 },
 140                 .num_parents = 1,
 141                 .ops = &clk_pll_vote_ops,
 142         },
 143 };
 144
 145 static struct clk_pll bimc_pll = {
 146         .l_reg = 0x23004,
 147         .m_reg = 0x23008,
 148         .n_reg = 0x2300c,
 149         .config_reg = 0x23010,
 150         .mode_reg = 0x23000,
 151         .status_reg = 0x2301c,
 152         .status_bit = 17,
 153         .clkr.hw.init = &(struct clk_init_data){
 154                 .name = "bimc_pll",
 155                 .parent_data = &(const struct clk_parent_data) {
 156                         .fw_name = "xo",
 157                 },
 158                 .num_parents = 1,
 159                 .ops = &clk_pll_ops,
 160         },
 161 };
 162
 163 static struct clk_regmap bimc_pll_vote = {
 164         .enable_reg = 0x45000,
 165         .enable_mask = BIT(3),
 166         .hw.init = &(struct clk_init_data){
 167                 .name = "bimc_pll_vote",
 168                 .parent_hws = (const struct clk_hw*[]) {
 169                         &bimc_pll.clkr.hw,
 170                 },
 171                 .num_parents = 1,
 172                 .ops = &clk_pll_vote_ops,
 173         },
 174 };
 175
 176 static struct clk_pll gpll3 = {
 177         .l_reg = 0x22004,
 178         .m_reg = 0x22008,
 179         .n_reg = 0x2200c,
 180         .config_reg = 0x22010,
 181         .mode_reg = 0x22000,
 182         .status_reg = 0x2201c,
 183         .status_bit = 17,
 184         .clkr.hw.init = &(struct clk_init_data){
 185                 .name = "gpll3",
 186                 .parent_data = &(const struct clk_parent_data) {
 187                         .fw_name = "xo",
 188                 },
 189                 .num_parents = 1,
 190                 .ops = &clk_pll_ops,
 191         },
 192 };
 193
 194 static struct clk_regmap gpll3_vote = {
 195         .enable_reg = 0x45000,
 196         .enable_mask = BIT(4),
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "gpll3_vote",
 199                 .parent_hws = (const struct clk_hw*[]) {
 200                         &gpll3.clkr.hw,
 201                 },
 202                 .num_parents = 1,
 203                 .ops = &clk_pll_vote_ops,
 204         },
 205 };
 206
 207 /* GPLL3 at 1100 MHz, main output enabled. */
 208 static const struct pll_config gpll3_config = {
 209         .l = 57,
 210         .m = 7,
 211         .n = 24,
 212         .vco_val = 0x0,
 213         .vco_mask = BIT(20),
 214         .pre_div_val = 0x0,
 215         .pre_div_mask = BIT(12),
 216         .post_div_val = 0x0,
 217         .post_div_mask = BIT(9) | BIT(8),
 218         .mn_ena_mask = BIT(24),
 219         .main_output_mask = BIT(0),
 220         .aux_output_mask = BIT(1),
 221 };
 222
 223 static struct clk_pll gpll4 = {
 224         .l_reg = 0x24004,
 225         .m_reg = 0x24008,
 226         .n_reg = 0x2400c,
 227         .config_reg = 0x24010,
 228         .mode_reg = 0x24000,
 229         .status_reg = 0x2401c,
 230         .status_bit = 17,
 231         .clkr.hw.init = &(struct clk_init_data){
 232                 .name = "gpll4",
 233                 .parent_data = &(const struct clk_parent_data) {
 234                         .fw_name = "xo",
 235                 },
 236                 .num_parents = 1,
 237                 .ops = &clk_pll_ops,
 238         },
 239 };
 240
 241 static struct clk_regmap gpll4_vote = {
 242         .enable_reg = 0x45000,
 243         .enable_mask = BIT(5),
 244         .hw.init = &(struct clk_init_data){
 245                 .name = "gpll4_vote",
 246                 .parent_hws = (const struct clk_hw*[]) {
 247                         &gpll4.clkr.hw,
 248                 },
 249                 .num_parents = 1,
 250                 .ops = &clk_pll_vote_ops,
 251         },
 252 };
 253
 254 /* GPLL4 at 1200 MHz, main output enabled. */
 255 static struct pll_config gpll4_config = {
 256         .l = 62,
 257         .m = 1,
 258         .n = 2,
 259         .vco_val = 0x0,
 260         .vco_mask = BIT(20),
 261         .pre_div_val = 0x0,
 262         .pre_div_mask = BIT(12),
 263         .post_div_val = 0x0,
 264         .post_div_mask = BIT(9) | BIT(8),
 265         .mn_ena_mask = BIT(24),
 266         .main_output_mask = BIT(0),
 267 };
 268
 269 static struct clk_pll gpll5 = {
 270         .l_reg = 0x25004,
 271         .m_reg = 0x25008,
 272         .n_reg = 0x2500c,
 273         .config_reg = 0x25010,
 274         .mode_reg = 0x25000,
 275         .status_reg = 0x2501c,
 276         .status_bit = 17,
 277         .clkr.hw.init = &(struct clk_init_data){
 278                 .name = "gpll5",
 279                 .parent_data = &(const struct clk_parent_data) {
 280                         .fw_name = "xo",
 281                 },
 282                 .num_parents = 1,
 283                 .ops = &clk_pll_ops,
 284         },
 285 };
 286
 287 static struct clk_regmap gpll5_vote = {
 288         .enable_reg = 0x45000,
 289         .enable_mask = BIT(6),
 290         .hw.init = &(struct clk_init_data){
 291                 .name = "gpll5_vote",
 292                 .parent_hws = (const struct clk_hw*[]) {
 293                         &gpll5.clkr.hw,
 294                 },
 295                 .num_parents = 1,
 296                 .ops = &clk_pll_vote_ops,
 297         },
 298 };
 299
 300 static struct clk_pll gpll6 = {
 301         .l_reg = 0x37004,
 302         .m_reg = 0x37008,
 303         .n_reg = 0x3700c,
 304         .config_reg = 0x37010,
 305         .mode_reg = 0x37000,
 306         .status_reg = 0x3701c,
 307         .status_bit = 17,
 308         .clkr.hw.init = &(struct clk_init_data){
 309                 .name = "gpll6",
 310                 .parent_data = &(const struct clk_parent_data) {
 311                         .fw_name = "xo",
 312                 },
 313                 .num_parents = 1,
 314                 .ops = &clk_pll_ops,
 315         },
 316 };
 317
 318 static struct clk_regmap gpll6_vote = {
 319         .enable_reg = 0x45000,
 320         .enable_mask = BIT(7),
 321         .hw.init = &(struct clk_init_data){
 322                 .name = "gpll6_vote",
 323                 .parent_hws = (const struct clk_hw*[]) {
 324                         &gpll6.clkr.hw,
 325                 },
 326                 .num_parents = 1,
 327                 .ops = &clk_pll_vote_ops,
 328         },
 329 };
 330
 331 static const struct parent_map gcc_xo_gpll0_map[] = {
 332         { P_XO, 0 },
 333         { P_GPLL0, 1 },
 334 };
 335
 336 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
 337         { .fw_name = "xo" },
 338         { .hw = &gpll0_vote.hw },
 339 };
 340
 341 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 342         { P_XO, 0 },
 343         { P_GPLL0, 1 },
 344         { P_BIMC, 2 },
 345 };
 346
 347 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
 348         { .fw_name = "xo" },
 349         { .hw = &gpll0_vote.hw },
 350         { .hw = &bimc_pll_vote.hw },
 351 };
 352
 353 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
 354         { P_XO, 0 },
 355         { P_GPLL0, 1 },
 356         { P_GPLL6_AUX, 2 },
 357 };
 358
 359 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
 360         { .fw_name = "xo" },
 361         { .hw = &gpll0_vote.hw },
 362         { .hw = &gpll6_vote.hw },
 363 };
 364
 365 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
 366         { P_XO, 0 },
 367         { P_GPLL0, 1 },
 368         { P_GPLL2_AUX, 4 },
 369         { P_GPLL3, 2 },
 370         { P_GPLL6_AUX, 3 },
 371 };
 372
 373 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
 374         { .fw_name = "xo" },
 375         { .hw = &gpll0_vote.hw },
 376         { .hw = &gpll2_vote.hw },
 377         { .hw = &gpll3_vote.hw },
 378         { .hw = &gpll6_vote.hw },
 379 };
 380
 381 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 382         { P_XO, 0 },
 383         { P_GPLL0, 1 },
 384         { P_GPLL2, 2 },
 385 };
 386
 387 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
 388         { .fw_name = "xo" },
 389         { .hw = &gpll0_vote.hw },
 390         { .hw = &gpll2_vote.hw },
 391 };
 392
 393 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 394         { P_XO, 0 },
 395         { P_GPLL0, 1 },
 396         { P_GPLL2, 3 },
 397         { P_GPLL4, 2 },
 398 };
 399
 400 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
 401         { .fw_name = "xo" },
 402         { .hw = &gpll0_vote.hw },
 403         { .hw = &gpll2_vote.hw },
 404         { .hw = &gpll4_vote.hw },
 405 };
 406
 407 static const struct parent_map gcc_xo_gpll0a_map[] = {
 408         { P_XO, 0 },
 409         { P_GPLL0_AUX, 2 },
 410 };
 411
 412 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
 413         { .fw_name = "xo" },
 414         { .hw = &gpll0_vote.hw },
 415 };
 416
 417 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 418         { P_XO, 0 },
 419         { P_GPLL0, 1 },
 420         { P_GPLL1_AUX, 2 },
 421         { P_SLEEP_CLK, 6 },
 422 };
 423
 424 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
 425         { .fw_name = "xo" },
 426         { .hw = &gpll0_vote.hw },
 427         { .hw = &gpll1_vote.hw },
 428         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 429 };
 430
 431 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
 432         { P_XO, 0 },
 433         { P_GPLL0, 1 },
 434         { P_GPLL1_AUX, 2 },
 435         { P_GPLL6, 2 },
 436         { P_SLEEP_CLK, 6 },
 437 };
 438
 439 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
 440         { .fw_name = "xo" },
 441         { .hw = &gpll0_vote.hw },
 442         { .hw = &gpll1_vote.hw },
 443         { .hw = &gpll6_vote.hw },
 444         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 445 };
 446
 447 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 448         { P_XO, 0 },
 449         { P_GPLL0, 1 },
 450         { P_GPLL1_AUX, 2 },
 451 };
 452
 453 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
 454         { .fw_name = "xo" },
 455         { .hw = &gpll0_vote.hw },
 456         { .hw = &gpll1_vote.hw },
 457 };
 458
 459 static const struct parent_map gcc_xo_dsibyte_map[] = {
 460         { P_XO, 0, },
 461         { P_DSI0_PHYPLL_BYTE, 2 },
 462 };
 463
 464 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
 465         { .fw_name = "xo" },
 466         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 467 };
 468
 469 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 470         { P_XO, 0 },
 471         { P_GPLL0_AUX, 2 },
 472         { P_DSI0_PHYPLL_BYTE, 1 },
 473 };
 474
 475 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
 476         { .fw_name = "xo" },
 477         { .hw = &gpll0_vote.hw },
 478         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 479 };
 480
 481 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
 482         { P_XO, 0 },
 483         { P_GPLL1, 1 },
 484         { P_DSI0_PHYPLL_DSI, 2 },
 485         { P_GPLL6, 3 },
 486         { P_GPLL3_AUX, 4 },
 487         { P_GPLL0_AUX, 5 },
 488 };
 489
 490 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
 491         { .fw_name = "xo" },
 492         { .hw = &gpll1_vote.hw },
 493         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 494         { .hw = &gpll6_vote.hw },
 495         { .hw = &gpll3_vote.hw },
 496         { .hw = &gpll0_vote.hw },
 497 };
 498
 499 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 500         { P_XO, 0 },
 501         { P_GPLL0_AUX, 2 },
 502         { P_DSI0_PHYPLL_DSI, 1 },
 503 };
 504
 505 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
 506         { .fw_name = "xo" },
 507         { .hw = &gpll0_vote.hw },
 508         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 509 };
 510
 511 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
 512         { P_XO, 0 },
 513         { P_GPLL0, 1 },
 514         { P_GPLL5_AUX, 3 },
 515         { P_GPLL6, 2 },
 516         { P_BIMC, 4 },
 517 };
 518
 519 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
 520         { .fw_name = "xo" },
 521         { .hw = &gpll0_vote.hw },
 522         { .hw = &gpll5_vote.hw },
 523         { .hw = &gpll6_vote.hw },
 524         { .hw = &bimc_pll_vote.hw },
 525 };
 526
 527 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 528         { P_XO, 0 },
 529         { P_GPLL0, 1 },
 530         { P_GPLL1, 2 },
 531         { P_SLEEP_CLK, 6 }
 532 };
 533
 534 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
 535         { .fw_name = "xo" },
 536         { .hw = &gpll0_vote.hw },
 537         { .hw = &gpll1_vote.hw },
 538         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 539 };
 540
 541 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 542         { P_XO, 0 },
 543         { P_GPLL1, 1 },
 544         { P_EXT_PRI_I2S, 2 },
 545         { P_EXT_MCLK, 3 },
 546         { P_SLEEP_CLK, 6 }
 547 };
 548
 549 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
 550         { .fw_name = "xo" },
 551         { .hw = &gpll0_vote.hw },
 552         { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 553         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 554         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 555 };
 556
 557 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 558         { P_XO, 0 },
 559         { P_GPLL1, 1 },
 560         { P_EXT_SEC_I2S, 2 },
 561         { P_EXT_MCLK, 3 },
 562         { P_SLEEP_CLK, 6 }
 563 };
 564
 565 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
 566         { .fw_name = "xo" },
 567         { .hw = &gpll1_vote.hw },
 568         { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 569         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 570         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 571 };
 572
 573 static const struct parent_map gcc_xo_sleep_map[] = {
 574         { P_XO, 0 },
 575         { P_SLEEP_CLK, 6 }
 576 };
 577
 578 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
 579         { .fw_name = "xo" },
 580         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 581 };
 582
 583 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 584         { P_XO, 0 },
 585         { P_GPLL1, 1 },
 586         { P_EXT_MCLK, 2 },
 587         { P_SLEEP_CLK, 6 }
 588 };
 589
 590 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
 591         { .fw_name = "xo" },
 592         { .hw = &gpll1_vote.hw },
 593         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 594         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 595 };
 596
 597 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
 598         { .fw_name = "xo" },
 599         { .hw = &gpll6_vote.hw },
 600         { .hw = &gpll0_vote.hw },
 601 };
 602
 603 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
 604         { .fw_name = "xo" },
 605         { .hw = &gpll6_vote.hw },
 606         { .hw = &gpll0_vote.hw },
 607 };
 608
 609 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 610         .cmd_rcgr = 0x27000,
 611         .hid_width = 5,
 612         .parent_map = gcc_xo_gpll0_map,
 613         .clkr.hw.init = &(struct clk_init_data){
 614                 .name = "pcnoc_bfdcd_clk_src",
 615                 .parent_data = gcc_xo_gpll0_parent_data,
 616                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 617                 .ops = &clk_rcg2_ops,
 618         },
 619 };
 620
 621 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 622         .cmd_rcgr = 0x26004,
 623         .hid_width = 5,
 624         .parent_map = gcc_xo_gpll0_gpll6a_map,
 625         .clkr.hw.init = &(struct clk_init_data){
 626                 .name = "system_noc_bfdcd_clk_src",
 627                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 628                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 629                 .ops = &clk_rcg2_ops,
 630         },
 631 };
 632
 633 static struct clk_rcg2 bimc_ddr_clk_src = {
 634         .cmd_rcgr = 0x32024,
 635         .hid_width = 5,
 636         .parent_map = gcc_xo_gpll0_bimc_map,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "bimc_ddr_clk_src",
 639                 .parent_data = gcc_xo_gpll0_bimc_parent_data,
 640                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
 641                 .ops = &clk_rcg2_ops,
 642                 .flags = CLK_GET_RATE_NOCACHE,
 643         },
 644 };
 645
 646 static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
 647         .cmd_rcgr = 0x2600c,
 648         .hid_width = 5,
 649         .parent_map = gcc_xo_gpll0_gpll6a_map,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "system_mm_noc_bfdcd_clk_src",
 652                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 653                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
 654                 .ops = &clk_rcg2_ops,
 655         },
 656 };
 657
 658 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 659         F(40000000, P_GPLL0, 10, 1, 2),
 660         F(80000000, P_GPLL0, 10, 0, 0),
 661         { }
 662 };
 663
 664 static struct clk_rcg2 camss_ahb_clk_src = {
 665         .cmd_rcgr = 0x5a000,
 666         .mnd_width = 8,
 667         .hid_width = 5,
 668         .parent_map = gcc_xo_gpll0_map,
 669         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 670         .clkr.hw.init = &(struct clk_init_data){
 671                 .name = "camss_ahb_clk_src",
 672                 .parent_data = gcc_xo_gpll0_parent_data,
 673                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 674                 .ops = &clk_rcg2_ops,
 675         },
 676 };
 677
 678 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 679         F(19200000, P_XO, 1, 0, 0),
 680         F(50000000, P_GPLL0, 16, 0, 0),
 681         F(100000000, P_GPLL0, 8, 0, 0),
 682         F(133330000, P_GPLL0, 6, 0, 0),
 683         { }
 684 };
 685
 686 static struct clk_rcg2 apss_ahb_clk_src = {
 687         .cmd_rcgr = 0x46000,
 688         .hid_width = 5,
 689         .parent_map = gcc_xo_gpll0_map,
 690         .freq_tbl = ftbl_apss_ahb_clk,
 691         .clkr.hw.init = &(struct clk_init_data){
 692                 .name = "apss_ahb_clk_src",
 693                 .parent_data = gcc_xo_gpll0_parent_data,
 694                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 695                 .ops = &clk_rcg2_ops,
 696         },
 697 };
 698
 699 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 700         F(100000000, P_GPLL0, 8, 0,     0),
 701         F(200000000, P_GPLL0, 4, 0,     0),
 702         { }
 703 };
 704
 705 static struct clk_rcg2 csi0_clk_src = {
 706         .cmd_rcgr = 0x4e020,
 707         .hid_width = 5,
 708         .parent_map = gcc_xo_gpll0_map,
 709         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 710         .clkr.hw.init = &(struct clk_init_data){
 711                 .name = "csi0_clk_src",
 712                 .parent_data = gcc_xo_gpll0_parent_data,
 713                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 714                 .ops = &clk_rcg2_ops,
 715         },
 716 };
 717
 718 static struct clk_rcg2 csi1_clk_src = {
 719         .cmd_rcgr = 0x4f020,
 720         .hid_width = 5,
 721         .parent_map = gcc_xo_gpll0_map,
 722         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 723         .clkr.hw.init = &(struct clk_init_data){
 724                 .name = "csi1_clk_src",
 725                 .parent_data = gcc_xo_gpll0_parent_data,
 726                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 727                 .ops = &clk_rcg2_ops,
 728         },
 729 };
 730
 731 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 732         F(19200000, P_XO, 1, 0, 0),
 733         F(50000000, P_GPLL0, 16, 0, 0),
 734         F(80000000, P_GPLL0, 10, 0, 0),
 735         F(100000000, P_GPLL0, 8, 0, 0),
 736         F(160000000, P_GPLL0, 5, 0, 0),
 737         F(200000000, P_GPLL0, 4, 0, 0),
 738         F(220000000, P_GPLL3, 5, 0, 0),
 739         F(266670000, P_GPLL0, 3, 0, 0),
 740         F(310000000, P_GPLL2_AUX, 3, 0, 0),
 741         F(400000000, P_GPLL0, 2, 0, 0),
 742         F(465000000, P_GPLL2_AUX, 2, 0, 0),
 743         F(550000000, P_GPLL3, 2, 0, 0),
 744         { }
 745 };
 746
 747 static struct clk_rcg2 gfx3d_clk_src = {
 748         .cmd_rcgr = 0x59000,
 749         .hid_width = 5,
 750         .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
 751         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 752         .clkr.hw.init = &(struct clk_init_data){
 753                 .name = "gfx3d_clk_src",
 754                 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
 755                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
 756                 .ops = &clk_rcg2_ops,
 757         },
 758 };
 759
 760 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 761         F(50000000, P_GPLL0, 16, 0, 0),
 762         F(80000000, P_GPLL0, 10, 0, 0),
 763         F(100000000, P_GPLL0, 8, 0, 0),
 764         F(160000000, P_GPLL0, 5, 0, 0),
 765         F(177780000, P_GPLL0, 4.5, 0, 0),
 766         F(200000000, P_GPLL0, 4, 0, 0),
 767         F(266670000, P_GPLL0, 3, 0, 0),
 768         F(320000000, P_GPLL0, 2.5, 0, 0),
 769         F(400000000, P_GPLL0, 2, 0, 0),
 770         F(465000000, P_GPLL2, 2, 0, 0),
 771         F(480000000, P_GPLL4, 2.5, 0, 0),
 772         F(600000000, P_GPLL4, 2, 0, 0),
 773         { }
 774 };
 775
 776 static struct clk_rcg2 vfe0_clk_src = {
 777         .cmd_rcgr = 0x58000,
 778         .hid_width = 5,
 779         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
 780         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 781         .clkr.hw.init = &(struct clk_init_data){
 782                 .name = "vfe0_clk_src",
 783                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
 784                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
 785                 .ops = &clk_rcg2_ops,
 786         },
 787 };
 788
 789 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 790         F(19200000, P_XO, 1, 0, 0),
 791         F(50000000, P_GPLL0, 16, 0, 0),
 792         { }
 793 };
 794
 795 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 796         .cmd_rcgr = 0x0200c,
 797         .hid_width = 5,
 798         .parent_map = gcc_xo_gpll0_map,
 799         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 800         .clkr.hw.init = &(struct clk_init_data){
 801                 .name = "blsp1_qup1_i2c_apps_clk_src",
 802                 .parent_data = gcc_xo_gpll0_parent_data,
 803                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 809         F(960000, P_XO, 10, 1, 2),
 810         F(4800000, P_XO, 4, 0, 0),
 811         F(9600000, P_XO, 2, 0, 0),
 812         F(16000000, P_GPLL0, 10, 1, 5),
 813         F(19200000, P_XO, 1, 0, 0),
 814         F(25000000, P_GPLL0, 16, 1, 2),
 815         F(50000000, P_GPLL0, 16, 0, 0),
 816         { }
 817 };
 818
 819 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 820         .cmd_rcgr = 0x02024,
 821         .mnd_width = 8,
 822         .hid_width = 5,
 823         .parent_map = gcc_xo_gpll0_map,
 824         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 825         .clkr.hw.init = &(struct clk_init_data){
 826                 .name = "blsp1_qup1_spi_apps_clk_src",
 827                 .parent_data = gcc_xo_gpll0_parent_data,
 828                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 829                 .ops = &clk_rcg2_ops,
 830         },
 831 };
 832
 833 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 834         .cmd_rcgr = 0x03000,
 835         .hid_width = 5,
 836         .parent_map = gcc_xo_gpll0_map,
 837         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 838         .clkr.hw.init = &(struct clk_init_data){
 839                 .name = "blsp1_qup2_i2c_apps_clk_src",
 840                 .parent_data = gcc_xo_gpll0_parent_data,
 841                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 842                 .ops = &clk_rcg2_ops,
 843         },
 844 };
 845
 846 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 847         .cmd_rcgr = 0x03014,
 848         .mnd_width = 8,
 849         .hid_width = 5,
 850         .parent_map = gcc_xo_gpll0_map,
 851         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 852         .clkr.hw.init = &(struct clk_init_data){
 853                 .name = "blsp1_qup2_spi_apps_clk_src",
 854                 .parent_data = gcc_xo_gpll0_parent_data,
 855                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 856                 .ops = &clk_rcg2_ops,
 857         },
 858 };
 859
 860 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 861         .cmd_rcgr = 0x04000,
 862         .hid_width = 5,
 863         .parent_map = gcc_xo_gpll0_map,
 864         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 865         .clkr.hw.init = &(struct clk_init_data){
 866                 .name = "blsp1_qup3_i2c_apps_clk_src",
 867                 .parent_data = gcc_xo_gpll0_parent_data,
 868                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 869                 .ops = &clk_rcg2_ops,
 870         },
 871 };
 872
 873 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 874         .cmd_rcgr = 0x04024,
 875         .mnd_width = 8,
 876         .hid_width = 5,
 877         .parent_map = gcc_xo_gpll0_map,
 878         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 879         .clkr.hw.init = &(struct clk_init_data){
 880                 .name = "blsp1_qup3_spi_apps_clk_src",
 881                 .parent_data = gcc_xo_gpll0_parent_data,
 882                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 883                 .ops = &clk_rcg2_ops,
 884         },
 885 };
 886
 887 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 888         .cmd_rcgr = 0x05000,
 889         .hid_width = 5,
 890         .parent_map = gcc_xo_gpll0_map,
 891         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 892         .clkr.hw.init = &(struct clk_init_data){
 893                 .name = "blsp1_qup4_i2c_apps_clk_src",
 894                 .parent_data = gcc_xo_gpll0_parent_data,
 895                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 896                 .ops = &clk_rcg2_ops,
 897         },
 898 };
 899
 900 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 901         .cmd_rcgr = 0x05024,
 902         .mnd_width = 8,
 903         .hid_width = 5,
 904         .parent_map = gcc_xo_gpll0_map,
 905         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 906         .clkr.hw.init = &(struct clk_init_data){
 907                 .name = "blsp1_qup4_spi_apps_clk_src",
 908                 .parent_data = gcc_xo_gpll0_parent_data,
 909                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 910                 .ops = &clk_rcg2_ops,
 911         },
 912 };
 913
 914 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 915         .cmd_rcgr = 0x06000,
 916         .hid_width = 5,
 917         .parent_map = gcc_xo_gpll0_map,
 918         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 919         .clkr.hw.init = &(struct clk_init_data){
 920                 .name = "blsp1_qup5_i2c_apps_clk_src",
 921                 .parent_data = gcc_xo_gpll0_parent_data,
 922                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 923                 .ops = &clk_rcg2_ops,
 924         },
 925 };
 926
 927 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 928         .cmd_rcgr = 0x06024,
 929         .mnd_width = 8,
 930         .hid_width = 5,
 931         .parent_map = gcc_xo_gpll0_map,
 932         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 933         .clkr.hw.init = &(struct clk_init_data){
 934                 .name = "blsp1_qup5_spi_apps_clk_src",
 935                 .parent_data = gcc_xo_gpll0_parent_data,
 936                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 937                 .ops = &clk_rcg2_ops,
 938         },
 939 };
 940
 941 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 942         .cmd_rcgr = 0x07000,
 943         .hid_width = 5,
 944         .parent_map = gcc_xo_gpll0_map,
 945         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 946         .clkr.hw.init = &(struct clk_init_data){
 947                 .name = "blsp1_qup6_i2c_apps_clk_src",
 948                 .parent_data = gcc_xo_gpll0_parent_data,
 949                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 950                 .ops = &clk_rcg2_ops,
 951         },
 952 };
 953
 954 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 955         .cmd_rcgr = 0x07024,
 956         .mnd_width = 8,
 957         .hid_width = 5,
 958         .parent_map = gcc_xo_gpll0_map,
 959         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 960         .clkr.hw.init = &(struct clk_init_data){
 961                 .name = "blsp1_qup6_spi_apps_clk_src",
 962                 .parent_data = gcc_xo_gpll0_parent_data,
 963                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 964                 .ops = &clk_rcg2_ops,
 965         },
 966 };
 967
 968 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 969         F(3686400, P_GPLL0, 1, 72, 15625),
 970         F(7372800, P_GPLL0, 1, 144, 15625),
 971         F(14745600, P_GPLL0, 1, 288, 15625),
 972         F(16000000, P_GPLL0, 10, 1, 5),
 973         F(19200000, P_XO, 1, 0, 0),
 974         F(24000000, P_GPLL0, 1, 3, 100),
 975         F(25000000, P_GPLL0, 16, 1, 2),
 976         F(32000000, P_GPLL0, 1, 1, 25),
 977         F(40000000, P_GPLL0, 1, 1, 20),
 978         F(46400000, P_GPLL0, 1, 29, 500),
 979         F(48000000, P_GPLL0, 1, 3, 50),
 980         F(51200000, P_GPLL0, 1, 8, 125),
 981         F(56000000, P_GPLL0, 1, 7, 100),
 982         F(58982400, P_GPLL0, 1, 1152, 15625),
 983         F(60000000, P_GPLL0, 1, 3, 40),
 984         { }
 985 };
 986
 987 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 988         .cmd_rcgr = 0x02044,
 989         .mnd_width = 16,
 990         .hid_width = 5,
 991         .parent_map = gcc_xo_gpll0_map,
 992         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 993         .clkr.hw.init = &(struct clk_init_data){
 994                 .name = "blsp1_uart1_apps_clk_src",
 995                 .parent_data = gcc_xo_gpll0_parent_data,
 996                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
 997                 .ops = &clk_rcg2_ops,
 998         },
 999 };
1000
1001 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1002         .cmd_rcgr = 0x03034,
1003         .mnd_width = 16,
1004         .hid_width = 5,
1005         .parent_map = gcc_xo_gpll0_map,
1006         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
1007         .clkr.hw.init = &(struct clk_init_data){
1008                 .name = "blsp1_uart2_apps_clk_src",
1009                 .parent_data = gcc_xo_gpll0_parent_data,
1010                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1011                 .ops = &clk_rcg2_ops,
1012         },
1013 };
1014
1015 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1016         F(19200000, P_XO, 1, 0, 0),
1017         F(37500000, P_GPLL0, 1, 3, 64),
1018         { }
1019 };
1020
1021 static struct clk_rcg2 cci_clk_src = {
1022         .cmd_rcgr = 0x51000,
1023         .mnd_width = 8,
1024         .hid_width = 5,
1025         .parent_map = gcc_xo_gpll0a_map,
1026         .freq_tbl = ftbl_gcc_camss_cci_clk,
1027         .clkr.hw.init = &(struct clk_init_data){
1028                 .name = "cci_clk_src",
1029                 .parent_data = gcc_xo_gpll0a_parent_data,
1030                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1031                 .ops = &clk_rcg2_ops,
1032         },
1033 };
1034
1035 /*
1036  * This is a frequency table for "General Purpose" clocks.
1037  * These clocks can be muxed to the SoC pins and may be used by
1038  * external devices. They're often used as PWM source.
1039  *
1040  * See comment at ftbl_gcc_gp1_3_clk.
1041  */
1042 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1043         F(10000,   P_XO,    16,  1, 120),
1044         F(100000,  P_XO,    16,  1,  12),
1045         F(500000,  P_GPLL0, 16,  1, 100),
1046         F(1000000, P_GPLL0, 16,  1,  50),
1047         F(2500000, P_GPLL0, 16,  1,  20),
1048         F(5000000, P_GPLL0, 16,  1,  10),
1049         F(100000000, P_GPLL0, 8, 0, 0),
1050         F(200000000, P_GPLL0, 4, 0, 0),
1051         { }
1052 };
1053
1054 static struct clk_rcg2 camss_gp0_clk_src = {
1055         .cmd_rcgr = 0x54000,
1056         .mnd_width = 8,
1057         .hid_width = 5,
1058         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1059         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1060         .clkr.hw.init = &(struct clk_init_data){
1061                 .name = "camss_gp0_clk_src",
1062                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1063                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1064                 .ops = &clk_rcg2_ops,
1065         },
1066 };
1067
1068 static struct clk_rcg2 camss_gp1_clk_src = {
1069         .cmd_rcgr = 0x55000,
1070         .mnd_width = 8,
1071         .hid_width = 5,
1072         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1073         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1074         .clkr.hw.init = &(struct clk_init_data){
1075                 .name = "camss_gp1_clk_src",
1076                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1077                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1078                 .ops = &clk_rcg2_ops,
1079         },
1080 };
1081
1082 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1083         F(133330000, P_GPLL0, 6, 0,     0),
1084         F(266670000, P_GPLL0, 3, 0,     0),
1085         F(320000000, P_GPLL0, 2.5, 0, 0),
1086         { }
1087 };
1088
1089 static struct clk_rcg2 jpeg0_clk_src = {
1090         .cmd_rcgr = 0x57000,
1091         .hid_width = 5,
1092         .parent_map = gcc_xo_gpll0_map,
1093         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1094         .clkr.hw.init = &(struct clk_init_data){
1095                 .name = "jpeg0_clk_src",
1096                 .parent_data = gcc_xo_gpll0_parent_data,
1097                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1098                 .ops = &clk_rcg2_ops,
1099         },
1100 };
1101
1102 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1103         F(24000000, P_GPLL0, 1, 1, 45),
1104         F(66670000, P_GPLL0, 12, 0, 0),
1105         { }
1106 };
1107
1108 static struct clk_rcg2 mclk0_clk_src = {
1109         .cmd_rcgr = 0x52000,
1110         .mnd_width = 8,
1111         .hid_width = 5,
1112         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1113         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1114         .clkr.hw.init = &(struct clk_init_data){
1115                 .name = "mclk0_clk_src",
1116                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1117                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1118                 .ops = &clk_rcg2_ops,
1119         },
1120 };
1121
1122 static struct clk_rcg2 mclk1_clk_src = {
1123         .cmd_rcgr = 0x53000,
1124         .mnd_width = 8,
1125         .hid_width = 5,
1126         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1127         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1128         .clkr.hw.init = &(struct clk_init_data){
1129                 .name = "mclk1_clk_src",
1130                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1131                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
1132                 .ops = &clk_rcg2_ops,
1133         },
1134 };
1135
1136 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1137         F(100000000, P_GPLL0, 8, 0,     0),
1138         F(200000000, P_GPLL0, 4, 0,     0),
1139         { }
1140 };
1141
1142 static struct clk_rcg2 csi0phytimer_clk_src = {
1143         .cmd_rcgr = 0x4e000,
1144         .hid_width = 5,
1145         .parent_map = gcc_xo_gpll0_gpll1a_map,
1146         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1147         .clkr.hw.init = &(struct clk_init_data){
1148                 .name = "csi0phytimer_clk_src",
1149                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1150                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1151                 .ops = &clk_rcg2_ops,
1152         },
1153 };
1154
1155 static struct clk_rcg2 csi1phytimer_clk_src = {
1156         .cmd_rcgr = 0x4f000,
1157         .hid_width = 5,
1158         .parent_map = gcc_xo_gpll0_gpll1a_map,
1159         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1160         .clkr.hw.init = &(struct clk_init_data){
1161                 .name = "csi1phytimer_clk_src",
1162                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1163                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
1164                 .ops = &clk_rcg2_ops,
1165         },
1166 };
1167
1168 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1169         F(160000000, P_GPLL0, 5, 0, 0),
1170         F(200000000, P_GPLL0, 4, 0, 0),
1171         F(228570000, P_GPLL0, 3.5, 0, 0),
1172         F(266670000, P_GPLL0, 3, 0, 0),
1173         F(320000000, P_GPLL0, 2.5, 0, 0),
1174         F(465000000, P_GPLL2, 2, 0, 0),
1175         { }
1176 };
1177
1178 static struct clk_rcg2 cpp_clk_src = {
1179         .cmd_rcgr = 0x58018,
1180         .hid_width = 5,
1181         .parent_map = gcc_xo_gpll0_gpll2_map,
1182         .freq_tbl = ftbl_gcc_camss_cpp_clk,
1183         .clkr.hw.init = &(struct clk_init_data){
1184                 .name = "cpp_clk_src",
1185                 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1186                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
1187                 .ops = &clk_rcg2_ops,
1188         },
1189 };
1190
1191 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1192         F(50000000, P_GPLL0, 16, 0, 0),
1193         F(80000000, P_GPLL0, 10, 0, 0),
1194         F(100000000, P_GPLL0, 8, 0, 0),
1195         F(160000000, P_GPLL0, 5, 0, 0),
1196         { }
1197 };
1198
1199 /* This is not in the documentation but is in the downstream driver */
1200 static struct clk_rcg2 crypto_clk_src = {
1201         .cmd_rcgr = 0x16004,
1202         .hid_width = 5,
1203         .parent_map = gcc_xo_gpll0_map,
1204         .freq_tbl = ftbl_gcc_crypto_clk,
1205         .clkr.hw.init = &(struct clk_init_data){
1206                 .name = "crypto_clk_src",
1207                 .parent_data = gcc_xo_gpll0_parent_data,
1208                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1209                 .ops = &clk_rcg2_ops,
1210         },
1211 };
1212
1213 /*
1214  * This is a frequency table for "General Purpose" clocks.
1215  * These clocks can be muxed to the SoC pins and may be used by
1216  * external devices. They're often used as PWM source.
1217  *
1218  * Please note that MND divider must be enabled for duty-cycle
1219  * control to be possible. (M != N) Also since D register is configured
1220  * with a value multiplied by 2, and duty cycle is calculated as
1221  *                             (2 * D) % 2^W
1222  *                DutyCycle = ----------------
1223  *                              2 * (N % 2^W)
1224  * (where W = .mnd_width)
1225  * N must be half or less than maximum value for the register.
1226  * Otherwise duty-cycle control would be limited.
1227  * (e.g. for 8-bit NMD N should be less than 128)
1228  */
1229 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1230         F(10000,   P_XO,    16,  1, 120),
1231         F(100000,  P_XO,    16,  1,  12),
1232         F(500000,  P_GPLL0, 16,  1, 100),
1233         F(1000000, P_GPLL0, 16,  1,  50),
1234         F(2500000, P_GPLL0, 16,  1,  20),
1235         F(5000000, P_GPLL0, 16,  1,  10),
1236         F(19200000, P_XO, 1, 0, 0),
1237         { }
1238 };
1239
1240 static struct clk_rcg2 gp1_clk_src = {
1241         .cmd_rcgr = 0x08004,
1242         .mnd_width = 8,
1243         .hid_width = 5,
1244         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1245         .freq_tbl = ftbl_gcc_gp1_3_clk,
1246         .clkr.hw.init = &(struct clk_init_data){
1247                 .name = "gp1_clk_src",
1248                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1249                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1250                 .ops = &clk_rcg2_ops,
1251         },
1252 };
1253
1254 static struct clk_rcg2 gp2_clk_src = {
1255         .cmd_rcgr = 0x09004,
1256         .mnd_width = 8,
1257         .hid_width = 5,
1258         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1259         .freq_tbl = ftbl_gcc_gp1_3_clk,
1260         .clkr.hw.init = &(struct clk_init_data){
1261                 .name = "gp2_clk_src",
1262                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1263                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1264                 .ops = &clk_rcg2_ops,
1265         },
1266 };
1267
1268 static struct clk_rcg2 gp3_clk_src = {
1269         .cmd_rcgr = 0x0a004,
1270         .mnd_width = 8,
1271         .hid_width = 5,
1272         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1273         .freq_tbl = ftbl_gcc_gp1_3_clk,
1274         .clkr.hw.init = &(struct clk_init_data){
1275                 .name = "gp3_clk_src",
1276                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1277                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
1278                 .ops = &clk_rcg2_ops,
1279         },
1280 };
1281
1282 static struct clk_rcg2 byte0_clk_src = {
1283         .cmd_rcgr = 0x4d044,
1284         .hid_width = 5,
1285         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1286         .clkr.hw.init = &(struct clk_init_data){
1287                 .name = "byte0_clk_src",
1288                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1289                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1290                 .ops = &clk_byte2_ops,
1291                 .flags = CLK_SET_RATE_PARENT,
1292         },
1293 };
1294
1295 static struct clk_rcg2 byte1_clk_src = {
1296         .cmd_rcgr = 0x4d0b0,
1297         .hid_width = 5,
1298         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1299         .clkr.hw.init = &(struct clk_init_data){
1300                 .name = "byte1_clk_src",
1301                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1302                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
1303                 .ops = &clk_byte2_ops,
1304                 .flags = CLK_SET_RATE_PARENT,
1305         },
1306 };
1307
1308 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1309         F(19200000, P_XO, 1, 0, 0),
1310         { }
1311 };
1312
1313 static struct clk_rcg2 esc0_clk_src = {
1314         .cmd_rcgr = 0x4d060,
1315         .hid_width = 5,
1316         .parent_map = gcc_xo_dsibyte_map,
1317         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1318         .clkr.hw.init = &(struct clk_init_data){
1319                 .name = "esc0_clk_src",
1320                 .parent_data = gcc_xo_dsibyte_parent_data,
1321                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1322                 .ops = &clk_rcg2_ops,
1323         },
1324 };
1325
1326 static struct clk_rcg2 esc1_clk_src = {
1327         .cmd_rcgr = 0x4d0a8,
1328         .hid_width = 5,
1329         .parent_map = gcc_xo_dsibyte_map,
1330         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1331         .clkr.hw.init = &(struct clk_init_data){
1332                 .name = "esc1_clk_src",
1333                 .parent_data = gcc_xo_dsibyte_parent_data,
1334                 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
1335                 .ops = &clk_rcg2_ops,
1336         },
1337 };
1338
1339 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1340         F(50000000, P_GPLL0_AUX, 16, 0, 0),
1341         F(80000000, P_GPLL0_AUX, 10, 0, 0),
1342         F(100000000, P_GPLL0_AUX, 8, 0, 0),
1343         F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1344         F(153600000, P_GPLL0, 4, 0, 0),
1345         F(160000000, P_GPLL0_AUX, 5, 0, 0),
1346         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1347         F(200000000, P_GPLL0_AUX, 4, 0, 0),
1348         F(266670000, P_GPLL0_AUX, 3, 0, 0),
1349         F(307200000, P_GPLL1, 2, 0, 0),
1350         F(366670000, P_GPLL3_AUX, 3, 0, 0),
1351         { }
1352 };
1353
1354 static struct clk_rcg2 mdp_clk_src = {
1355         .cmd_rcgr = 0x4d014,
1356         .hid_width = 5,
1357         .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1358         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1359         .clkr.hw.init = &(struct clk_init_data){
1360                 .name = "mdp_clk_src",
1361                 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1362                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
1363                 .ops = &clk_rcg2_ops,
1364         },
1365 };
1366
1367 static struct clk_rcg2 pclk0_clk_src = {
1368         .cmd_rcgr = 0x4d000,
1369         .mnd_width = 8,
1370         .hid_width = 5,
1371         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1372         .clkr.hw.init = &(struct clk_init_data){
1373                 .name = "pclk0_clk_src",
1374                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1375                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1376                 .ops = &clk_pixel_ops,
1377                 .flags = CLK_SET_RATE_PARENT,
1378         },
1379 };
1380
1381 static struct clk_rcg2 pclk1_clk_src = {
1382         .cmd_rcgr = 0x4d0b8,
1383         .mnd_width = 8,
1384         .hid_width = 5,
1385         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1386         .clkr.hw.init = &(struct clk_init_data){
1387                 .name = "pclk1_clk_src",
1388                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1389                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
1390                 .ops = &clk_pixel_ops,
1391                 .flags = CLK_SET_RATE_PARENT,
1392         },
1393 };
1394
1395 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1396         F(19200000, P_XO, 1, 0, 0),
1397         { }
1398 };
1399
1400 static struct clk_rcg2 vsync_clk_src = {
1401         .cmd_rcgr = 0x4d02c,
1402         .hid_width = 5,
1403         .parent_map = gcc_xo_gpll0a_map,
1404         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1405         .clkr.hw.init = &(struct clk_init_data){
1406                 .name = "vsync_clk_src",
1407                 .parent_data = gcc_xo_gpll0a_parent_data,
1408                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
1409                 .ops = &clk_rcg2_ops,
1410         },
1411 };
1412
1413 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1414         F(64000000, P_GPLL0, 12.5, 0, 0),
1415         { }
1416 };
1417
1418 /* This is not in the documentation but is in the downstream driver */
1419 static struct clk_rcg2 pdm2_clk_src = {
1420         .cmd_rcgr = 0x44010,
1421         .hid_width = 5,
1422         .parent_map = gcc_xo_gpll0_map,
1423         .freq_tbl = ftbl_gcc_pdm2_clk,
1424         .clkr.hw.init = &(struct clk_init_data){
1425                 .name = "pdm2_clk_src",
1426                 .parent_data = gcc_xo_gpll0_parent_data,
1427                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1428                 .ops = &clk_rcg2_ops,
1429         },
1430 };
1431
1432 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1433         F(144000, P_XO, 16, 3, 25),
1434         F(400000, P_XO, 12, 1, 4),
1435         F(20000000, P_GPLL0, 10, 1, 4),
1436         F(25000000, P_GPLL0, 16, 1, 2),
1437         F(50000000, P_GPLL0, 16, 0, 0),
1438         F(100000000, P_GPLL0, 8, 0, 0),
1439         F(177770000, P_GPLL0, 4.5, 0, 0),
1440         F(200000000, P_GPLL0, 4, 0, 0),
1441         { }
1442 };
1443
1444 static struct clk_rcg2 sdcc1_apps_clk_src = {
1445         .cmd_rcgr = 0x42004,
1446         .mnd_width = 8,
1447         .hid_width = 5,
1448         .parent_map = gcc_xo_gpll0_map,
1449         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1450         .clkr.hw.init = &(struct clk_init_data){
1451                 .name = "sdcc1_apps_clk_src",
1452                 .parent_data = gcc_xo_gpll0_parent_data,
1453                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1454                 .ops = &clk_rcg2_floor_ops,
1455         },
1456 };
1457
1458 static struct clk_rcg2 sdcc2_apps_clk_src = {
1459         .cmd_rcgr = 0x43004,
1460         .mnd_width = 8,
1461         .hid_width = 5,
1462         .parent_map = gcc_xo_gpll0_map,
1463         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1464         .clkr.hw.init = &(struct clk_init_data){
1465                 .name = "sdcc2_apps_clk_src",
1466                 .parent_data = gcc_xo_gpll0_parent_data,
1467                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1468                 .ops = &clk_rcg2_floor_ops,
1469         },
1470 };
1471
1472 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1473         F(154285000, P_GPLL6, 7, 0, 0),
1474         F(320000000, P_GPLL0, 2.5, 0, 0),
1475         F(400000000, P_GPLL0, 2, 0, 0),
1476         { }
1477 };
1478
1479 static struct clk_rcg2 apss_tcu_clk_src = {
1480         .cmd_rcgr = 0x1207c,
1481         .hid_width = 5,
1482         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1483         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1484         .clkr.hw.init = &(struct clk_init_data){
1485                 .name = "apss_tcu_clk_src",
1486                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1487                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1488                 .ops = &clk_rcg2_ops,
1489         },
1490 };
1491
1492 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1493         F(19200000, P_XO, 1, 0, 0),
1494         F(100000000, P_GPLL0, 8, 0, 0),
1495         F(200000000, P_GPLL0, 4, 0, 0),
1496         F(266500000, P_BIMC, 4, 0, 0),
1497         F(400000000, P_GPLL0, 2, 0, 0),
1498         F(533000000, P_BIMC, 2, 0, 0),
1499         { }
1500 };
1501
1502 static struct clk_rcg2 bimc_gpu_clk_src = {
1503         .cmd_rcgr = 0x31028,
1504         .hid_width = 5,
1505         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1506         .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1507         .clkr.hw.init = &(struct clk_init_data){
1508                 .name = "bimc_gpu_clk_src",
1509                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1510                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
1511                 .flags = CLK_GET_RATE_NOCACHE,
1512                 .ops = &clk_rcg2_ops,
1513         },
1514 };
1515
1516 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1517         F(57140000, P_GPLL0, 14, 0, 0),
1518         F(80000000, P_GPLL0, 10, 0, 0),
1519         F(100000000, P_GPLL0, 8, 0, 0),
1520         { }
1521 };
1522
1523 static struct clk_rcg2 usb_hs_system_clk_src = {
1524         .cmd_rcgr = 0x41010,
1525         .hid_width = 5,
1526         .parent_map = gcc_xo_gpll0_map,
1527         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1528         .clkr.hw.init = &(struct clk_init_data){
1529                 .name = "usb_hs_system_clk_src",
1530                 .parent_data = gcc_xo_gpll0_parent_data,
1531                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1532                 .ops = &clk_rcg2_ops,
1533         },
1534 };
1535
1536 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1537         F(64000000, P_GPLL0, 12.5, 0, 0),
1538         { }
1539 };
1540
1541 static struct clk_rcg2 usb_fs_system_clk_src = {
1542         .cmd_rcgr = 0x3f010,
1543         .hid_width = 5,
1544         .parent_map = gcc_xo_gpll0_map,
1545         .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1546         .clkr.hw.init = &(struct clk_init_data){
1547                 .name = "usb_fs_system_clk_src",
1548                 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1549                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
1550                 .ops = &clk_rcg2_ops,
1551         },
1552 };
1553
1554 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1555         F(60000000, P_GPLL6, 1, 1, 18),
1556         { }
1557 };
1558
1559 static struct clk_rcg2 usb_fs_ic_clk_src = {
1560         .cmd_rcgr = 0x3f034,
1561         .hid_width = 5,
1562         .parent_map = gcc_xo_gpll0_map,
1563         .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1564         .clkr.hw.init = &(struct clk_init_data){
1565                 .name = "usb_fs_ic_clk_src",
1566                 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1567                 .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
1568                 .ops = &clk_rcg2_ops,
1569         },
1570 };
1571
1572 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1573         F(3200000, P_XO, 6, 0, 0),
1574         F(6400000, P_XO, 3, 0, 0),
1575         F(9600000, P_XO, 2, 0, 0),
1576         F(19200000, P_XO, 1, 0, 0),
1577         F(40000000, P_GPLL0, 10, 1, 2),
1578         F(66670000, P_GPLL0, 12, 0, 0),
1579         F(80000000, P_GPLL0, 10, 0, 0),
1580         F(100000000, P_GPLL0, 8, 0, 0),
1581         { }
1582 };
1583
1584 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1585         .cmd_rcgr = 0x1c010,
1586         .hid_width = 5,
1587         .mnd_width = 8,
1588         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1589         .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1590         .clkr.hw.init = &(struct clk_init_data){
1591                 .name = "ultaudio_ahbfabric_clk_src",
1592                 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1593                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
1594                 .ops = &clk_rcg2_ops,
1595         },
1596 };
1597
1598 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1599         .halt_reg = 0x1c028,
1600         .clkr = {
1601                 .enable_reg = 0x1c028,
1602                 .enable_mask = BIT(0),
1603                 .hw.init = &(struct clk_init_data){
1604                         .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1605                         .parent_hws = (const struct clk_hw*[]){
1606                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1607                         },
1608                         .num_parents = 1,
1609                         .flags = CLK_SET_RATE_PARENT,
1610                         .ops = &clk_branch2_ops,
1611                 },
1612         },
1613 };
1614
1615 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1616         .halt_reg = 0x1c024,
1617         .clkr = {
1618                 .enable_reg = 0x1c024,
1619                 .enable_mask = BIT(0),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1622                         .parent_hws = (const struct clk_hw*[]){
1623                                 &ultaudio_ahbfabric_clk_src.clkr.hw,
1624                         },
1625                         .num_parents = 1,
1626                         .flags = CLK_SET_RATE_PARENT,
1627                         .ops = &clk_branch2_ops,
1628                 },
1629         },
1630 };
1631
1632 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1633         F(128000, P_XO, 10, 1, 15),
1634         F(256000, P_XO, 5, 1, 15),
1635         F(384000, P_XO, 5, 1, 10),
1636         F(512000, P_XO, 5, 2, 15),
1637         F(576000, P_XO, 5, 3, 20),
1638         F(705600, P_GPLL1, 16, 1, 80),
1639         F(768000, P_XO, 5, 1, 5),
1640         F(800000, P_XO, 5, 5, 24),
1641         F(1024000, P_XO, 5, 4, 15),
1642         F(1152000, P_XO, 1, 3, 50),
1643         F(1411200, P_GPLL1, 16, 1, 40),
1644         F(1536000, P_XO, 1, 2, 25),
1645         F(1600000, P_XO, 12, 0, 0),
1646         F(1728000, P_XO, 5, 9, 20),
1647         F(2048000, P_XO, 5, 8, 15),
1648         F(2304000, P_XO, 5, 3, 5),
1649         F(2400000, P_XO, 8, 0, 0),
1650         F(2822400, P_GPLL1, 16, 1, 20),
1651         F(3072000, P_XO, 5, 4, 5),
1652         F(4096000, P_GPLL1, 9, 2, 49),
1653         F(4800000, P_XO, 4, 0, 0),
1654         F(5644800, P_GPLL1, 16, 1, 10),
1655         F(6144000, P_GPLL1, 7, 1, 21),
1656         F(8192000, P_GPLL1, 9, 4, 49),
1657         F(9600000, P_XO, 2, 0, 0),
1658         F(11289600, P_GPLL1, 16, 1, 5),
1659         F(12288000, P_GPLL1, 7, 2, 21),
1660         { }
1661 };
1662
1663 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1664         .cmd_rcgr = 0x1c054,
1665         .hid_width = 5,
1666         .mnd_width = 8,
1667         .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1668         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1669         .clkr.hw.init = &(struct clk_init_data){
1670                 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1671                 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1672                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
1673                 .ops = &clk_rcg2_ops,
1674         },
1675 };
1676
1677 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1678         .halt_reg = 0x1c068,
1679         .clkr = {
1680                 .enable_reg = 0x1c068,
1681                 .enable_mask = BIT(0),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1684                         .parent_hws = (const struct clk_hw*[]){
1685                                 &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1686                         },
1687                         .num_parents = 1,
1688                         .flags = CLK_SET_RATE_PARENT,
1689                         .ops = &clk_branch2_ops,
1690                 },
1691         },
1692 };
1693
1694 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1695         .cmd_rcgr = 0x1c06c,
1696         .hid_width = 5,
1697         .mnd_width = 8,
1698         .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1699         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1700         .clkr.hw.init = &(struct clk_init_data){
1701                 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1702                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1703                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1704                 .ops = &clk_rcg2_ops,
1705         },
1706 };
1707
1708 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1709         .halt_reg = 0x1c080,
1710         .clkr = {
1711                 .enable_reg = 0x1c080,
1712                 .enable_mask = BIT(0),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1715                         .parent_hws = (const struct clk_hw*[]){
1716                                 &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1717                         },
1718                         .num_parents = 1,
1719                         .flags = CLK_SET_RATE_PARENT,
1720                         .ops = &clk_branch2_ops,
1721                 },
1722         },
1723 };
1724
1725 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1726         .cmd_rcgr = 0x1c084,
1727         .hid_width = 5,
1728         .mnd_width = 8,
1729         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1730         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1731         .clkr.hw.init = &(struct clk_init_data){
1732                 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1733                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1734                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
1735                 .ops = &clk_rcg2_ops,
1736         },
1737 };
1738
1739 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1740         .halt_reg = 0x1c098,
1741         .clkr = {
1742                 .enable_reg = 0x1c098,
1743                 .enable_mask = BIT(0),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1746                         .parent_hws = (const struct clk_hw*[]){
1747                                 &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1748                         },
1749                         .num_parents = 1,
1750                         .flags = CLK_SET_RATE_PARENT,
1751                         .ops = &clk_branch2_ops,
1752                 },
1753         },
1754 };
1755
1756 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1757         F(19200000, P_XO, 1, 0, 0),
1758         { }
1759 };
1760
1761 static struct clk_rcg2 ultaudio_xo_clk_src = {
1762         .cmd_rcgr = 0x1c034,
1763         .hid_width = 5,
1764         .parent_map = gcc_xo_sleep_map,
1765         .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1766         .clkr.hw.init = &(struct clk_init_data){
1767                 .name = "ultaudio_xo_clk_src",
1768                 .parent_data = gcc_xo_sleep_parent_data,
1769                 .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
1770                 .ops = &clk_rcg2_ops,
1771         },
1772 };
1773
1774 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1775         .halt_reg = 0x1c04c,
1776         .clkr = {
1777                 .enable_reg = 0x1c04c,
1778                 .enable_mask = BIT(0),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "gcc_ultaudio_avsync_xo_clk",
1781                         .parent_hws = (const struct clk_hw*[]){
1782                                 &ultaudio_xo_clk_src.clkr.hw,
1783                         },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1792         .halt_reg = 0x1c050,
1793         .clkr = {
1794                 .enable_reg = 0x1c050,
1795                 .enable_mask = BIT(0),
1796                 .hw.init = &(struct clk_init_data){
1797                         .name = "gcc_ultaudio_stc_xo_clk",
1798                         .parent_hws = (const struct clk_hw*[]){
1799                                 &ultaudio_xo_clk_src.clkr.hw,
1800                         },
1801                         .num_parents = 1,
1802                         .flags = CLK_SET_RATE_PARENT,
1803                         .ops = &clk_branch2_ops,
1804                 },
1805         },
1806 };
1807
1808 static const struct freq_tbl ftbl_codec_clk[] = {
1809         F(9600000, P_XO, 2, 0, 0),
1810         F(12288000, P_XO, 1, 16, 25),
1811         F(19200000, P_XO, 1, 0, 0),
1812         F(11289600, P_EXT_MCLK, 1, 0, 0),
1813         { }
1814 };
1815
1816 static struct clk_rcg2 codec_digcodec_clk_src = {
1817         .cmd_rcgr = 0x1c09c,
1818         .mnd_width = 8,
1819         .hid_width = 5,
1820         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1821         .freq_tbl = ftbl_codec_clk,
1822         .clkr.hw.init = &(struct clk_init_data){
1823                 .name = "codec_digcodec_clk_src",
1824                 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1825                 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
1826                 .ops = &clk_rcg2_ops,
1827         },
1828 };
1829
1830 static struct clk_branch gcc_codec_digcodec_clk = {
1831         .halt_reg = 0x1c0b0,
1832         .clkr = {
1833                 .enable_reg = 0x1c0b0,
1834                 .enable_mask = BIT(0),
1835                 .hw.init = &(struct clk_init_data){
1836                         .name = "gcc_ultaudio_codec_digcodec_clk",
1837                         .parent_hws = (const struct clk_hw*[]){
1838                                 &codec_digcodec_clk_src.clkr.hw,
1839                         },
1840                         .num_parents = 1,
1841                         .flags = CLK_SET_RATE_PARENT,
1842                         .ops = &clk_branch2_ops,
1843                 },
1844         },
1845 };
1846
1847 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1848         .halt_reg = 0x1c000,
1849         .clkr = {
1850                 .enable_reg = 0x1c000,
1851                 .enable_mask = BIT(0),
1852                 .hw.init = &(struct clk_init_data){
1853                         .name = "gcc_ultaudio_pcnoc_mport_clk",
1854                         .parent_hws = (const struct clk_hw*[]){
1855                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1856                         },
1857                         .num_parents = 1,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1864         .halt_reg = 0x1c004,
1865         .clkr = {
1866                 .enable_reg = 0x1c004,
1867                 .enable_mask = BIT(0),
1868                 .hw.init = &(struct clk_init_data){
1869                         .name = "gcc_ultaudio_pcnoc_sway_clk",
1870                         .parent_hws = (const struct clk_hw*[]){
1871                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1872                         },
1873                         .num_parents = 1,
1874                         .ops = &clk_branch2_ops,
1875                 },
1876         },
1877 };
1878
1879 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1880         F(133330000, P_GPLL0, 6, 0, 0),
1881         F(200000000, P_GPLL0, 4, 0, 0),
1882         F(266670000, P_GPLL0, 3, 0, 0),
1883         { }
1884 };
1885
1886 static struct clk_rcg2 vcodec0_clk_src = {
1887         .cmd_rcgr = 0x4C000,
1888         .mnd_width = 8,
1889         .hid_width = 5,
1890         .parent_map = gcc_xo_gpll0_map,
1891         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1892         .clkr.hw.init = &(struct clk_init_data){
1893                 .name = "vcodec0_clk_src",
1894                 .parent_data = gcc_xo_gpll0_parent_data,
1895                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
1896                 .ops = &clk_rcg2_ops,
1897         },
1898 };
1899
1900 static struct clk_branch gcc_blsp1_ahb_clk = {
1901         .halt_reg = 0x01008,
1902         .halt_check = BRANCH_HALT_VOTED,
1903         .clkr = {
1904                 .enable_reg = 0x45004,
1905                 .enable_mask = BIT(10),
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "gcc_blsp1_ahb_clk",
1908                         .parent_hws = (const struct clk_hw*[]){
1909                                 &pcnoc_bfdcd_clk_src.clkr.hw,
1910                         },
1911                         .num_parents = 1,
1912                         .ops = &clk_branch2_ops,
1913                 },
1914         },
1915 };
1916
1917 static struct clk_branch gcc_blsp1_sleep_clk = {
1918         .halt_reg = 0x01004,
1919         .clkr = {
1920                 .enable_reg = 0x01004,
1921                 .enable_mask = BIT(0),
1922                 .hw.init = &(struct clk_init_data){
1923                         .name = "gcc_blsp1_sleep_clk",
1924                         .ops = &clk_branch2_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1930         .halt_reg = 0x02008,
1931         .clkr = {
1932                 .enable_reg = 0x02008,
1933                 .enable_mask = BIT(0),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1936                         .parent_hws = (const struct clk_hw*[]){
1937                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1938                         },
1939                         .num_parents = 1,
1940                         .flags = CLK_SET_RATE_PARENT,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1947         .halt_reg = 0x02004,
1948         .clkr = {
1949                 .enable_reg = 0x02004,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1953                         .parent_hws = (const struct clk_hw*[]){
1954                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1955                         },
1956                         .num_parents = 1,
1957                         .flags = CLK_SET_RATE_PARENT,
1958                         .ops = &clk_branch2_ops,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1964         .halt_reg = 0x03010,
1965         .clkr = {
1966                 .enable_reg = 0x03010,
1967                 .enable_mask = BIT(0),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1970                         .parent_hws = (const struct clk_hw*[]){
1971                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1972                         },
1973                         .num_parents = 1,
1974                         .flags = CLK_SET_RATE_PARENT,
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1981         .halt_reg = 0x0300c,
1982         .clkr = {
1983                 .enable_reg = 0x0300c,
1984                 .enable_mask = BIT(0),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1987                         .parent_hws = (const struct clk_hw*[]){
1988                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1989                         },
1990                         .num_parents = 1,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1998         .halt_reg = 0x04020,
1999         .clkr = {
2000                 .enable_reg = 0x04020,
2001                 .enable_mask = BIT(0),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2004                         .parent_hws = (const struct clk_hw*[]){
2005                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
2006                         },
2007                         .num_parents = 1,
2008                         .flags = CLK_SET_RATE_PARENT,
2009                         .ops = &clk_branch2_ops,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2015         .halt_reg = 0x0401c,
2016         .clkr = {
2017                 .enable_reg = 0x0401c,
2018                 .enable_mask = BIT(0),
2019                 .hw.init = &(struct clk_init_data){
2020                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2021                         .parent_hws = (const struct clk_hw*[]){
2022                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
2023                         },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2032         .halt_reg = 0x05020,
2033         .clkr = {
2034                 .enable_reg = 0x05020,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2038                         .parent_hws = (const struct clk_hw*[]){
2039                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
2040                         },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2049         .halt_reg = 0x0501c,
2050         .clkr = {
2051                 .enable_reg = 0x0501c,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2055                         .parent_hws = (const struct clk_hw*[]){
2056                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2057                         },
2058                         .num_parents = 1,
2059                         .flags = CLK_SET_RATE_PARENT,
2060                         .ops = &clk_branch2_ops,
2061                 },
2062         },
2063 };
2064
2065 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2066         .halt_reg = 0x06020,
2067         .clkr = {
2068                 .enable_reg = 0x06020,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2072                         .parent_hws = (const struct clk_hw*[]){
2073                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2074                         },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2083         .halt_reg = 0x0601c,
2084         .clkr = {
2085                 .enable_reg = 0x0601c,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2089                         .parent_hws = (const struct clk_hw*[]){
2090                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2091                         },
2092                         .num_parents = 1,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                         .ops = &clk_branch2_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2100         .halt_reg = 0x07020,
2101         .clkr = {
2102                 .enable_reg = 0x07020,
2103                 .enable_mask = BIT(0),
2104                 .hw.init = &(struct clk_init_data){
2105                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2106                         .parent_hws = (const struct clk_hw*[]){
2107                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2108                         },
2109                         .num_parents = 1,
2110                         .flags = CLK_SET_RATE_PARENT,
2111                         .ops = &clk_branch2_ops,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2117         .halt_reg = 0x0701c,
2118         .clkr = {
2119                 .enable_reg = 0x0701c,
2120                 .enable_mask = BIT(0),
2121                 .hw.init = &(struct clk_init_data){
2122                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2123                         .parent_hws = (const struct clk_hw*[]){
2124                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2125                         },
2126                         .num_parents = 1,
2127                         .flags = CLK_SET_RATE_PARENT,
2128                         .ops = &clk_branch2_ops,
2129                 },
2130         },
2131 };
2132
2133 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2134         .halt_reg = 0x0203c,
2135         .clkr = {
2136                 .enable_reg = 0x0203c,
2137                 .enable_mask = BIT(0),
2138                 .hw.init = &(struct clk_init_data){
2139                         .name = "gcc_blsp1_uart1_apps_clk",
2140                         .parent_hws = (const struct clk_hw*[]){
2141                                 &blsp1_uart1_apps_clk_src.clkr.hw,
2142                         },
2143                         .num_parents = 1,
2144                         .flags = CLK_SET_RATE_PARENT,
2145                         .ops = &clk_branch2_ops,
2146                 },
2147         },
2148 };
2149
2150 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2151         .halt_reg = 0x0302c,
2152         .clkr = {
2153                 .enable_reg = 0x0302c,
2154                 .enable_mask = BIT(0),
2155                 .hw.init = &(struct clk_init_data){
2156                         .name = "gcc_blsp1_uart2_apps_clk",
2157                         .parent_hws = (const struct clk_hw*[]){
2158                                 &blsp1_uart2_apps_clk_src.clkr.hw,
2159                         },
2160                         .num_parents = 1,
2161                         .flags = CLK_SET_RATE_PARENT,
2162                         .ops = &clk_branch2_ops,
2163                 },
2164         },
2165 };
2166
2167 static struct clk_branch gcc_boot_rom_ahb_clk = {
2168         .halt_reg = 0x1300c,
2169         .halt_check = BRANCH_HALT_VOTED,
2170         .clkr = {
2171                 .enable_reg = 0x45004,
2172                 .enable_mask = BIT(7),
2173                 .hw.init = &(struct clk_init_data){
2174                         .name = "gcc_boot_rom_ahb_clk",
2175                         .parent_hws = (const struct clk_hw*[]){
2176                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2177                         },
2178                         .num_parents = 1,
2179                         .ops = &clk_branch2_ops,
2180                 },
2181         },
2182 };
2183
2184 static struct clk_branch gcc_camss_cci_ahb_clk = {
2185         .halt_reg = 0x5101c,
2186         .clkr = {
2187                 .enable_reg = 0x5101c,
2188                 .enable_mask = BIT(0),
2189                 .hw.init = &(struct clk_init_data){
2190                         .name = "gcc_camss_cci_ahb_clk",
2191                         .parent_hws = (const struct clk_hw*[]){
2192                                 &camss_ahb_clk_src.clkr.hw,
2193                         },
2194                         .num_parents = 1,
2195                         .flags = CLK_SET_RATE_PARENT,
2196                         .ops = &clk_branch2_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gcc_camss_cci_clk = {
2202         .halt_reg = 0x51018,
2203         .clkr = {
2204                 .enable_reg = 0x51018,
2205                 .enable_mask = BIT(0),
2206                 .hw.init = &(struct clk_init_data){
2207                         .name = "gcc_camss_cci_clk",
2208                         .parent_hws = (const struct clk_hw*[]){
2209                                 &cci_clk_src.clkr.hw,
2210                         },
2211                         .num_parents = 1,
2212                         .flags = CLK_SET_RATE_PARENT,
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2219         .halt_reg = 0x4e040,
2220         .clkr = {
2221                 .enable_reg = 0x4e040,
2222                 .enable_mask = BIT(0),
2223                 .hw.init = &(struct clk_init_data){
2224                         .name = "gcc_camss_csi0_ahb_clk",
2225                         .parent_hws = (const struct clk_hw*[]){
2226                                 &camss_ahb_clk_src.clkr.hw,
2227                         },
2228                         .num_parents = 1,
2229                         .flags = CLK_SET_RATE_PARENT,
2230                         .ops = &clk_branch2_ops,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch gcc_camss_csi0_clk = {
2236         .halt_reg = 0x4e03c,
2237         .clkr = {
2238                 .enable_reg = 0x4e03c,
2239                 .enable_mask = BIT(0),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "gcc_camss_csi0_clk",
2242                         .parent_hws = (const struct clk_hw*[]){
2243                                 &csi0_clk_src.clkr.hw,
2244                         },
2245                         .num_parents = 1,
2246                         .flags = CLK_SET_RATE_PARENT,
2247                         .ops = &clk_branch2_ops,
2248                 },
2249         },
2250 };
2251
2252 static struct clk_branch gcc_camss_csi0phy_clk = {
2253         .halt_reg = 0x4e048,
2254         .clkr = {
2255                 .enable_reg = 0x4e048,
2256                 .enable_mask = BIT(0),
2257                 .hw.init = &(struct clk_init_data){
2258                         .name = "gcc_camss_csi0phy_clk",
2259                         .parent_hws = (const struct clk_hw*[]){
2260                                 &csi0_clk_src.clkr.hw,
2261                         },
2262                         .num_parents = 1,
2263                         .flags = CLK_SET_RATE_PARENT,
2264                         .ops = &clk_branch2_ops,
2265                 },
2266         },
2267 };
2268
2269 static struct clk_branch gcc_camss_csi0pix_clk = {
2270         .halt_reg = 0x4e058,
2271         .clkr = {
2272                 .enable_reg = 0x4e058,
2273                 .enable_mask = BIT(0),
2274                 .hw.init = &(struct clk_init_data){
2275                         .name = "gcc_camss_csi0pix_clk",
2276                         .parent_hws = (const struct clk_hw*[]){
2277                                 &csi0_clk_src.clkr.hw,
2278                         },
2279                         .num_parents = 1,
2280                         .flags = CLK_SET_RATE_PARENT,
2281                         .ops = &clk_branch2_ops,
2282                 },
2283         },
2284 };
2285
2286 static struct clk_branch gcc_camss_csi0rdi_clk = {
2287         .halt_reg = 0x4e050,
2288         .clkr = {
2289                 .enable_reg = 0x4e050,
2290                 .enable_mask = BIT(0),
2291                 .hw.init = &(struct clk_init_data){
2292                         .name = "gcc_camss_csi0rdi_clk",
2293                         .parent_hws = (const struct clk_hw*[]){
2294                                 &csi0_clk_src.clkr.hw,
2295                         },
2296                         .num_parents = 1,
2297                         .flags = CLK_SET_RATE_PARENT,
2298                         .ops = &clk_branch2_ops,
2299                 },
2300         },
2301 };
2302
2303 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2304         .halt_reg = 0x4f040,
2305         .clkr = {
2306                 .enable_reg = 0x4f040,
2307                 .enable_mask = BIT(0),
2308                 .hw.init = &(struct clk_init_data){
2309                         .name = "gcc_camss_csi1_ahb_clk",
2310                         .parent_hws = (const struct clk_hw*[]){
2311                                 &camss_ahb_clk_src.clkr.hw,
2312                         },
2313                         .num_parents = 1,
2314                         .flags = CLK_SET_RATE_PARENT,
2315                         .ops = &clk_branch2_ops,
2316                 },
2317         },
2318 };
2319
2320 static struct clk_branch gcc_camss_csi1_clk = {
2321         .halt_reg = 0x4f03c,
2322         .clkr = {
2323                 .enable_reg = 0x4f03c,
2324                 .enable_mask = BIT(0),
2325                 .hw.init = &(struct clk_init_data){
2326                         .name = "gcc_camss_csi1_clk",
2327                         .parent_hws = (const struct clk_hw*[]){
2328                                 &csi1_clk_src.clkr.hw,
2329                         },
2330                         .num_parents = 1,
2331                         .flags = CLK_SET_RATE_PARENT,
2332                         .ops = &clk_branch2_ops,
2333                 },
2334         },
2335 };
2336
2337 static struct clk_branch gcc_camss_csi1phy_clk = {
2338         .halt_reg = 0x4f048,
2339         .clkr = {
2340                 .enable_reg = 0x4f048,
2341                 .enable_mask = BIT(0),
2342                 .hw.init = &(struct clk_init_data){
2343                         .name = "gcc_camss_csi1phy_clk",
2344                         .parent_hws = (const struct clk_hw*[]){
2345                                 &csi1_clk_src.clkr.hw,
2346                         },
2347                         .num_parents = 1,
2348                         .flags = CLK_SET_RATE_PARENT,
2349                         .ops = &clk_branch2_ops,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch gcc_camss_csi1pix_clk = {
2355         .halt_reg = 0x4f058,
2356         .clkr = {
2357                 .enable_reg = 0x4f058,
2358                 .enable_mask = BIT(0),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gcc_camss_csi1pix_clk",
2361                         .parent_hws = (const struct clk_hw*[]){
2362                                 &csi1_clk_src.clkr.hw,
2363                         },
2364                         .num_parents = 1,
2365                         .flags = CLK_SET_RATE_PARENT,
2366                         .ops = &clk_branch2_ops,
2367                 },
2368         },
2369 };
2370
2371 static struct clk_branch gcc_camss_csi1rdi_clk = {
2372         .halt_reg = 0x4f050,
2373         .clkr = {
2374                 .enable_reg = 0x4f050,
2375                 .enable_mask = BIT(0),
2376                 .hw.init = &(struct clk_init_data){
2377                         .name = "gcc_camss_csi1rdi_clk",
2378                         .parent_hws = (const struct clk_hw*[]){
2379                                 &csi1_clk_src.clkr.hw,
2380                         },
2381                         .num_parents = 1,
2382                         .flags = CLK_SET_RATE_PARENT,
2383                         .ops = &clk_branch2_ops,
2384                 },
2385         },
2386 };
2387
2388 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2389         .halt_reg = 0x58050,
2390         .clkr = {
2391                 .enable_reg = 0x58050,
2392                 .enable_mask = BIT(0),
2393                 .hw.init = &(struct clk_init_data){
2394                         .name = "gcc_camss_csi_vfe0_clk",
2395                         .parent_hws = (const struct clk_hw*[]){
2396                                 &vfe0_clk_src.clkr.hw,
2397                         },
2398                         .num_parents = 1,
2399                         .flags = CLK_SET_RATE_PARENT,
2400                         .ops = &clk_branch2_ops,
2401                 },
2402         },
2403 };
2404
2405 static struct clk_branch gcc_camss_gp0_clk = {
2406         .halt_reg = 0x54018,
2407         .clkr = {
2408                 .enable_reg = 0x54018,
2409                 .enable_mask = BIT(0),
2410                 .hw.init = &(struct clk_init_data){
2411                         .name = "gcc_camss_gp0_clk",
2412                         .parent_hws = (const struct clk_hw*[]){
2413                                 &camss_gp0_clk_src.clkr.hw,
2414                         },
2415                         .num_parents = 1,
2416                         .flags = CLK_SET_RATE_PARENT,
2417                         .ops = &clk_branch2_ops,
2418                 },
2419         },
2420 };
2421
2422 static struct clk_branch gcc_camss_gp1_clk = {
2423         .halt_reg = 0x55018,
2424         .clkr = {
2425                 .enable_reg = 0x55018,
2426                 .enable_mask = BIT(0),
2427                 .hw.init = &(struct clk_init_data){
2428                         .name = "gcc_camss_gp1_clk",
2429                         .parent_hws = (const struct clk_hw*[]){
2430                                 &camss_gp1_clk_src.clkr.hw,
2431                         },
2432                         .num_parents = 1,
2433                         .flags = CLK_SET_RATE_PARENT,
2434                         .ops = &clk_branch2_ops,
2435                 },
2436         },
2437 };
2438
2439 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2440         .halt_reg = 0x50004,
2441         .clkr = {
2442                 .enable_reg = 0x50004,
2443                 .enable_mask = BIT(0),
2444                 .hw.init = &(struct clk_init_data){
2445                         .name = "gcc_camss_ispif_ahb_clk",
2446                         .parent_hws = (const struct clk_hw*[]){
2447                                 &camss_ahb_clk_src.clkr.hw,
2448                         },
2449                         .num_parents = 1,
2450                         .flags = CLK_SET_RATE_PARENT,
2451                         .ops = &clk_branch2_ops,
2452                 },
2453         },
2454 };
2455
2456 static struct clk_branch gcc_camss_jpeg0_clk = {
2457         .halt_reg = 0x57020,
2458         .clkr = {
2459                 .enable_reg = 0x57020,
2460                 .enable_mask = BIT(0),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "gcc_camss_jpeg0_clk",
2463                         .parent_hws = (const struct clk_hw*[]){
2464                                 &jpeg0_clk_src.clkr.hw,
2465                         },
2466                         .num_parents = 1,
2467                         .flags = CLK_SET_RATE_PARENT,
2468                         .ops = &clk_branch2_ops,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2474         .halt_reg = 0x57024,
2475         .clkr = {
2476                 .enable_reg = 0x57024,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "gcc_camss_jpeg_ahb_clk",
2480                         .parent_hws = (const struct clk_hw*[]){
2481                                 &camss_ahb_clk_src.clkr.hw,
2482                         },
2483                         .num_parents = 1,
2484                         .flags = CLK_SET_RATE_PARENT,
2485                         .ops = &clk_branch2_ops,
2486                 },
2487         },
2488 };
2489
2490 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2491         .halt_reg = 0x57028,
2492         .clkr = {
2493                 .enable_reg = 0x57028,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_camss_jpeg_axi_clk",
2497                         .parent_hws = (const struct clk_hw*[]){
2498                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2499                         },
2500                         .num_parents = 1,
2501                         .flags = CLK_SET_RATE_PARENT,
2502                         .ops = &clk_branch2_ops,
2503                 },
2504         },
2505 };
2506
2507 static struct clk_branch gcc_camss_mclk0_clk = {
2508         .halt_reg = 0x52018,
2509         .clkr = {
2510                 .enable_reg = 0x52018,
2511                 .enable_mask = BIT(0),
2512                 .hw.init = &(struct clk_init_data){
2513                         .name = "gcc_camss_mclk0_clk",
2514                         .parent_hws = (const struct clk_hw*[]){
2515                                 &mclk0_clk_src.clkr.hw,
2516                         },
2517                         .num_parents = 1,
2518                         .flags = CLK_SET_RATE_PARENT,
2519                         .ops = &clk_branch2_ops,
2520                 },
2521         },
2522 };
2523
2524 static struct clk_branch gcc_camss_mclk1_clk = {
2525         .halt_reg = 0x53018,
2526         .clkr = {
2527                 .enable_reg = 0x53018,
2528                 .enable_mask = BIT(0),
2529                 .hw.init = &(struct clk_init_data){
2530                         .name = "gcc_camss_mclk1_clk",
2531                         .parent_hws = (const struct clk_hw*[]){
2532                                 &mclk1_clk_src.clkr.hw,
2533                         },
2534                         .num_parents = 1,
2535                         .flags = CLK_SET_RATE_PARENT,
2536                         .ops = &clk_branch2_ops,
2537                 },
2538         },
2539 };
2540
2541 static struct clk_branch gcc_camss_micro_ahb_clk = {
2542         .halt_reg = 0x5600c,
2543         .clkr = {
2544                 .enable_reg = 0x5600c,
2545                 .enable_mask = BIT(0),
2546                 .hw.init = &(struct clk_init_data){
2547                         .name = "gcc_camss_micro_ahb_clk",
2548                         .parent_hws = (const struct clk_hw*[]){
2549                                 &camss_ahb_clk_src.clkr.hw,
2550                         },
2551                         .num_parents = 1,
2552                         .flags = CLK_SET_RATE_PARENT,
2553                         .ops = &clk_branch2_ops,
2554                 },
2555         },
2556 };
2557
2558 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2559         .halt_reg = 0x4e01c,
2560         .clkr = {
2561                 .enable_reg = 0x4e01c,
2562                 .enable_mask = BIT(0),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "gcc_camss_csi0phytimer_clk",
2565                         .parent_hws = (const struct clk_hw*[]){
2566                                 &csi0phytimer_clk_src.clkr.hw,
2567                         },
2568                         .num_parents = 1,
2569                         .flags = CLK_SET_RATE_PARENT,
2570                         .ops = &clk_branch2_ops,
2571                 },
2572         },
2573 };
2574
2575 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2576         .halt_reg = 0x4f01c,
2577         .clkr = {
2578                 .enable_reg = 0x4f01c,
2579                 .enable_mask = BIT(0),
2580                 .hw.init = &(struct clk_init_data){
2581                         .name = "gcc_camss_csi1phytimer_clk",
2582                         .parent_hws = (const struct clk_hw*[]){
2583                                 &csi1phytimer_clk_src.clkr.hw,
2584                         },
2585                         .num_parents = 1,
2586                         .flags = CLK_SET_RATE_PARENT,
2587                         .ops = &clk_branch2_ops,
2588                 },
2589         },
2590 };
2591
2592 static struct clk_branch gcc_camss_ahb_clk = {
2593         .halt_reg = 0x5a014,
2594         .clkr = {
2595                 .enable_reg = 0x5a014,
2596                 .enable_mask = BIT(0),
2597                 .hw.init = &(struct clk_init_data){
2598                         .name = "gcc_camss_ahb_clk",
2599                         .parent_hws = (const struct clk_hw*[]){
2600                                 &camss_ahb_clk_src.clkr.hw,
2601                         },
2602                         .num_parents = 1,
2603                         .flags = CLK_SET_RATE_PARENT,
2604                         .ops = &clk_branch2_ops,
2605                 },
2606         },
2607 };
2608
2609 static struct clk_branch gcc_camss_top_ahb_clk = {
2610         .halt_reg = 0x56004,
2611         .clkr = {
2612                 .enable_reg = 0x56004,
2613                 .enable_mask = BIT(0),
2614                 .hw.init = &(struct clk_init_data){
2615                         .name = "gcc_camss_top_ahb_clk",
2616                         .parent_hws = (const struct clk_hw*[]){
2617                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2618                         },
2619                         .num_parents = 1,
2620                         .flags = CLK_SET_RATE_PARENT,
2621                         .ops = &clk_branch2_ops,
2622                 },
2623         },
2624 };
2625
2626 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2627         .halt_reg = 0x58040,
2628         .clkr = {
2629                 .enable_reg = 0x58040,
2630                 .enable_mask = BIT(0),
2631                 .hw.init = &(struct clk_init_data){
2632                         .name = "gcc_camss_cpp_ahb_clk",
2633                         .parent_hws = (const struct clk_hw*[]){
2634                                 &camss_ahb_clk_src.clkr.hw,
2635                         },
2636                         .num_parents = 1,
2637                         .flags = CLK_SET_RATE_PARENT,
2638                         .ops = &clk_branch2_ops,
2639                 },
2640         },
2641 };
2642
2643 static struct clk_branch gcc_camss_cpp_clk = {
2644         .halt_reg = 0x5803c,
2645         .clkr = {
2646                 .enable_reg = 0x5803c,
2647                 .enable_mask = BIT(0),
2648                 .hw.init = &(struct clk_init_data){
2649                         .name = "gcc_camss_cpp_clk",
2650                         .parent_hws = (const struct clk_hw*[]){
2651                                 &cpp_clk_src.clkr.hw,
2652                         },
2653                         .num_parents = 1,
2654                         .flags = CLK_SET_RATE_PARENT,
2655                         .ops = &clk_branch2_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch gcc_camss_vfe0_clk = {
2661         .halt_reg = 0x58038,
2662         .clkr = {
2663                 .enable_reg = 0x58038,
2664                 .enable_mask = BIT(0),
2665                 .hw.init = &(struct clk_init_data){
2666                         .name = "gcc_camss_vfe0_clk",
2667                         .parent_hws = (const struct clk_hw*[]){
2668                                 &vfe0_clk_src.clkr.hw,
2669                         },
2670                         .num_parents = 1,
2671                         .flags = CLK_SET_RATE_PARENT,
2672                         .ops = &clk_branch2_ops,
2673                 },
2674         },
2675 };
2676
2677 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2678         .halt_reg = 0x58044,
2679         .clkr = {
2680                 .enable_reg = 0x58044,
2681                 .enable_mask = BIT(0),
2682                 .hw.init = &(struct clk_init_data){
2683                         .name = "gcc_camss_vfe_ahb_clk",
2684                         .parent_hws = (const struct clk_hw*[]){
2685                                 &camss_ahb_clk_src.clkr.hw,
2686                         },
2687                         .num_parents = 1,
2688                         .flags = CLK_SET_RATE_PARENT,
2689                         .ops = &clk_branch2_ops,
2690                 },
2691         },
2692 };
2693
2694 static struct clk_branch gcc_camss_vfe_axi_clk = {
2695         .halt_reg = 0x58048,
2696         .clkr = {
2697                 .enable_reg = 0x58048,
2698                 .enable_mask = BIT(0),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "gcc_camss_vfe_axi_clk",
2701                         .parent_hws = (const struct clk_hw*[]){
2702                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2703                         },
2704                         .num_parents = 1,
2705                         .flags = CLK_SET_RATE_PARENT,
2706                         .ops = &clk_branch2_ops,
2707                 },
2708         },
2709 };
2710
2711 static struct clk_branch gcc_crypto_ahb_clk = {
2712         .halt_reg = 0x16024,
2713         .halt_check = BRANCH_HALT_VOTED,
2714         .clkr = {
2715                 .enable_reg = 0x45004,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data){
2718                         .name = "gcc_crypto_ahb_clk",
2719                         .parent_hws = (const struct clk_hw*[]){
2720                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2721                         },
2722                         .num_parents = 1,
2723                         .flags = CLK_SET_RATE_PARENT,
2724                         .ops = &clk_branch2_ops,
2725                 },
2726         },
2727 };
2728
2729 static struct clk_branch gcc_crypto_axi_clk = {
2730         .halt_reg = 0x16020,
2731         .halt_check = BRANCH_HALT_VOTED,
2732         .clkr = {
2733                 .enable_reg = 0x45004,
2734                 .enable_mask = BIT(1),
2735                 .hw.init = &(struct clk_init_data){
2736                         .name = "gcc_crypto_axi_clk",
2737                         .parent_hws = (const struct clk_hw*[]){
2738                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2739                         },
2740                         .num_parents = 1,
2741                         .flags = CLK_SET_RATE_PARENT,
2742                         .ops = &clk_branch2_ops,
2743                 },
2744         },
2745 };
2746
2747 static struct clk_branch gcc_crypto_clk = {
2748         .halt_reg = 0x1601c,
2749         .halt_check = BRANCH_HALT_VOTED,
2750         .clkr = {
2751                 .enable_reg = 0x45004,
2752                 .enable_mask = BIT(2),
2753                 .hw.init = &(struct clk_init_data){
2754                         .name = "gcc_crypto_clk",
2755                         .parent_hws = (const struct clk_hw*[]){
2756                                 &crypto_clk_src.clkr.hw,
2757                         },
2758                         .num_parents = 1,
2759                         .flags = CLK_SET_RATE_PARENT,
2760                         .ops = &clk_branch2_ops,
2761                 },
2762         },
2763 };
2764
2765 static struct clk_branch gcc_oxili_gmem_clk = {
2766         .halt_reg = 0x59024,
2767         .clkr = {
2768                 .enable_reg = 0x59024,
2769                 .enable_mask = BIT(0),
2770                 .hw.init = &(struct clk_init_data){
2771                         .name = "gcc_oxili_gmem_clk",
2772                         .parent_hws = (const struct clk_hw*[]){
2773                                 &gfx3d_clk_src.clkr.hw,
2774                         },
2775                         .num_parents = 1,
2776                         .flags = CLK_SET_RATE_PARENT,
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch gcc_gp1_clk = {
2783         .halt_reg = 0x08000,
2784         .clkr = {
2785                 .enable_reg = 0x08000,
2786                 .enable_mask = BIT(0),
2787                 .hw.init = &(struct clk_init_data){
2788                         .name = "gcc_gp1_clk",
2789                         .parent_hws = (const struct clk_hw*[]){
2790                                 &gp1_clk_src.clkr.hw,
2791                         },
2792                         .num_parents = 1,
2793                         .flags = CLK_SET_RATE_PARENT,
2794                         .ops = &clk_branch2_ops,
2795                 },
2796         },
2797 };
2798
2799 static struct clk_branch gcc_gp2_clk = {
2800         .halt_reg = 0x09000,
2801         .clkr = {
2802                 .enable_reg = 0x09000,
2803                 .enable_mask = BIT(0),
2804                 .hw.init = &(struct clk_init_data){
2805                         .name = "gcc_gp2_clk",
2806                         .parent_hws = (const struct clk_hw*[]){
2807                                 &gp2_clk_src.clkr.hw,
2808                         },
2809                         .num_parents = 1,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch gcc_gp3_clk = {
2817         .halt_reg = 0x0a000,
2818         .clkr = {
2819                 .enable_reg = 0x0a000,
2820                 .enable_mask = BIT(0),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "gcc_gp3_clk",
2823                         .parent_hws = (const struct clk_hw*[]){
2824                                 &gp3_clk_src.clkr.hw,
2825                         },
2826                         .num_parents = 1,
2827                         .flags = CLK_SET_RATE_PARENT,
2828                         .ops = &clk_branch2_ops,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch gcc_mdss_ahb_clk = {
2834         .halt_reg = 0x4d07c,
2835         .clkr = {
2836                 .enable_reg = 0x4d07c,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data){
2839                         .name = "gcc_mdss_ahb_clk",
2840                         .parent_hws = (const struct clk_hw*[]){
2841                                 &pcnoc_bfdcd_clk_src.clkr.hw,
2842                         },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch gcc_mdss_axi_clk = {
2851         .halt_reg = 0x4d080,
2852         .clkr = {
2853                 .enable_reg = 0x4d080,
2854                 .enable_mask = BIT(0),
2855                 .hw.init = &(struct clk_init_data){
2856                         .name = "gcc_mdss_axi_clk",
2857                         .parent_hws = (const struct clk_hw*[]){
2858                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
2859                         },
2860                         .num_parents = 1,
2861                         .flags = CLK_SET_RATE_PARENT,
2862                         .ops = &clk_branch2_ops,
2863                 },
2864         },
2865 };
2866
2867 static struct clk_branch gcc_mdss_byte0_clk = {
2868         .halt_reg = 0x4d094,
2869         .clkr = {
2870                 .enable_reg = 0x4d094,
2871                 .enable_mask = BIT(0),
2872                 .hw.init = &(struct clk_init_data){
2873                         .name = "gcc_mdss_byte0_clk",
2874                         .parent_hws = (const struct clk_hw*[]){
2875                                 &byte0_clk_src.clkr.hw,
2876                         },
2877                         .num_parents = 1,
2878                         .flags = CLK_SET_RATE_PARENT,
2879                         .ops = &clk_branch2_ops,
2880                 },
2881         },
2882 };
2883
2884 static struct clk_branch gcc_mdss_byte1_clk = {
2885         .halt_reg = 0x4d0a0,
2886         .clkr = {
2887                 .enable_reg = 0x4d0a0,
2888                 .enable_mask = BIT(0),
2889                 .hw.init = &(struct clk_init_data){
2890                         .name = "gcc_mdss_byte1_clk",
2891                         .parent_hws = (const struct clk_hw*[]){
2892                                 &byte1_clk_src.clkr.hw,
2893                         },
2894                         .num_parents = 1,
2895                         .flags = CLK_SET_RATE_PARENT,
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch gcc_mdss_esc0_clk = {
2902         .halt_reg = 0x4d098,
2903         .clkr = {
2904                 .enable_reg = 0x4d098,
2905                 .enable_mask = BIT(0),
2906                 .hw.init = &(struct clk_init_data){
2907                         .name = "gcc_mdss_esc0_clk",
2908                         .parent_hws = (const struct clk_hw*[]){
2909                                 &esc0_clk_src.clkr.hw,
2910                         },
2911                         .num_parents = 1,
2912                         .flags = CLK_SET_RATE_PARENT,
2913                         .ops = &clk_branch2_ops,
2914                 },
2915         },
2916 };
2917
2918 static struct clk_branch gcc_mdss_esc1_clk = {
2919         .halt_reg = 0x4d09c,
2920         .clkr = {
2921                 .enable_reg = 0x4d09c,
2922                 .enable_mask = BIT(0),
2923                 .hw.init = &(struct clk_init_data){
2924                         .name = "gcc_mdss_esc1_clk",
2925                         .parent_hws = (const struct clk_hw*[]){
2926                                 &esc1_clk_src.clkr.hw,
2927                         },
2928                         .num_parents = 1,
2929                         .flags = CLK_SET_RATE_PARENT,
2930                         .ops = &clk_branch2_ops,
2931                 },
2932         },
2933 };
2934
2935 static struct clk_branch gcc_mdss_mdp_clk = {
2936         .halt_reg = 0x4D088,
2937         .clkr = {
2938                 .enable_reg = 0x4D088,
2939                 .enable_mask = BIT(0),
2940                 .hw.init = &(struct clk_init_data){
2941                         .name = "gcc_mdss_mdp_clk",
2942                         .parent_hws = (const struct clk_hw*[]){
2943                                 &mdp_clk_src.clkr.hw,
2944                         },
2945                         .num_parents = 1,
2946                         .flags = CLK_SET_RATE_PARENT,
2947                         .ops = &clk_branch2_ops,
2948                 },
2949         },
2950 };
2951
2952 static struct clk_branch gcc_mdss_pclk0_clk = {
2953         .halt_reg = 0x4d084,
2954         .clkr = {
2955                 .enable_reg = 0x4d084,
2956                 .enable_mask = BIT(0),
2957                 .hw.init = &(struct clk_init_data){
2958                         .name = "gcc_mdss_pclk0_clk",
2959                         .parent_hws = (const struct clk_hw*[]){
2960                                 &pclk0_clk_src.clkr.hw,
2961                         },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch gcc_mdss_pclk1_clk = {
2970         .halt_reg = 0x4d0a4,
2971         .clkr = {
2972                 .enable_reg = 0x4d0a4,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "gcc_mdss_pclk1_clk",
2976                         .parent_hws = (const struct clk_hw*[]){
2977                                 &pclk1_clk_src.clkr.hw,
2978                         },
2979                         .num_parents = 1,
2980                         .flags = CLK_SET_RATE_PARENT,
2981                         .ops = &clk_branch2_ops,
2982                 },
2983         },
2984 };
2985
2986 static struct clk_branch gcc_mdss_vsync_clk = {
2987         .halt_reg = 0x4d090,
2988         .clkr = {
2989                 .enable_reg = 0x4d090,
2990                 .enable_mask = BIT(0),
2991                 .hw.init = &(struct clk_init_data){
2992                         .name = "gcc_mdss_vsync_clk",
2993                         .parent_hws = (const struct clk_hw*[]){
2994                                 &vsync_clk_src.clkr.hw,
2995                         },
2996                         .num_parents = 1,
2997                         .flags = CLK_SET_RATE_PARENT,
2998                         .ops = &clk_branch2_ops,
2999                 },
3000         },
3001 };
3002
3003 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3004         .halt_reg = 0x49000,
3005         .clkr = {
3006                 .enable_reg = 0x49000,
3007                 .enable_mask = BIT(0),
3008                 .hw.init = &(struct clk_init_data){
3009                         .name = "gcc_mss_cfg_ahb_clk",
3010                         .parent_hws = (const struct clk_hw*[]){
3011                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3012                         },
3013                         .num_parents = 1,
3014                         .flags = CLK_SET_RATE_PARENT,
3015                         .ops = &clk_branch2_ops,
3016                 },
3017         },
3018 };
3019
3020 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3021         .halt_reg = 0x49004,
3022         .clkr = {
3023                 .enable_reg = 0x49004,
3024                 .enable_mask = BIT(0),
3025                 .hw.init = &(struct clk_init_data){
3026                         .name = "gcc_mss_q6_bimc_axi_clk",
3027                         .parent_hws = (const struct clk_hw*[]){
3028                                 &bimc_ddr_clk_src.clkr.hw,
3029                         },
3030                         .num_parents = 1,
3031                         .flags = CLK_SET_RATE_PARENT,
3032                         .ops = &clk_branch2_ops,
3033                 },
3034         },
3035 };
3036
3037 static struct clk_branch gcc_oxili_ahb_clk = {
3038         .halt_reg = 0x59028,
3039         .clkr = {
3040                 .enable_reg = 0x59028,
3041                 .enable_mask = BIT(0),
3042                 .hw.init = &(struct clk_init_data){
3043                         .name = "gcc_oxili_ahb_clk",
3044                         .parent_hws = (const struct clk_hw*[]){
3045                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3046                         },
3047                         .num_parents = 1,
3048                         .flags = CLK_SET_RATE_PARENT,
3049                         .ops = &clk_branch2_ops,
3050                 },
3051         },
3052 };
3053
3054 static struct clk_branch gcc_oxili_gfx3d_clk = {
3055         .halt_reg = 0x59020,
3056         .clkr = {
3057                 .enable_reg = 0x59020,
3058                 .enable_mask = BIT(0),
3059                 .hw.init = &(struct clk_init_data){
3060                         .name = "gcc_oxili_gfx3d_clk",
3061                         .parent_hws = (const struct clk_hw*[]){
3062                                 &gfx3d_clk_src.clkr.hw,
3063                         },
3064                         .num_parents = 1,
3065                         .flags = CLK_SET_RATE_PARENT,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch gcc_pdm2_clk = {
3072         .halt_reg = 0x4400c,
3073         .clkr = {
3074                 .enable_reg = 0x4400c,
3075                 .enable_mask = BIT(0),
3076                 .hw.init = &(struct clk_init_data){
3077                         .name = "gcc_pdm2_clk",
3078                         .parent_hws = (const struct clk_hw*[]){
3079                                 &pdm2_clk_src.clkr.hw,
3080                         },
3081                         .num_parents = 1,
3082                         .flags = CLK_SET_RATE_PARENT,
3083                         .ops = &clk_branch2_ops,
3084                 },
3085         },
3086 };
3087
3088 static struct clk_branch gcc_pdm_ahb_clk = {
3089         .halt_reg = 0x44004,
3090         .clkr = {
3091                 .enable_reg = 0x44004,
3092                 .enable_mask = BIT(0),
3093                 .hw.init = &(struct clk_init_data){
3094                         .name = "gcc_pdm_ahb_clk",
3095                         .parent_hws = (const struct clk_hw*[]){
3096                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3097                         },
3098                         .num_parents = 1,
3099                         .flags = CLK_SET_RATE_PARENT,
3100                         .ops = &clk_branch2_ops,
3101                 },
3102         },
3103 };
3104
3105 static struct clk_branch gcc_prng_ahb_clk = {
3106         .halt_reg = 0x13004,
3107         .halt_check = BRANCH_HALT_VOTED,
3108         .clkr = {
3109                 .enable_reg = 0x45004,
3110                 .enable_mask = BIT(8),
3111                 .hw.init = &(struct clk_init_data){
3112                         .name = "gcc_prng_ahb_clk",
3113                         .parent_hws = (const struct clk_hw*[]){
3114                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3115                         },
3116                         .num_parents = 1,
3117                         .ops = &clk_branch2_ops,
3118                 },
3119         },
3120 };
3121
3122 static struct clk_branch gcc_sdcc1_ahb_clk = {
3123         .halt_reg = 0x4201c,
3124         .clkr = {
3125                 .enable_reg = 0x4201c,
3126                 .enable_mask = BIT(0),
3127                 .hw.init = &(struct clk_init_data){
3128                         .name = "gcc_sdcc1_ahb_clk",
3129                         .parent_hws = (const struct clk_hw*[]){
3130                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3131                         },
3132                         .num_parents = 1,
3133                         .flags = CLK_SET_RATE_PARENT,
3134                         .ops = &clk_branch2_ops,
3135                 },
3136         },
3137 };
3138
3139 static struct clk_branch gcc_sdcc1_apps_clk = {
3140         .halt_reg = 0x42018,
3141         .clkr = {
3142                 .enable_reg = 0x42018,
3143                 .enable_mask = BIT(0),
3144                 .hw.init = &(struct clk_init_data){
3145                         .name = "gcc_sdcc1_apps_clk",
3146                         .parent_hws = (const struct clk_hw*[]){
3147                                 &sdcc1_apps_clk_src.clkr.hw,
3148                         },
3149                         .num_parents = 1,
3150                         .flags = CLK_SET_RATE_PARENT,
3151                         .ops = &clk_branch2_ops,
3152                 },
3153         },
3154 };
3155
3156 static struct clk_branch gcc_sdcc2_ahb_clk = {
3157         .halt_reg = 0x4301c,
3158         .clkr = {
3159                 .enable_reg = 0x4301c,
3160                 .enable_mask = BIT(0),
3161                 .hw.init = &(struct clk_init_data){
3162                         .name = "gcc_sdcc2_ahb_clk",
3163                         .parent_hws = (const struct clk_hw*[]){
3164                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3165                         },
3166                         .num_parents = 1,
3167                         .flags = CLK_SET_RATE_PARENT,
3168                         .ops = &clk_branch2_ops,
3169                 },
3170         },
3171 };
3172
3173 static struct clk_branch gcc_sdcc2_apps_clk = {
3174         .halt_reg = 0x43018,
3175         .clkr = {
3176                 .enable_reg = 0x43018,
3177                 .enable_mask = BIT(0),
3178                 .hw.init = &(struct clk_init_data){
3179                         .name = "gcc_sdcc2_apps_clk",
3180                         .parent_hws = (const struct clk_hw*[]){
3181                                 &sdcc2_apps_clk_src.clkr.hw,
3182                         },
3183                         .num_parents = 1,
3184                         .flags = CLK_SET_RATE_PARENT,
3185                         .ops = &clk_branch2_ops,
3186                 },
3187         },
3188 };
3189
3190 static struct clk_branch gcc_apss_tcu_clk = {
3191         .halt_reg = 0x12018,
3192         .halt_check = BRANCH_HALT_VOTED,
3193         .clkr = {
3194                 .enable_reg = 0x4500c,
3195                 .enable_mask = BIT(1),
3196                 .hw.init = &(struct clk_init_data){
3197                         .name = "gcc_apss_tcu_clk",
3198                         .parent_hws = (const struct clk_hw*[]){
3199                                 &bimc_ddr_clk_src.clkr.hw,
3200                         },
3201                         .num_parents = 1,
3202                         .ops = &clk_branch2_ops,
3203                 },
3204         },
3205 };
3206
3207 static struct clk_branch gcc_gfx_tcu_clk = {
3208         .halt_reg = 0x12020,
3209         .halt_check = BRANCH_HALT_VOTED,
3210         .clkr = {
3211                 .enable_reg = 0x4500c,
3212                 .enable_mask = BIT(2),
3213                 .hw.init = &(struct clk_init_data){
3214                         .name = "gcc_gfx_tcu_clk",
3215                         .parent_hws = (const struct clk_hw*[]){
3216                                 &bimc_ddr_clk_src.clkr.hw,
3217                         },
3218                         .num_parents = 1,
3219                         .ops = &clk_branch2_ops,
3220                 },
3221         },
3222 };
3223
3224 static struct clk_branch gcc_gfx_tbu_clk = {
3225         .halt_reg = 0x12010,
3226         .halt_check = BRANCH_HALT_VOTED,
3227         .clkr = {
3228                 .enable_reg = 0x4500c,
3229                 .enable_mask = BIT(3),
3230                 .hw.init = &(struct clk_init_data){
3231                         .name = "gcc_gfx_tbu_clk",
3232                         .parent_hws = (const struct clk_hw*[]){
3233                                 &bimc_ddr_clk_src.clkr.hw,
3234                         },
3235                         .num_parents = 1,
3236                         .ops = &clk_branch2_ops,
3237                 },
3238         },
3239 };
3240
3241 static struct clk_branch gcc_mdp_tbu_clk = {
3242         .halt_reg = 0x1201c,
3243         .halt_check = BRANCH_HALT_VOTED,
3244         .clkr = {
3245                 .enable_reg = 0x4500c,
3246                 .enable_mask = BIT(4),
3247                 .hw.init = &(struct clk_init_data){
3248                         .name = "gcc_mdp_tbu_clk",
3249                         .parent_hws = (const struct clk_hw*[]){
3250                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3251                         },
3252                         .num_parents = 1,
3253                         .flags = CLK_SET_RATE_PARENT,
3254                         .ops = &clk_branch2_ops,
3255                 },
3256         },
3257 };
3258
3259 static struct clk_branch gcc_venus_tbu_clk = {
3260         .halt_reg = 0x12014,
3261         .halt_check = BRANCH_HALT_VOTED,
3262         .clkr = {
3263                 .enable_reg = 0x4500c,
3264                 .enable_mask = BIT(5),
3265                 .hw.init = &(struct clk_init_data){
3266                         .name = "gcc_venus_tbu_clk",
3267                         .parent_hws = (const struct clk_hw*[]){
3268                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3269                         },
3270                         .num_parents = 1,
3271                         .flags = CLK_SET_RATE_PARENT,
3272                         .ops = &clk_branch2_ops,
3273                 },
3274         },
3275 };
3276
3277 static struct clk_branch gcc_vfe_tbu_clk = {
3278         .halt_reg = 0x1203c,
3279         .halt_check = BRANCH_HALT_VOTED,
3280         .clkr = {
3281                 .enable_reg = 0x4500c,
3282                 .enable_mask = BIT(9),
3283                 .hw.init = &(struct clk_init_data){
3284                         .name = "gcc_vfe_tbu_clk",
3285                         .parent_hws = (const struct clk_hw*[]){
3286                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3287                         },
3288                         .num_parents = 1,
3289                         .flags = CLK_SET_RATE_PARENT,
3290                         .ops = &clk_branch2_ops,
3291                 },
3292         },
3293 };
3294
3295 static struct clk_branch gcc_jpeg_tbu_clk = {
3296         .halt_reg = 0x12034,
3297         .halt_check = BRANCH_HALT_VOTED,
3298         .clkr = {
3299                 .enable_reg = 0x4500c,
3300                 .enable_mask = BIT(10),
3301                 .hw.init = &(struct clk_init_data){
3302                         .name = "gcc_jpeg_tbu_clk",
3303                         .parent_hws = (const struct clk_hw*[]){
3304                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3305                         },
3306                         .num_parents = 1,
3307                         .flags = CLK_SET_RATE_PARENT,
3308                         .ops = &clk_branch2_ops,
3309                 },
3310         },
3311 };
3312
3313 static struct clk_branch gcc_smmu_cfg_clk = {
3314         .halt_reg = 0x12038,
3315         .halt_check = BRANCH_HALT_VOTED,
3316         .clkr = {
3317                 .enable_reg = 0x4500c,
3318                 .enable_mask = BIT(12),
3319                 .hw.init = &(struct clk_init_data){
3320                         .name = "gcc_smmu_cfg_clk",
3321                         .parent_hws = (const struct clk_hw*[]){
3322                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3323                         },
3324                         .num_parents = 1,
3325                         .flags = CLK_SET_RATE_PARENT,
3326                         .ops = &clk_branch2_ops,
3327                 },
3328         },
3329 };
3330
3331 static struct clk_branch gcc_gtcu_ahb_clk = {
3332         .halt_reg = 0x12044,
3333         .halt_check = BRANCH_HALT_VOTED,
3334         .clkr = {
3335                 .enable_reg = 0x4500c,
3336                 .enable_mask = BIT(13),
3337                 .hw.init = &(struct clk_init_data){
3338                         .name = "gcc_gtcu_ahb_clk",
3339                         .parent_hws = (const struct clk_hw*[]){
3340                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3341                         },
3342                         .num_parents = 1,
3343                         .flags = CLK_SET_RATE_PARENT,
3344                         .ops = &clk_branch2_ops,
3345                 },
3346         },
3347 };
3348
3349 static struct clk_branch gcc_cpp_tbu_clk = {
3350         .halt_reg = 0x12040,
3351         .halt_check = BRANCH_HALT_VOTED,
3352         .clkr = {
3353                 .enable_reg = 0x4500c,
3354                 .enable_mask = BIT(14),
3355                 .hw.init = &(struct clk_init_data){
3356                         .name = "gcc_cpp_tbu_clk",
3357                         .parent_hws = (const struct clk_hw*[]){
3358                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3359                         },
3360                         .num_parents = 1,
3361                         .flags = CLK_SET_RATE_PARENT,
3362                         .ops = &clk_branch2_ops,
3363                 },
3364         },
3365 };
3366
3367 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3368         .halt_reg = 0x1201c,
3369         .halt_check = BRANCH_HALT_VOTED,
3370         .clkr = {
3371                 .enable_reg = 0x4500c,
3372                 .enable_mask = BIT(15),
3373                 .hw.init = &(struct clk_init_data){
3374                         .name = "gcc_mdp_rt_tbu_clk",
3375                         .parent_hws = (const struct clk_hw*[]){
3376                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3377                         },
3378                         .num_parents = 1,
3379                         .flags = CLK_SET_RATE_PARENT,
3380                         .ops = &clk_branch2_ops,
3381                 },
3382         },
3383 };
3384
3385 static struct clk_branch gcc_bimc_gfx_clk = {
3386         .halt_reg = 0x31024,
3387         .clkr = {
3388                 .enable_reg = 0x31024,
3389                 .enable_mask = BIT(0),
3390                 .hw.init = &(struct clk_init_data){
3391                         .name = "gcc_bimc_gfx_clk",
3392                         .parent_hws = (const struct clk_hw*[]){
3393                                 &bimc_gpu_clk_src.clkr.hw,
3394                         },
3395                         .num_parents = 1,
3396                         .flags = CLK_SET_RATE_PARENT,
3397                         .ops = &clk_branch2_ops,
3398                 },
3399         },
3400 };
3401
3402 static struct clk_branch gcc_bimc_gpu_clk = {
3403         .halt_reg = 0x31040,
3404         .clkr = {
3405                 .enable_reg = 0x31040,
3406                 .enable_mask = BIT(0),
3407                 .hw.init = &(struct clk_init_data){
3408                         .name = "gcc_bimc_gpu_clk",
3409                         .parent_hws = (const struct clk_hw*[]){
3410                                 &bimc_gpu_clk_src.clkr.hw,
3411                         },
3412                         .num_parents = 1,
3413                         .flags = CLK_SET_RATE_PARENT,
3414                         .ops = &clk_branch2_ops,
3415                 },
3416         },
3417 };
3418
3419 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3420         .halt_reg = 0x4102c,
3421         .clkr = {
3422                 .enable_reg = 0x4102c,
3423                 .enable_mask = BIT(0),
3424                 .hw.init = &(struct clk_init_data){
3425                         .name = "gcc_usb2a_phy_sleep_clk",
3426                         .ops = &clk_branch2_ops,
3427                 },
3428         },
3429 };
3430
3431 static struct clk_branch gcc_usb_fs_ahb_clk = {
3432         .halt_reg = 0x3f008,
3433         .clkr = {
3434                 .enable_reg = 0x3f008,
3435                 .enable_mask = BIT(0),
3436                 .hw.init = &(struct clk_init_data){
3437                         .name = "gcc_usb_fs_ahb_clk",
3438                         .parent_hws = (const struct clk_hw*[]){
3439                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3440                         },
3441                         .num_parents = 1,
3442                         .flags = CLK_SET_RATE_PARENT,
3443                         .ops = &clk_branch2_ops,
3444                 },
3445         },
3446 };
3447
3448 static struct clk_branch gcc_usb_fs_ic_clk = {
3449         .halt_reg = 0x3f030,
3450         .clkr = {
3451                 .enable_reg = 0x3f030,
3452                 .enable_mask = BIT(0),
3453                 .hw.init = &(struct clk_init_data){
3454                         .name = "gcc_usb_fs_ic_clk",
3455                         .parent_hws = (const struct clk_hw*[]){
3456                                 &usb_fs_ic_clk_src.clkr.hw,
3457                         },
3458                         .num_parents = 1,
3459                         .flags = CLK_SET_RATE_PARENT,
3460                         .ops = &clk_branch2_ops,
3461                 },
3462         },
3463 };
3464
3465 static struct clk_branch gcc_usb_fs_system_clk = {
3466         .halt_reg = 0x3f004,
3467         .clkr = {
3468                 .enable_reg = 0x3f004,
3469                 .enable_mask = BIT(0),
3470                 .hw.init = &(struct clk_init_data){
3471                         .name = "gcc_usb_fs_system_clk",
3472                         .parent_hws = (const struct clk_hw*[]){
3473                                 &usb_fs_system_clk_src.clkr.hw,
3474                         },
3475                         .num_parents = 1,
3476                         .flags = CLK_SET_RATE_PARENT,
3477                         .ops = &clk_branch2_ops,
3478                 },
3479         },
3480 };
3481
3482 static struct clk_branch gcc_usb_hs_ahb_clk = {
3483         .halt_reg = 0x41008,
3484         .clkr = {
3485                 .enable_reg = 0x41008,
3486                 .enable_mask = BIT(0),
3487                 .hw.init = &(struct clk_init_data){
3488                         .name = "gcc_usb_hs_ahb_clk",
3489                         .parent_hws = (const struct clk_hw*[]){
3490                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3491                         },
3492                         .num_parents = 1,
3493                         .flags = CLK_SET_RATE_PARENT,
3494                         .ops = &clk_branch2_ops,
3495                 },
3496         },
3497 };
3498
3499 static struct clk_branch gcc_usb_hs_system_clk = {
3500         .halt_reg = 0x41004,
3501         .clkr = {
3502                 .enable_reg = 0x41004,
3503                 .enable_mask = BIT(0),
3504                 .hw.init = &(struct clk_init_data){
3505                         .name = "gcc_usb_hs_system_clk",
3506                         .parent_hws = (const struct clk_hw*[]){
3507                                 &usb_hs_system_clk_src.clkr.hw,
3508                         },
3509                         .num_parents = 1,
3510                         .flags = CLK_SET_RATE_PARENT,
3511                         .ops = &clk_branch2_ops,
3512                 },
3513         },
3514 };
3515
3516 static struct clk_branch gcc_venus0_ahb_clk = {
3517         .halt_reg = 0x4c020,
3518         .clkr = {
3519                 .enable_reg = 0x4c020,
3520                 .enable_mask = BIT(0),
3521                 .hw.init = &(struct clk_init_data){
3522                         .name = "gcc_venus0_ahb_clk",
3523                         .parent_hws = (const struct clk_hw*[]){
3524                                 &pcnoc_bfdcd_clk_src.clkr.hw,
3525                         },
3526                         .num_parents = 1,
3527                         .flags = CLK_SET_RATE_PARENT,
3528                         .ops = &clk_branch2_ops,
3529                 },
3530         },
3531 };
3532
3533 static struct clk_branch gcc_venus0_axi_clk = {
3534         .halt_reg = 0x4c024,
3535         .clkr = {
3536                 .enable_reg = 0x4c024,
3537                 .enable_mask = BIT(0),
3538                 .hw.init = &(struct clk_init_data){
3539                         .name = "gcc_venus0_axi_clk",
3540                         .parent_hws = (const struct clk_hw*[]){
3541                                 &system_mm_noc_bfdcd_clk_src.clkr.hw,
3542                         },
3543                         .num_parents = 1,
3544                         .flags = CLK_SET_RATE_PARENT,
3545                         .ops = &clk_branch2_ops,
3546                 },
3547         },
3548 };
3549
3550 static struct clk_branch gcc_venus0_vcodec0_clk = {
3551         .halt_reg = 0x4c01c,
3552         .clkr = {
3553                 .enable_reg = 0x4c01c,
3554                 .enable_mask = BIT(0),
3555                 .hw.init = &(struct clk_init_data){
3556                         .name = "gcc_venus0_vcodec0_clk",
3557                         .parent_hws = (const struct clk_hw*[]){
3558                                 &vcodec0_clk_src.clkr.hw,
3559                         },
3560                         .num_parents = 1,
3561                         .flags = CLK_SET_RATE_PARENT,
3562                         .ops = &clk_branch2_ops,
3563                 },
3564         },
3565 };
3566
3567 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3568         .halt_reg = 0x4c02c,
3569         .clkr = {
3570                 .enable_reg = 0x4c02c,
3571                 .enable_mask = BIT(0),
3572                 .hw.init = &(struct clk_init_data){
3573                         .name = "gcc_venus0_core0_vcodec0_clk",
3574                         .parent_hws = (const struct clk_hw*[]){
3575                                 &vcodec0_clk_src.clkr.hw,
3576                         },
3577                         .num_parents = 1,
3578                         .flags = CLK_SET_RATE_PARENT,
3579                         .ops = &clk_branch2_ops,
3580                 },
3581         },
3582 };
3583
3584 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3585         .halt_reg = 0x4c034,
3586         .clkr = {
3587                 .enable_reg = 0x4c034,
3588                 .enable_mask = BIT(0),
3589                 .hw.init = &(struct clk_init_data){
3590                         .name = "gcc_venus0_core1_vcodec0_clk",
3591                         .parent_hws = (const struct clk_hw*[]){
3592                                 &vcodec0_clk_src.clkr.hw,
3593                         },
3594                         .num_parents = 1,
3595                         .flags = CLK_SET_RATE_PARENT,
3596                         .ops = &clk_branch2_ops,
3597                 },
3598         },
3599 };
3600
3601 static struct clk_branch gcc_oxili_timer_clk = {
3602         .halt_reg = 0x59040,
3603         .clkr = {
3604                 .enable_reg = 0x59040,
3605                 .enable_mask = BIT(0),
3606                 .hw.init = &(struct clk_init_data){
3607                         .name = "gcc_oxili_timer_clk",
3608                         .ops = &clk_branch2_ops,
3609                 },
3610         },
3611 };
3612
3613 static struct gdsc venus_gdsc = {
3614         .gdscr = 0x4c018,
3615         .pd = {
3616                 .name = "venus",
3617         },
3618         .pwrsts = PWRSTS_OFF_ON,
3619 };
3620
3621 static struct gdsc mdss_gdsc = {
3622         .gdscr = 0x4d078,
3623         .pd = {
3624                 .name = "mdss",
3625         },
3626         .pwrsts = PWRSTS_OFF_ON,
3627 };
3628
3629 static struct gdsc jpeg_gdsc = {
3630         .gdscr = 0x5701c,
3631         .pd = {
3632                 .name = "jpeg",
3633         },
3634         .pwrsts = PWRSTS_OFF_ON,
3635 };
3636
3637 static struct gdsc vfe_gdsc = {
3638         .gdscr = 0x58034,
3639         .pd = {
3640                 .name = "vfe",
3641         },
3642         .pwrsts = PWRSTS_OFF_ON,
3643 };
3644
3645 static struct gdsc oxili_gdsc = {
3646         .gdscr = 0x5901c,
3647         .pd = {
3648                 .name = "oxili",
3649         },
3650         .pwrsts = PWRSTS_OFF_ON,
3651 };
3652
3653 static struct gdsc venus_core0_gdsc = {
3654         .gdscr = 0x4c028,
3655         .pd = {
3656                 .name = "venus_core0",
3657         },
3658         .pwrsts = PWRSTS_OFF_ON,
3659 };
3660
3661 static struct gdsc venus_core1_gdsc = {
3662         .gdscr = 0x4c030,
3663         .pd = {
3664                 .name = "venus_core1",
3665         },
3666         .pwrsts = PWRSTS_OFF_ON,
3667 };
3668
3669 static struct clk_regmap *gcc_msm8939_clocks[] = {
3670         [GPLL0] = &gpll0.clkr,
3671         [GPLL0_VOTE] = &gpll0_vote,
3672         [BIMC_PLL] = &bimc_pll.clkr,
3673         [BIMC_PLL_VOTE] = &bimc_pll_vote,
3674         [GPLL1] = &gpll1.clkr,
3675         [GPLL1_VOTE] = &gpll1_vote,
3676         [GPLL2] = &gpll2.clkr,
3677         [GPLL2_VOTE] = &gpll2_vote,
3678         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3679         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3680         [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
3681         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3682         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3683         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3684         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3685         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3686         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3687         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3688         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3689         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3690         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3691         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3692         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3693         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3694         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3695         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3696         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3697         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3698         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3699         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3700         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3701         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3702         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3703         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3704         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3705         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3706         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3707         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3708         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3709         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3710         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3711         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3712         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3713         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3714         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3715         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3716         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3717         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3718         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3719         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3720         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3721         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3722         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3723         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3724         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3725         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3726         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3727         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3728         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3729         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3730         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3731         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3732         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3733         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3734         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3735         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3736         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3737         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3738         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3739         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3740         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3741         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3742         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3743         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3744         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3745         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3746         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3747         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3748         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3749         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3750         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3751         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3752         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3753         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3754         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3755         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3756         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3757         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3758         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3759         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3760         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3761         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3762         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3763         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3764         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3765         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3766         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3767         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3768         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3769         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3770         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3771         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3772         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3773         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3774         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3775         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3776         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3777         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3778         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3779         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3780         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3781         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3782         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3783         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3784         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3785         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3786         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3787         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3788         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3789         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3790         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3791         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3792         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3793         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3794         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3795         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3796         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3797         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3798         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3799         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3800         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3801         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3802         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3803         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3804         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3805         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3806         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3807         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3808         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3809         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3810         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3811         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3812         [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3813         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3814         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3815         [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3816         [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3817         [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3818         [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3819         [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3820         [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3821         [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3822         [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3823         [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3824         [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3825         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3826         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3827         [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3828         [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3829         [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3830         [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3831         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3832         [GPLL3] = &gpll3.clkr,
3833         [GPLL3_VOTE] = &gpll3_vote,
3834         [GPLL4] = &gpll4.clkr,
3835         [GPLL4_VOTE] = &gpll4_vote,
3836         [GPLL5] = &gpll5.clkr,
3837         [GPLL5_VOTE] = &gpll5_vote,
3838         [GPLL6] = &gpll6.clkr,
3839         [GPLL6_VOTE] = &gpll6_vote,
3840         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3841         [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3842         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3843         [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3844         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3845         [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3846         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3847         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3848         [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3849         [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3850         [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3851         [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3852         [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3853         [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3854         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3855         [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3856         [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3857 };
3858
3859 static struct gdsc *gcc_msm8939_gdscs[] = {
3860         [VENUS_GDSC] = &venus_gdsc,
3861         [MDSS_GDSC] = &mdss_gdsc,
3862         [JPEG_GDSC] = &jpeg_gdsc,
3863         [VFE_GDSC] = &vfe_gdsc,
3864         [OXILI_GDSC] = &oxili_gdsc,
3865         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3866         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3867 };
3868
3869 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3870         [GCC_BLSP1_BCR] = { 0x01000 },
3871         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3872         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3873         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3874         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3875         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3876         [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3877         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3878         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3879         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3880         [GCC_IMEM_BCR] = { 0x0e000 },
3881         [GCC_SMMU_BCR] = { 0x12000 },
3882         [GCC_APSS_TCU_BCR] = { 0x12050 },
3883         [GCC_SMMU_XPU_BCR] = { 0x12054 },
3884         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3885         [GCC_PRNG_BCR] = { 0x13000 },
3886         [GCC_BOOT_ROM_BCR] = { 0x13008 },
3887         [GCC_CRYPTO_BCR] = { 0x16000 },
3888         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3889         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3890         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3891         [GCC_DEHR_BCR] = { 0x1f000 },
3892         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3893         [GCC_PCNOC_BCR] = { 0x27018 },
3894         [GCC_TCSR_BCR] = { 0x28000 },
3895         [GCC_QDSS_BCR] = { 0x29000 },
3896         [GCC_DCD_BCR] = { 0x2a000 },
3897         [GCC_MSG_RAM_BCR] = { 0x2b000 },
3898         [GCC_MPM_BCR] = { 0x2c000 },
3899         [GCC_SPMI_BCR] = { 0x2e000 },
3900         [GCC_SPDM_BCR] = { 0x2f000 },
3901         [GCC_MM_SPDM_BCR] = { 0x2f024 },
3902         [GCC_BIMC_BCR] = { 0x31000 },
3903         [GCC_RBCPR_BCR] = { 0x33000 },
3904         [GCC_TLMM_BCR] = { 0x34000 },
3905         [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3906         [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3907         [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3908         [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3909         [GCC_USB_FS_BCR] = { 0x3f000 },
3910         [GCC_USB_HS_BCR] = { 0x41000 },
3911         [GCC_USB2A_PHY_BCR] = { 0x41028 },
3912         [GCC_SDCC1_BCR] = { 0x42000 },
3913         [GCC_SDCC2_BCR] = { 0x43000 },
3914         [GCC_PDM_BCR] = { 0x44000 },
3915         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3916         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3917         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3918         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3919         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3920         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3921         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3922         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3923         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3924         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3925         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3926         [GCC_MMSS_BCR] = { 0x4b000 },
3927         [GCC_VENUS0_BCR] = { 0x4c014 },
3928         [GCC_MDSS_BCR] = { 0x4d074 },
3929         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3930         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3931         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3932         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3933         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3934         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3935         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3936         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3937         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3938         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3939         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3940         [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3941         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3942         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3943         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3944         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3945         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3946         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3947         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3948         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3949         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3950         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3951         [GCC_OXILI_BCR] = { 0x59018 },
3952         [GCC_GMEM_BCR] = { 0x5902c },
3953         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3954         [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3955         [GCC_MDP_TBU_BCR] = { 0x62000 },
3956         [GCC_GFX_TBU_BCR] = { 0x63000 },
3957         [GCC_GFX_TCU_BCR] = { 0x64000 },
3958         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3959         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3960         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3961         [GCC_GTCU_AHB_BCR] = { 0x68000 },
3962         [GCC_SMMU_CFG_BCR] = { 0x69000 },
3963         [GCC_VFE_TBU_BCR] = { 0x6a000 },
3964         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3965         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3966         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3967         [GCC_CPP_TBU_BCR] = { 0x6e000 },
3968         [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3969         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3970 };
3971
3972 static const struct regmap_config gcc_msm8939_regmap_config = {
3973         .reg_bits       = 32,
3974         .reg_stride     = 4,
3975         .val_bits       = 32,
3976         .max_register   = 0x80000,
3977         .fast_io        = true,
3978 };
3979
3980 static const struct qcom_cc_desc gcc_msm8939_desc = {
3981         .config = &gcc_msm8939_regmap_config,
3982         .clks = gcc_msm8939_clocks,
3983         .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3984         .resets = gcc_msm8939_resets,
3985         .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3986         .gdscs = gcc_msm8939_gdscs,
3987         .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3988 };
3989
3990 static const struct of_device_id gcc_msm8939_match_table[] = {
3991         { .compatible = "qcom,gcc-msm8939" },
3992         { }
3993 };
3994 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3995
3996 static int gcc_msm8939_probe(struct platform_device *pdev)
3997 {
3998         struct regmap *regmap;
3999
4000         regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
4001         if (IS_ERR(regmap))
4002                 return PTR_ERR(regmap);
4003
4004         clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
4005         clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
4006
4007         return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
4008 }
4009
4010 static struct platform_driver gcc_msm8939_driver = {
4011         .probe          = gcc_msm8939_probe,
4012         .driver         = {
4013                 .name   = "gcc-msm8939",
4014                 .of_match_table = gcc_msm8939_match_table,
4015         },
4016 };
4017
4018 static int __init gcc_msm8939_init(void)
4019 {
4020         return platform_driver_register(&gcc_msm8939_driver);
4021 }
4022 core_initcall(gcc_msm8939_init);
4023
4024 static void __exit gcc_msm8939_exit(void)
4025 {
4026         platform_driver_unregister(&gcc_msm8939_driver);
4027 }
4028 module_exit(gcc_msm8939_exit);
4029
4030 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
4031 MODULE_LICENSE("GPL v2");