gcc-ipq6018.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/regmap.h>
  13
  14 #include <linux/reset-controller.h>
  15 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  16 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  17
  18 #include "common.h"
  19 #include "clk-regmap.h"
  20 #include "clk-pll.h"
  21 #include "clk-rcg.h"
  22 #include "clk-branch.h"
  23 #include "clk-alpha-pll.h"
  24 #include "clk-regmap-divider.h"
  25 #include "clk-regmap-mux.h"
  26 #include "reset.h"
  27
  28 enum {
  29         P_XO,
  30         P_BIAS_PLL,
  31         P_UNIPHY0_RX,
  32         P_UNIPHY0_TX,
  33         P_UNIPHY1_RX,
  34         P_BIAS_PLL_NSS_NOC,
  35         P_UNIPHY1_TX,
  36         P_PCIE20_PHY0_PIPE,
  37         P_USB3PHY_0_PIPE,
  38         P_GPLL0,
  39         P_GPLL0_DIV2,
  40         P_GPLL2,
  41         P_GPLL4,
  42         P_GPLL6,
  43         P_SLEEP_CLK,
  44         P_UBI32_PLL,
  45         P_NSS_CRYPTO_PLL,
  46         P_PI_SLEEP,
  47 };
  48
  49 static struct clk_alpha_pll gpll0_main = {
  50         .offset = 0x21000,
  51         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  52         .clkr = {
  53                 .enable_reg = 0x0b000,
  54                 .enable_mask = BIT(0),
  55                 .hw.init = &(struct clk_init_data){
  56                         .name = "gpll0_main",
  57                         .parent_data = &(const struct clk_parent_data){
  58                                 .fw_name = "xo",
  59                         },
  60                         .num_parents = 1,
  61                         .ops = &clk_alpha_pll_ops,
  62                 },
  63         },
  64 };
  65
  66 static struct clk_fixed_factor gpll0_out_main_div2 = {
  67         .mult = 1,
  68         .div = 2,
  69         .hw.init = &(struct clk_init_data){
  70                 .name = "gpll0_out_main_div2",
  71                 .parent_hws = (const struct clk_hw *[]){
  72                                 &gpll0_main.clkr.hw },
  73                 .num_parents = 1,
  74                 .ops = &clk_fixed_factor_ops,
  75         },
  76 };
  77
  78 static struct clk_alpha_pll_postdiv gpll0 = {
  79         .offset = 0x21000,
  80         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  81         .width = 4,
  82         .clkr.hw.init = &(struct clk_init_data){
  83                 .name = "gpll0",
  84                 .parent_hws = (const struct clk_hw *[]){
  85                                 &gpll0_main.clkr.hw },
  86                 .num_parents = 1,
  87                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  88         },
  89 };
  90
  91 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
  92         { .fw_name = "xo" },
  93         { .hw = &gpll0.clkr.hw},
  94         { .hw = &gpll0_out_main_div2.hw},
  95 };
  96
  97 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  98         { P_XO, 0 },
  99         { P_GPLL0, 1 },
 100         { P_GPLL0_DIV2, 4 },
 101 };
 102
 103 static struct clk_alpha_pll ubi32_pll_main = {
 104         .offset = 0x25000,
 105         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 106         .flags = SUPPORTS_DYNAMIC_UPDATE,
 107         .clkr = {
 108                 .enable_reg = 0x0b000,
 109                 .enable_mask = BIT(6),
 110                 .hw.init = &(struct clk_init_data){
 111                         .name = "ubi32_pll_main",
 112                         .parent_data = &(const struct clk_parent_data){
 113                                 .fw_name = "xo",
 114                         },
 115                         .num_parents = 1,
 116                         .ops = &clk_alpha_pll_huayra_ops,
 117                 },
 118         },
 119 };
 120
 121 static struct clk_alpha_pll_postdiv ubi32_pll = {
 122         .offset = 0x25000,
 123         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 124         .width = 2,
 125         .clkr.hw.init = &(struct clk_init_data){
 126                 .name = "ubi32_pll",
 127                 .parent_hws = (const struct clk_hw *[]){
 128                                 &ubi32_pll_main.clkr.hw },
 129                 .num_parents = 1,
 130                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 131                 .flags = CLK_SET_RATE_PARENT,
 132         },
 133 };
 134
 135 static struct clk_alpha_pll gpll6_main = {
 136         .offset = 0x37000,
 137         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 138         .clkr = {
 139                 .enable_reg = 0x0b000,
 140                 .enable_mask = BIT(7),
 141                 .hw.init = &(struct clk_init_data){
 142                         .name = "gpll6_main",
 143                         .parent_data = &(const struct clk_parent_data){
 144                                 .fw_name = "xo",
 145                         },
 146                         .num_parents = 1,
 147                         .ops = &clk_alpha_pll_ops,
 148                 },
 149         },
 150 };
 151
 152 static struct clk_alpha_pll_postdiv gpll6 = {
 153         .offset = 0x37000,
 154         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 155         .width = 2,
 156         .clkr.hw.init = &(struct clk_init_data){
 157                 .name = "gpll6",
 158                 .parent_hws = (const struct clk_hw *[]){
 159                                 &gpll6_main.clkr.hw },
 160                 .num_parents = 1,
 161                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 162         },
 163 };
 164
 165 static struct clk_alpha_pll gpll4_main = {
 166         .offset = 0x24000,
 167         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 168         .clkr = {
 169                 .enable_reg = 0x0b000,
 170                 .enable_mask = BIT(5),
 171                 .hw.init = &(struct clk_init_data){
 172                         .name = "gpll4_main",
 173                         .parent_data = &(const struct clk_parent_data){
 174                                 .fw_name = "xo",
 175                         },
 176                         .num_parents = 1,
 177                         .ops = &clk_alpha_pll_ops,
 178                 },
 179         },
 180 };
 181
 182 static struct clk_alpha_pll_postdiv gpll4 = {
 183         .offset = 0x24000,
 184         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 185         .width = 4,
 186         .clkr.hw.init = &(struct clk_init_data){
 187                 .name = "gpll4",
 188                 .parent_hws = (const struct clk_hw *[]){
 189                                 &gpll4_main.clkr.hw },
 190                 .num_parents = 1,
 191                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 192         },
 193 };
 194
 195 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 196         F(24000000, P_XO, 1, 0, 0),
 197         F(50000000, P_GPLL0, 16, 0, 0),
 198         F(100000000, P_GPLL0, 8, 0, 0),
 199         { }
 200 };
 201
 202 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 203         .cmd_rcgr = 0x27000,
 204         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 205         .hid_width = 5,
 206         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 207         .clkr.hw.init = &(struct clk_init_data){
 208                 .name = "pcnoc_bfdcd_clk_src",
 209                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 210                 .num_parents = 3,
 211                 .ops = &clk_rcg2_ops,
 212         },
 213 };
 214
 215 static struct clk_alpha_pll gpll2_main = {
 216         .offset = 0x4a000,
 217         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 218         .clkr = {
 219                 .enable_reg = 0x0b000,
 220                 .enable_mask = BIT(2),
 221                 .hw.init = &(struct clk_init_data){
 222                         .name = "gpll2_main",
 223                         .parent_data = &(const struct clk_parent_data){
 224                                 .fw_name = "xo",
 225                         },
 226                         .num_parents = 1,
 227                         .ops = &clk_alpha_pll_ops,
 228                 },
 229         },
 230 };
 231
 232 static struct clk_alpha_pll_postdiv gpll2 = {
 233         .offset = 0x4a000,
 234         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 235         .width = 4,
 236         .clkr.hw.init = &(struct clk_init_data){
 237                 .name = "gpll2",
 238                 .parent_hws = (const struct clk_hw *[]){
 239                                 &gpll2_main.clkr.hw },
 240                 .num_parents = 1,
 241                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 242         },
 243 };
 244
 245 static struct clk_alpha_pll nss_crypto_pll_main = {
 246         .offset = 0x22000,
 247         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 248         .clkr = {
 249                 .enable_reg = 0x0b000,
 250                 .enable_mask = BIT(4),
 251                 .hw.init = &(struct clk_init_data){
 252                         .name = "nss_crypto_pll_main",
 253                         .parent_data = &(const struct clk_parent_data){
 254                                 .fw_name = "xo",
 255                         },
 256                         .num_parents = 1,
 257                         .ops = &clk_alpha_pll_ops,
 258                 },
 259         },
 260 };
 261
 262 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 263         .offset = 0x22000,
 264         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 265         .width = 4,
 266         .clkr.hw.init = &(struct clk_init_data){
 267                 .name = "nss_crypto_pll",
 268                 .parent_hws = (const struct clk_hw *[]){
 269                                 &nss_crypto_pll_main.clkr.hw },
 270                 .num_parents = 1,
 271                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 272         },
 273 };
 274
 275 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
 276         F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
 277         F(320000000, P_GPLL0, 2.5, 0, 0),
 278         F(600000000, P_GPLL4, 2, 0, 0),
 279         { }
 280 };
 281
 282 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
 283         { .fw_name = "xo" },
 284         { .hw = &gpll4.clkr.hw },
 285         { .hw = &gpll0.clkr.hw },
 286         { .hw = &gpll6.clkr.hw },
 287         { .hw = &gpll0_out_main_div2.hw },
 288 };
 289
 290 static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
 291         { P_XO, 0 },
 292         { P_GPLL4, 1 },
 293         { P_GPLL0, 2 },
 294         { P_GPLL6, 3 },
 295         { P_GPLL0_DIV2, 4 },
 296 };
 297
 298 static struct clk_rcg2 qdss_tsctr_clk_src = {
 299         .cmd_rcgr = 0x29064,
 300         .freq_tbl = ftbl_qdss_tsctr_clk_src,
 301         .hid_width = 5,
 302         .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 303         .clkr.hw.init = &(struct clk_init_data){
 304                 .name = "qdss_tsctr_clk_src",
 305                 .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 306                 .num_parents = 5,
 307                 .ops = &clk_rcg2_ops,
 308         },
 309 };
 310
 311 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
 312         .mult = 1,
 313         .div = 4,
 314         .hw.init = &(struct clk_init_data){
 315                 .name = "qdss_dap_sync_clk_src",
 316                 .parent_hws = (const struct clk_hw *[]){
 317                                 &qdss_tsctr_clk_src.clkr.hw },
 318                 .num_parents = 1,
 319                 .ops = &clk_fixed_factor_ops,
 320         },
 321 };
 322
 323 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 324         F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 325         F(240000000, P_GPLL4, 5, 0, 0),
 326         { }
 327 };
 328
 329 static struct clk_rcg2 qdss_at_clk_src = {
 330         .cmd_rcgr = 0x2900c,
 331         .freq_tbl = ftbl_qdss_at_clk_src,
 332         .hid_width = 5,
 333         .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 334         .clkr.hw.init = &(struct clk_init_data){
 335                 .name = "qdss_at_clk_src",
 336                 .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 337                 .num_parents = 5,
 338                 .ops = &clk_rcg2_ops,
 339         },
 340 };
 341
 342 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
 343         .mult = 1,
 344         .div = 2,
 345         .hw.init = &(struct clk_init_data){
 346                 .name = "qdss_tsctr_div2_clk_src",
 347                 .parent_hws = (const struct clk_hw *[]){
 348                                 &qdss_tsctr_clk_src.clkr.hw },
 349                 .num_parents = 1,
 350                 .flags = CLK_SET_RATE_PARENT,
 351                 .ops = &clk_fixed_factor_ops,
 352         },
 353 };
 354
 355 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 356         F(24000000, P_XO, 1, 0, 0),
 357         F(300000000, P_BIAS_PLL, 1, 0, 0),
 358         { }
 359 };
 360
 361 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 362         { .fw_name = "xo" },
 363         { .fw_name = "bias_pll_cc_clk" },
 364         { .hw = &gpll0.clkr.hw },
 365         { .hw = &gpll4.clkr.hw },
 366         { .hw = &nss_crypto_pll.clkr.hw },
 367         { .hw = &ubi32_pll.clkr.hw },
 368 };
 369
 370 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 371         { P_XO, 0 },
 372         { P_BIAS_PLL, 1 },
 373         { P_GPLL0, 2 },
 374         { P_GPLL4, 3 },
 375         { P_NSS_CRYPTO_PLL, 4 },
 376         { P_UBI32_PLL, 5 },
 377 };
 378
 379 static struct clk_rcg2 nss_ppe_clk_src = {
 380         .cmd_rcgr = 0x68080,
 381         .freq_tbl = ftbl_nss_ppe_clk_src,
 382         .hid_width = 5,
 383         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
 384         .clkr.hw.init = &(struct clk_init_data){
 385                 .name = "nss_ppe_clk_src",
 386                 .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
 387                 .num_parents = 6,
 388                 .ops = &clk_rcg2_ops,
 389         },
 390 };
 391
 392 static struct clk_branch gcc_xo_clk_src = {
 393         .halt_reg = 0x30018,
 394         .clkr = {
 395                 .enable_reg = 0x30018,
 396                 .enable_mask = BIT(1),
 397                 .hw.init = &(struct clk_init_data){
 398                         .name = "gcc_xo_clk_src",
 399                         .parent_data = &(const struct clk_parent_data){
 400                                 .fw_name = "xo",
 401                         },
 402                         .num_parents = 1,
 403                         .flags = CLK_SET_RATE_PARENT,
 404                         .ops = &clk_branch2_ops,
 405                 },
 406         },
 407 };
 408
 409 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
 410         F(24000000, P_XO, 1, 0, 0),
 411         F(200000000, P_GPLL0, 4, 0, 0),
 412         { }
 413 };
 414
 415 static const struct clk_parent_data gcc_xo_gpll0[] = {
 416         { .fw_name = "xo" },
 417         { .hw = &gpll0.clkr.hw },
 418 };
 419
 420 static const struct parent_map gcc_xo_gpll0_map[] = {
 421         { P_XO, 0 },
 422         { P_GPLL0, 1 },
 423 };
 424
 425 static struct clk_rcg2 nss_ce_clk_src = {
 426         .cmd_rcgr = 0x68098,
 427         .freq_tbl = ftbl_nss_ce_clk_src,
 428         .hid_width = 5,
 429         .parent_map = gcc_xo_gpll0_map,
 430         .clkr.hw.init = &(struct clk_init_data){
 431                 .name = "nss_ce_clk_src",
 432                 .parent_data = gcc_xo_gpll0,
 433                 .num_parents = 2,
 434                 .ops = &clk_rcg2_ops,
 435         },
 436 };
 437
 438 static struct clk_branch gcc_sleep_clk_src = {
 439         .halt_reg = 0x30000,
 440         .clkr = {
 441                 .enable_reg = 0x30000,
 442                 .enable_mask = BIT(1),
 443                 .hw.init = &(struct clk_init_data){
 444                         .name = "gcc_sleep_clk_src",
 445                         .parent_data = &(const struct clk_parent_data){
 446                                 .fw_name = "sleep_clk",
 447                         },
 448                         .num_parents = 1,
 449                         .ops = &clk_branch2_ops,
 450                 },
 451         },
 452 };
 453
 454 static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
 455         F(24000000, P_XO, 1, 0, 0),
 456         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 457         F(100000000, P_GPLL0, 8, 0, 0),
 458         F(133333333, P_GPLL0, 6, 0, 0),
 459         F(160000000, P_GPLL0, 5, 0, 0),
 460         F(200000000, P_GPLL0, 4, 0, 0),
 461         F(266666667, P_GPLL0, 3, 0, 0),
 462         { }
 463 };
 464
 465 static const struct clk_parent_data
 466                         gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 467         { .fw_name = "xo" },
 468         { .hw = &gpll0.clkr.hw },
 469         { .hw = &gpll6.clkr.hw },
 470         { .hw = &gpll0_out_main_div2.hw },
 471 };
 472
 473 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 474         { P_XO, 0 },
 475         { P_GPLL0, 1 },
 476         { P_GPLL6, 2 },
 477         { P_GPLL0_DIV2, 3 },
 478 };
 479
 480 static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
 481         .cmd_rcgr = 0x76054,
 482         .freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
 483         .hid_width = 5,
 484         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
 485         .clkr.hw.init = &(struct clk_init_data){
 486                 .name = "snoc_nssnoc_bfdcd_clk_src",
 487                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
 488                 .num_parents = 4,
 489                 .ops = &clk_rcg2_ops,
 490         },
 491 };
 492
 493 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 494         F(24000000, P_XO, 1, 0, 0),
 495         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 496         F(50000000, P_GPLL0, 16, 0, 0),
 497         F(100000000, P_GPLL0, 8, 0, 0),
 498         { }
 499 };
 500
 501 static struct clk_rcg2 apss_ahb_clk_src = {
 502         .cmd_rcgr = 0x46000,
 503         .freq_tbl = ftbl_apss_ahb_clk_src,
 504         .hid_width = 5,
 505         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 506         .clkr.hw.init = &(struct clk_init_data){
 507                 .name = "apss_ahb_clk_src",
 508                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 509                 .num_parents = 3,
 510                 .ops = &clk_rcg2_ops,
 511         },
 512 };
 513
 514 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
 515         F(24000000, P_XO, 1, 0, 0),
 516         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
 517         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 518         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
 519         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
 520         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 521         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
 522         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
 523         { }
 524 };
 525
 526 static const struct clk_parent_data
 527 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 528         { .fw_name = "xo" },
 529         { .fw_name = "uniphy0_gcc_rx_clk" },
 530         { .fw_name = "uniphy0_gcc_tx_clk" },
 531         { .fw_name = "uniphy1_gcc_rx_clk" },
 532         { .fw_name = "uniphy1_gcc_tx_clk" },
 533         { .hw = &ubi32_pll.clkr.hw },
 534         { .fw_name = "bias_pll_cc_clk" },
 535 };
 536
 537 static const struct parent_map
 538 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 539         { P_XO, 0 },
 540         { P_UNIPHY0_RX, 1 },
 541         { P_UNIPHY0_TX, 2 },
 542         { P_UNIPHY1_RX, 3 },
 543         { P_UNIPHY1_TX, 4 },
 544         { P_UBI32_PLL, 5 },
 545         { P_BIAS_PLL, 6 },
 546 };
 547
 548 static struct clk_rcg2 nss_port5_rx_clk_src = {
 549         .cmd_rcgr = 0x68060,
 550         .freq_tbl = ftbl_nss_port5_rx_clk_src,
 551         .hid_width = 5,
 552         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
 553         .clkr.hw.init = &(struct clk_init_data){
 554                 .name = "nss_port5_rx_clk_src",
 555                 .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
 556                 .num_parents = 7,
 557                 .ops = &clk_rcg2_ops,
 558         },
 559 };
 560
 561 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
 562         F(24000000, P_XO, 1, 0, 0),
 563         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
 564         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 565         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
 566         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
 567         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 568         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
 569         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
 570         { }
 571 };
 572
 573 static const struct clk_parent_data
 574 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 575         { .fw_name = "xo" },
 576         { .fw_name = "uniphy0_gcc_tx_clk" },
 577         { .fw_name = "uniphy0_gcc_rx_clk" },
 578         { .fw_name = "uniphy1_gcc_tx_clk" },
 579         { .fw_name = "uniphy1_gcc_rx_clk" },
 580         { .hw = &ubi32_pll.clkr.hw },
 581         { .fw_name = "bias_pll_cc_clk" },
 582 };
 583
 584 static const struct parent_map
 585 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 586         { P_XO, 0 },
 587         { P_UNIPHY0_TX, 1 },
 588         { P_UNIPHY0_RX, 2 },
 589         { P_UNIPHY1_TX, 3 },
 590         { P_UNIPHY1_RX, 4 },
 591         { P_UBI32_PLL, 5 },
 592         { P_BIAS_PLL, 6 },
 593 };
 594
 595 static struct clk_rcg2 nss_port5_tx_clk_src = {
 596         .cmd_rcgr = 0x68068,
 597         .freq_tbl = ftbl_nss_port5_tx_clk_src,
 598         .hid_width = 5,
 599         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
 600         .clkr.hw.init = &(struct clk_init_data){
 601                 .name = "nss_port5_tx_clk_src",
 602                 .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
 603                 .num_parents = 7,
 604                 .ops = &clk_rcg2_ops,
 605         },
 606 };
 607
 608 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 609         F(24000000, P_XO, 1, 0, 0),
 610         F(200000000, P_GPLL0, 4, 0, 0),
 611         F(240000000, P_GPLL4, 5, 0, 0),
 612         { }
 613 };
 614
 615 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
 616         F(24000000, P_XO, 1, 0, 0),
 617         F(100000000, P_GPLL0, 8, 0, 0),
 618         { }
 619 };
 620
 621 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 622         { .fw_name = "xo" },
 623         { .hw = &gpll0.clkr.hw },
 624         { .hw = &gpll4.clkr.hw },
 625 };
 626
 627 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 628         { P_XO, 0 },
 629         { P_GPLL0, 1 },
 630         { P_GPLL4, 2 },
 631 };
 632
 633 static struct clk_rcg2 pcie0_axi_clk_src = {
 634         .cmd_rcgr = 0x75054,
 635         .freq_tbl = ftbl_pcie_axi_clk_src,
 636         .hid_width = 5,
 637         .parent_map = gcc_xo_gpll0_gpll4_map,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "pcie0_axi_clk_src",
 640                 .parent_data = gcc_xo_gpll0_gpll4,
 641                 .num_parents = 3,
 642                 .ops = &clk_rcg2_ops,
 643         },
 644 };
 645
 646 static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
 647         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 648         F(100000000, P_GPLL0, 8, 0, 0),
 649         F(133330000, P_GPLL0, 6, 0, 0),
 650         F(200000000, P_GPLL0, 4, 0, 0),
 651         { }
 652 };
 653
 654 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 655         { .fw_name = "xo" },
 656         { .hw = &gpll0_out_main_div2.hw },
 657         { .hw = &gpll0.clkr.hw },
 658 };
 659
 660 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 661         { P_XO, 0 },
 662         { P_GPLL0_DIV2, 2 },
 663         { P_GPLL0, 1 },
 664 };
 665
 666 static struct clk_rcg2 usb0_master_clk_src = {
 667         .cmd_rcgr = 0x3e00c,
 668         .freq_tbl = ftbl_usb0_master_clk_src,
 669         .mnd_width = 8,
 670         .hid_width = 5,
 671         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 672         .clkr.hw.init = &(struct clk_init_data){
 673                 .name = "usb0_master_clk_src",
 674                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 675                 .num_parents = 3,
 676                 .ops = &clk_rcg2_ops,
 677         },
 678 };
 679
 680 static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
 681         .reg = 0x46018,
 682         .shift = 4,
 683         .width = 4,
 684         .clkr = {
 685                 .hw.init = &(struct clk_init_data){
 686                         .name = "apss_ahb_postdiv_clk_src",
 687                         .parent_hws = (const struct clk_hw *[]){
 688                                         &apss_ahb_clk_src.clkr.hw },
 689                         .num_parents = 1,
 690                         .ops = &clk_regmap_div_ops,
 691                 },
 692         },
 693 };
 694
 695 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 696         .mult = 1,
 697         .div = 4,
 698         .hw.init = &(struct clk_init_data){
 699                 .name = "gcc_xo_div4_clk_src",
 700                 .parent_hws = (const struct clk_hw *[]){
 701                                 &gcc_xo_clk_src.clkr.hw },
 702                 .num_parents = 1,
 703                 .ops = &clk_fixed_factor_ops,
 704                 .flags = CLK_SET_RATE_PARENT,
 705         },
 706 };
 707
 708 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
 709         F(24000000, P_XO, 1, 0, 0),
 710         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 711         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 712         { }
 713 };
 714
 715 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 716         { .fw_name = "xo" },
 717         { .fw_name = "uniphy0_gcc_rx_clk" },
 718         { .fw_name = "uniphy0_gcc_tx_clk" },
 719         { .hw = &ubi32_pll.clkr.hw },
 720         { .fw_name = "bias_pll_cc_clk" },
 721 };
 722
 723 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 724         { P_XO, 0 },
 725         { P_UNIPHY0_RX, 1 },
 726         { P_UNIPHY0_TX, 2 },
 727         { P_UBI32_PLL, 5 },
 728         { P_BIAS_PLL, 6 },
 729 };
 730
 731 static struct clk_rcg2 nss_port1_rx_clk_src = {
 732         .cmd_rcgr = 0x68020,
 733         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 734         .hid_width = 5,
 735         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 736         .clkr.hw.init = &(struct clk_init_data){
 737                 .name = "nss_port1_rx_clk_src",
 738                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 739                 .num_parents = 5,
 740                 .ops = &clk_rcg2_ops,
 741         },
 742 };
 743
 744 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
 745         F(24000000, P_XO, 1, 0, 0),
 746         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 747         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 748         { }
 749 };
 750
 751 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 752         { .fw_name = "xo" },
 753         { .fw_name = "uniphy0_gcc_tx_clk" },
 754         { .fw_name = "uniphy0_gcc_rx_clk" },
 755         { .hw = &ubi32_pll.clkr.hw },
 756         { .fw_name = "bias_pll_cc_clk" },
 757 };
 758
 759 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 760         { P_XO, 0 },
 761         { P_UNIPHY0_TX, 1 },
 762         { P_UNIPHY0_RX, 2 },
 763         { P_UBI32_PLL, 5 },
 764         { P_BIAS_PLL, 6 },
 765 };
 766
 767 static struct clk_rcg2 nss_port1_tx_clk_src = {
 768         .cmd_rcgr = 0x68028,
 769         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 770         .hid_width = 5,
 771         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 772         .clkr.hw.init = &(struct clk_init_data){
 773                 .name = "nss_port1_tx_clk_src",
 774                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 775                 .num_parents = 5,
 776                 .ops = &clk_rcg2_ops,
 777         },
 778 };
 779
 780 static struct clk_rcg2 nss_port2_rx_clk_src = {
 781         .cmd_rcgr = 0x68030,
 782         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 783         .hid_width = 5,
 784         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 785         .clkr.hw.init = &(struct clk_init_data){
 786                 .name = "nss_port2_rx_clk_src",
 787                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 788                 .num_parents = 5,
 789                 .ops = &clk_rcg2_ops,
 790         },
 791 };
 792
 793 static struct clk_rcg2 nss_port2_tx_clk_src = {
 794         .cmd_rcgr = 0x68038,
 795         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 796         .hid_width = 5,
 797         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 798         .clkr.hw.init = &(struct clk_init_data){
 799                 .name = "nss_port2_tx_clk_src",
 800                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 801                 .num_parents = 5,
 802                 .ops = &clk_rcg2_ops,
 803         },
 804 };
 805
 806 static struct clk_rcg2 nss_port3_rx_clk_src = {
 807         .cmd_rcgr = 0x68040,
 808         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 809         .hid_width = 5,
 810         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 811         .clkr.hw.init = &(struct clk_init_data){
 812                 .name = "nss_port3_rx_clk_src",
 813                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 814                 .num_parents = 5,
 815                 .ops = &clk_rcg2_ops,
 816         },
 817 };
 818
 819 static struct clk_rcg2 nss_port3_tx_clk_src = {
 820         .cmd_rcgr = 0x68048,
 821         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 822         .hid_width = 5,
 823         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 824         .clkr.hw.init = &(struct clk_init_data){
 825                 .name = "nss_port3_tx_clk_src",
 826                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 827                 .num_parents = 5,
 828                 .ops = &clk_rcg2_ops,
 829         },
 830 };
 831
 832 static struct clk_rcg2 nss_port4_rx_clk_src = {
 833         .cmd_rcgr = 0x68050,
 834         .freq_tbl = ftbl_nss_port1_rx_clk_src,
 835         .hid_width = 5,
 836         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 837         .clkr.hw.init = &(struct clk_init_data){
 838                 .name = "nss_port4_rx_clk_src",
 839                 .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 840                 .num_parents = 5,
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static struct clk_rcg2 nss_port4_tx_clk_src = {
 846         .cmd_rcgr = 0x68058,
 847         .freq_tbl = ftbl_nss_port1_tx_clk_src,
 848         .hid_width = 5,
 849         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 850         .clkr.hw.init = &(struct clk_init_data){
 851                 .name = "nss_port4_tx_clk_src",
 852                 .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 853                 .num_parents = 5,
 854                 .ops = &clk_rcg2_ops,
 855         },
 856 };
 857
 858 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 859         .reg = 0x68440,
 860         .shift = 0,
 861         .width = 4,
 862         .clkr = {
 863                 .hw.init = &(struct clk_init_data){
 864                         .name = "nss_port5_rx_div_clk_src",
 865                         .parent_hws = (const struct clk_hw *[]){
 866                                         &nss_port5_rx_clk_src.clkr.hw },
 867                         .num_parents = 1,
 868                         .ops = &clk_regmap_div_ops,
 869                         .flags = CLK_SET_RATE_PARENT,
 870                 },
 871         },
 872 };
 873
 874 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
 875         .reg = 0x68444,
 876         .shift = 0,
 877         .width = 4,
 878         .clkr = {
 879                 .hw.init = &(struct clk_init_data){
 880                         .name = "nss_port5_tx_div_clk_src",
 881                         .parent_hws = (const struct clk_hw *[]){
 882                                         &nss_port5_tx_clk_src.clkr.hw },
 883                         .num_parents = 1,
 884                         .ops = &clk_regmap_div_ops,
 885                         .flags = CLK_SET_RATE_PARENT,
 886                 },
 887         },
 888 };
 889
 890 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 891         F(24000000, P_XO, 1, 0, 0),
 892         F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 893         F(200000000, P_GPLL0, 4, 0, 0),
 894         F(308570000, P_GPLL6, 3.5, 0, 0),
 895         F(400000000, P_GPLL0, 2, 0, 0),
 896         F(533000000, P_GPLL0, 1.5, 0, 0),
 897         { }
 898 };
 899
 900 static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
 901         { .fw_name = "xo" },
 902         { .hw = &gpll0.clkr.hw },
 903         { .hw = &gpll6.clkr.hw },
 904         { .hw = &ubi32_pll.clkr.hw },
 905         { .hw = &gpll0_out_main_div2.hw },
 906 };
 907
 908 static const struct parent_map
 909 gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
 910         { P_XO, 0 },
 911         { P_GPLL0, 1 },
 912         { P_GPLL6, 2 },
 913         { P_UBI32_PLL, 3 },
 914         { P_GPLL0_DIV2, 6 },
 915 };
 916
 917 static struct clk_rcg2 apss_axi_clk_src = {
 918         .cmd_rcgr = 0x38048,
 919         .freq_tbl = ftbl_apss_axi_clk_src,
 920         .hid_width = 5,
 921         .parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "apss_axi_clk_src",
 924                 .parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
 925                 .num_parents = 5,
 926                 .ops = &clk_rcg2_ops,
 927         },
 928 };
 929
 930 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
 931         F(24000000, P_XO, 1, 0, 0),
 932         F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
 933         { }
 934 };
 935
 936 static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
 937         { .fw_name = "xo" },
 938         { .hw = &nss_crypto_pll.clkr.hw },
 939         { .hw = &gpll0.clkr.hw },
 940 };
 941
 942 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 943         { P_XO, 0 },
 944         { P_NSS_CRYPTO_PLL, 1 },
 945         { P_GPLL0, 2 },
 946 };
 947
 948 static struct clk_rcg2 nss_crypto_clk_src = {
 949         .cmd_rcgr = 0x68144,
 950         .freq_tbl = ftbl_nss_crypto_clk_src,
 951         .mnd_width = 16,
 952         .hid_width = 5,
 953         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
 954         .clkr.hw.init = &(struct clk_init_data){
 955                 .name = "nss_crypto_clk_src",
 956                 .parent_data = gcc_xo_nss_crypto_pll_gpll0,
 957                 .num_parents = 3,
 958                 .ops = &clk_rcg2_ops,
 959         },
 960 };
 961
 962 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
 963         .reg = 0x68400,
 964         .shift = 0,
 965         .width = 4,
 966         .clkr = {
 967                 .hw.init = &(struct clk_init_data){
 968                         .name = "nss_port1_rx_div_clk_src",
 969                         .parent_hws = (const struct clk_hw *[]){
 970                                 &nss_port1_rx_clk_src.clkr.hw },
 971                         .num_parents = 1,
 972                         .ops = &clk_regmap_div_ops,
 973                         .flags = CLK_SET_RATE_PARENT,
 974                 },
 975         },
 976 };
 977
 978 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
 979         .reg = 0x68404,
 980         .shift = 0,
 981         .width = 4,
 982         .clkr = {
 983                 .hw.init = &(struct clk_init_data){
 984                         .name = "nss_port1_tx_div_clk_src",
 985                         .parent_hws = (const struct clk_hw *[]){
 986                                         &nss_port1_tx_clk_src.clkr.hw },
 987                         .num_parents = 1,
 988                         .ops = &clk_regmap_div_ops,
 989                         .flags = CLK_SET_RATE_PARENT,
 990                 },
 991         },
 992 };
 993
 994 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
 995         .reg = 0x68410,
 996         .shift = 0,
 997         .width = 4,
 998         .clkr = {
 999                 .hw.init = &(struct clk_init_data){
1000                         .name = "nss_port2_rx_div_clk_src",
1001                         .parent_hws = (const struct clk_hw *[]){
1002                                         &nss_port2_rx_clk_src.clkr.hw },
1003                         .num_parents = 1,
1004                         .ops = &clk_regmap_div_ops,
1005                         .flags = CLK_SET_RATE_PARENT,
1006                 },
1007         },
1008 };
1009
1010 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1011         .reg = 0x68414,
1012         .shift = 0,
1013         .width = 4,
1014         .clkr = {
1015                 .hw.init = &(struct clk_init_data){
1016                         .name = "nss_port2_tx_div_clk_src",
1017                         .parent_hws = (const struct clk_hw *[]){
1018                                         &nss_port2_tx_clk_src.clkr.hw },
1019                         .num_parents = 1,
1020                         .ops = &clk_regmap_div_ops,
1021                         .flags = CLK_SET_RATE_PARENT,
1022                 },
1023         },
1024 };
1025
1026 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1027         .reg = 0x68420,
1028         .shift = 0,
1029         .width = 4,
1030         .clkr = {
1031                 .hw.init = &(struct clk_init_data){
1032                         .name = "nss_port3_rx_div_clk_src",
1033                         .parent_hws = (const struct clk_hw *[]){
1034                                         &nss_port3_rx_clk_src.clkr.hw },
1035                         .num_parents = 1,
1036                         .ops = &clk_regmap_div_ops,
1037                         .flags = CLK_SET_RATE_PARENT,
1038                 },
1039         },
1040 };
1041
1042 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1043         .reg = 0x68424,
1044         .shift = 0,
1045         .width = 4,
1046         .clkr = {
1047                 .hw.init = &(struct clk_init_data){
1048                         .name = "nss_port3_tx_div_clk_src",
1049                         .parent_hws = (const struct clk_hw *[]){
1050                                         &nss_port3_tx_clk_src.clkr.hw },
1051                         .num_parents = 1,
1052                         .ops = &clk_regmap_div_ops,
1053                         .flags = CLK_SET_RATE_PARENT,
1054                 },
1055         },
1056 };
1057
1058 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1059         .reg = 0x68430,
1060         .shift = 0,
1061         .width = 4,
1062         .clkr = {
1063                 .hw.init = &(struct clk_init_data){
1064                         .name = "nss_port4_rx_div_clk_src",
1065                         .parent_hws = (const struct clk_hw *[]){
1066                                         &nss_port4_rx_clk_src.clkr.hw },
1067                         .num_parents = 1,
1068                         .ops = &clk_regmap_div_ops,
1069                         .flags = CLK_SET_RATE_PARENT,
1070                 },
1071         },
1072 };
1073
1074 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1075         .reg = 0x68434,
1076         .shift = 0,
1077         .width = 4,
1078         .clkr = {
1079                 .hw.init = &(struct clk_init_data){
1080                         .name = "nss_port4_tx_div_clk_src",
1081                         .parent_hws = (const struct clk_hw *[]){
1082                                         &nss_port4_tx_clk_src.clkr.hw },
1083                         .num_parents = 1,
1084                         .ops = &clk_regmap_div_ops,
1085                         .flags = CLK_SET_RATE_PARENT,
1086                 },
1087         },
1088 };
1089
1090 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1091         F(24000000, P_XO, 1, 0, 0),
1092         F(149760000, P_UBI32_PLL, 10, 0, 0),
1093         F(187200000, P_UBI32_PLL, 8, 0, 0),
1094         F(249600000, P_UBI32_PLL, 6, 0, 0),
1095         F(374400000, P_UBI32_PLL, 4, 0, 0),
1096         F(748800000, P_UBI32_PLL, 2, 0, 0),
1097         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1098         { }
1099 };
1100
1101 static const struct clk_parent_data
1102                         gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1103         { .fw_name = "xo" },
1104         { .hw = &ubi32_pll.clkr.hw },
1105         { .hw = &gpll0.clkr.hw },
1106         { .hw = &gpll2.clkr.hw },
1107         { .hw = &gpll4.clkr.hw },
1108         { .hw = &gpll6.clkr.hw },
1109 };
1110
1111 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1112         { P_XO, 0 },
1113         { P_UBI32_PLL, 1 },
1114         { P_GPLL0, 2 },
1115         { P_GPLL2, 3 },
1116         { P_GPLL4, 4 },
1117         { P_GPLL6, 5 },
1118 };
1119
1120 static struct clk_rcg2 nss_ubi0_clk_src = {
1121         .cmd_rcgr = 0x68104,
1122         .freq_tbl = ftbl_nss_ubi_clk_src,
1123         .hid_width = 5,
1124         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1125         .clkr.hw.init = &(struct clk_init_data){
1126                 .name = "nss_ubi0_clk_src",
1127                 .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1128                 .num_parents = 6,
1129                 .ops = &clk_rcg2_ops,
1130                 .flags = CLK_SET_RATE_PARENT,
1131         },
1132 };
1133
1134 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
1135         F(24000000, P_XO, 1, 0, 0),
1136         F(100000000, P_GPLL0, 8, 0, 0),
1137         { }
1138 };
1139
1140 static struct clk_rcg2 adss_pwm_clk_src = {
1141         .cmd_rcgr = 0x1c008,
1142         .freq_tbl = ftbl_adss_pwm_clk_src,
1143         .hid_width = 5,
1144         .parent_map = gcc_xo_gpll0_map,
1145         .clkr.hw.init = &(struct clk_init_data){
1146                 .name = "adss_pwm_clk_src",
1147                 .parent_data = gcc_xo_gpll0,
1148                 .num_parents = 2,
1149                 .ops = &clk_rcg2_ops,
1150         },
1151 };
1152
1153 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
1154         F(24000000, P_XO, 1, 0, 0),
1155         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1156         F(50000000, P_GPLL0, 16, 0, 0),
1157         { }
1158 };
1159
1160 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
1161         .cmd_rcgr = 0x0200c,
1162         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1163         .hid_width = 5,
1164         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1165         .clkr.hw.init = &(struct clk_init_data){
1166                 .name = "blsp1_qup1_i2c_apps_clk_src",
1167                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1168                 .num_parents = 3,
1169                 .ops = &clk_rcg2_ops,
1170         },
1171 };
1172
1173 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
1174         F(960000, P_XO, 10, 2, 5),
1175         F(4800000, P_XO, 5, 0, 0),
1176         F(9600000, P_XO, 2, 4, 5),
1177         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
1178         F(16000000, P_GPLL0, 10, 1, 5),
1179         F(24000000, P_XO, 1, 0, 0),
1180         F(25000000, P_GPLL0, 16, 1, 2),
1181         F(50000000, P_GPLL0, 16, 0, 0),
1182         { }
1183 };
1184
1185 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
1186         .cmd_rcgr = 0x02024,
1187         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1188         .mnd_width = 8,
1189         .hid_width = 5,
1190         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1191         .clkr.hw.init = &(struct clk_init_data){
1192                 .name = "blsp1_qup1_spi_apps_clk_src",
1193                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1194                 .num_parents = 3,
1195                 .ops = &clk_rcg2_ops,
1196         },
1197 };
1198
1199 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
1200         .cmd_rcgr = 0x03000,
1201         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1202         .hid_width = 5,
1203         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1204         .clkr.hw.init = &(struct clk_init_data){
1205                 .name = "blsp1_qup2_i2c_apps_clk_src",
1206                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1207                 .num_parents = 3,
1208                 .ops = &clk_rcg2_ops,
1209         },
1210 };
1211
1212 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
1213         .cmd_rcgr = 0x03014,
1214         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1215         .mnd_width = 8,
1216         .hid_width = 5,
1217         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1218         .clkr.hw.init = &(struct clk_init_data){
1219                 .name = "blsp1_qup2_spi_apps_clk_src",
1220                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1221                 .num_parents = 3,
1222                 .ops = &clk_rcg2_ops,
1223         },
1224 };
1225
1226 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
1227         .cmd_rcgr = 0x04000,
1228         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1229         .hid_width = 5,
1230         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1231         .clkr.hw.init = &(struct clk_init_data){
1232                 .name = "blsp1_qup3_i2c_apps_clk_src",
1233                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1234                 .num_parents = 3,
1235                 .ops = &clk_rcg2_ops,
1236         },
1237 };
1238
1239 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
1240         .cmd_rcgr = 0x04014,
1241         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1242         .mnd_width = 8,
1243         .hid_width = 5,
1244         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1245         .clkr.hw.init = &(struct clk_init_data){
1246                 .name = "blsp1_qup3_spi_apps_clk_src",
1247                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1248                 .num_parents = 3,
1249                 .ops = &clk_rcg2_ops,
1250         },
1251 };
1252
1253 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
1254         .cmd_rcgr = 0x05000,
1255         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1256         .hid_width = 5,
1257         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1258         .clkr.hw.init = &(struct clk_init_data){
1259                 .name = "blsp1_qup4_i2c_apps_clk_src",
1260                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1261                 .num_parents = 3,
1262                 .ops = &clk_rcg2_ops,
1263         },
1264 };
1265
1266 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
1267         .cmd_rcgr = 0x05014,
1268         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1269         .mnd_width = 8,
1270         .hid_width = 5,
1271         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1272         .clkr.hw.init = &(struct clk_init_data){
1273                 .name = "blsp1_qup4_spi_apps_clk_src",
1274                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1275                 .num_parents = 3,
1276                 .ops = &clk_rcg2_ops,
1277         },
1278 };
1279
1280 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
1281         .cmd_rcgr = 0x06000,
1282         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1283         .hid_width = 5,
1284         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1285         .clkr.hw.init = &(struct clk_init_data){
1286                 .name = "blsp1_qup5_i2c_apps_clk_src",
1287                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1288                 .num_parents = 3,
1289                 .ops = &clk_rcg2_ops,
1290         },
1291 };
1292
1293 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
1294         .cmd_rcgr = 0x06014,
1295         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1296         .mnd_width = 8,
1297         .hid_width = 5,
1298         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1299         .clkr.hw.init = &(struct clk_init_data){
1300                 .name = "blsp1_qup5_spi_apps_clk_src",
1301                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1302                 .num_parents = 3,
1303                 .ops = &clk_rcg2_ops,
1304         },
1305 };
1306
1307 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
1308         .cmd_rcgr = 0x07000,
1309         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1310         .hid_width = 5,
1311         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1312         .clkr.hw.init = &(struct clk_init_data){
1313                 .name = "blsp1_qup6_i2c_apps_clk_src",
1314                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1315                 .num_parents = 3,
1316                 .ops = &clk_rcg2_ops,
1317         },
1318 };
1319
1320 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
1321         .cmd_rcgr = 0x07014,
1322         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1323         .mnd_width = 8,
1324         .hid_width = 5,
1325         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1326         .clkr.hw.init = &(struct clk_init_data){
1327                 .name = "blsp1_qup6_spi_apps_clk_src",
1328                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1329                 .num_parents = 3,
1330                 .ops = &clk_rcg2_ops,
1331         },
1332 };
1333
1334 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
1335         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
1336         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
1337         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
1338         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
1339         F(24000000, P_XO, 1, 0, 0),
1340         F(24000000, P_GPLL0, 1, 3, 100),
1341         F(25000000, P_GPLL0, 16, 1, 2),
1342         F(32000000, P_GPLL0, 1, 1, 25),
1343         F(40000000, P_GPLL0, 1, 1, 20),
1344         F(46400000, P_GPLL0, 1, 29, 500),
1345         F(48000000, P_GPLL0, 1, 3, 50),
1346         F(51200000, P_GPLL0, 1, 8, 125),
1347         F(56000000, P_GPLL0, 1, 7, 100),
1348         F(58982400, P_GPLL0, 1, 1152, 15625),
1349         F(60000000, P_GPLL0, 1, 3, 40),
1350         F(64000000, P_GPLL0, 12.5, 1, 1),
1351         { }
1352 };
1353
1354 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
1355         .cmd_rcgr = 0x02044,
1356         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1357         .mnd_width = 16,
1358         .hid_width = 5,
1359         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1360         .clkr.hw.init = &(struct clk_init_data){
1361                 .name = "blsp1_uart1_apps_clk_src",
1362                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1363                 .num_parents = 3,
1364                 .ops = &clk_rcg2_ops,
1365         },
1366 };
1367
1368 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1369         .cmd_rcgr = 0x03034,
1370         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1371         .mnd_width = 16,
1372         .hid_width = 5,
1373         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1374         .clkr.hw.init = &(struct clk_init_data){
1375                 .name = "blsp1_uart2_apps_clk_src",
1376                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1377                 .num_parents = 3,
1378                 .ops = &clk_rcg2_ops,
1379         },
1380 };
1381
1382 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
1383         .cmd_rcgr = 0x04034,
1384         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1385         .mnd_width = 16,
1386         .hid_width = 5,
1387         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1388         .clkr.hw.init = &(struct clk_init_data){
1389                 .name = "blsp1_uart3_apps_clk_src",
1390                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1391                 .num_parents = 3,
1392                 .ops = &clk_rcg2_ops,
1393         },
1394 };
1395
1396 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
1397         .cmd_rcgr = 0x05034,
1398         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1399         .mnd_width = 16,
1400         .hid_width = 5,
1401         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1402         .clkr.hw.init = &(struct clk_init_data){
1403                 .name = "blsp1_uart4_apps_clk_src",
1404                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1405                 .num_parents = 3,
1406                 .ops = &clk_rcg2_ops,
1407         },
1408 };
1409
1410 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
1411         .cmd_rcgr = 0x06034,
1412         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1413         .mnd_width = 16,
1414         .hid_width = 5,
1415         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1416         .clkr.hw.init = &(struct clk_init_data){
1417                 .name = "blsp1_uart5_apps_clk_src",
1418                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1419                 .num_parents = 3,
1420                 .ops = &clk_rcg2_ops,
1421         },
1422 };
1423
1424 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
1425         .cmd_rcgr = 0x07034,
1426         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1427         .mnd_width = 16,
1428         .hid_width = 5,
1429         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1430         .clkr.hw.init = &(struct clk_init_data){
1431                 .name = "blsp1_uart6_apps_clk_src",
1432                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1433                 .num_parents = 3,
1434                 .ops = &clk_rcg2_ops,
1435         },
1436 };
1437
1438 static const struct freq_tbl ftbl_crypto_clk_src[] = {
1439         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1440         F(80000000, P_GPLL0, 10, 0, 0),
1441         F(100000000, P_GPLL0, 8, 0, 0),
1442         F(160000000, P_GPLL0, 5, 0, 0),
1443         { }
1444 };
1445
1446 static struct clk_rcg2 crypto_clk_src = {
1447         .cmd_rcgr = 0x16004,
1448         .freq_tbl = ftbl_crypto_clk_src,
1449         .hid_width = 5,
1450         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1451         .clkr.hw.init = &(struct clk_init_data){
1452                 .name = "crypto_clk_src",
1453                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1454                 .num_parents = 3,
1455                 .ops = &clk_rcg2_ops,
1456         },
1457 };
1458
1459 static const struct freq_tbl ftbl_gp_clk_src[] = {
1460         F(24000000, P_XO, 1, 0, 0),
1461         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1462         F(100000000, P_GPLL0, 8, 0, 0),
1463         F(200000000, P_GPLL0, 4, 0, 0),
1464         F(266666666, P_GPLL0, 3, 0, 0),
1465         { }
1466 };
1467
1468 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1469         { .fw_name = "xo" },
1470         { .hw = &gpll0.clkr.hw },
1471         { .hw = &gpll6.clkr.hw },
1472         { .hw = &gpll0_out_main_div2.hw },
1473         { .fw_name = "sleep_clk" },
1474 };
1475
1476 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1477         { P_XO, 0 },
1478         { P_GPLL0, 1 },
1479         { P_GPLL6, 2 },
1480         { P_GPLL0_DIV2, 4 },
1481         { P_SLEEP_CLK, 6 },
1482 };
1483
1484 static struct clk_rcg2 gp1_clk_src = {
1485         .cmd_rcgr = 0x08004,
1486         .freq_tbl = ftbl_gp_clk_src,
1487         .mnd_width = 8,
1488         .hid_width = 5,
1489         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1490         .clkr.hw.init = &(struct clk_init_data){
1491                 .name = "gp1_clk_src",
1492                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1493                 .num_parents = 5,
1494                 .ops = &clk_rcg2_ops,
1495         },
1496 };
1497
1498 static struct clk_rcg2 gp2_clk_src = {
1499         .cmd_rcgr = 0x09004,
1500         .freq_tbl = ftbl_gp_clk_src,
1501         .mnd_width = 8,
1502         .hid_width = 5,
1503         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1504         .clkr.hw.init = &(struct clk_init_data){
1505                 .name = "gp2_clk_src",
1506                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1507                 .num_parents = 5,
1508                 .ops = &clk_rcg2_ops,
1509         },
1510 };
1511
1512 static struct clk_rcg2 gp3_clk_src = {
1513         .cmd_rcgr = 0x0a004,
1514         .freq_tbl = ftbl_gp_clk_src,
1515         .mnd_width = 8,
1516         .hid_width = 5,
1517         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1518         .clkr.hw.init = &(struct clk_init_data){
1519                 .name = "gp3_clk_src",
1520                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1521                 .num_parents = 5,
1522                 .ops = &clk_rcg2_ops,
1523         },
1524 };
1525
1526 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1527         .mult = 1,
1528         .div = 4,
1529         .hw.init = &(struct clk_init_data){
1530                 .name = "nss_ppe_cdiv_clk_src",
1531                 .parent_hws = (const struct clk_hw *[]){
1532                                 &nss_ppe_clk_src.clkr.hw },
1533                 .num_parents = 1,
1534                 .ops = &clk_fixed_factor_ops,
1535                 .flags = CLK_SET_RATE_PARENT,
1536         },
1537 };
1538
1539 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1540         .reg = 0x68118,
1541         .shift = 0,
1542         .width = 4,
1543         .clkr = {
1544                 .hw.init = &(struct clk_init_data){
1545                         .name = "nss_ubi0_div_clk_src",
1546                         .parent_hws = (const struct clk_hw *[]){
1547                                 &nss_ubi0_clk_src.clkr.hw },
1548                         .num_parents = 1,
1549                         .ops = &clk_regmap_div_ro_ops,
1550                         .flags = CLK_SET_RATE_PARENT,
1551                 },
1552         },
1553 };
1554
1555 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1556         F(24000000, P_XO, 1, 0, 0),
1557 };
1558
1559 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
1560         { .fw_name = "xo" },
1561         { .hw = &gpll0.clkr.hw },
1562         { .fw_name = "sleep_clk" },
1563 };
1564
1565 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
1566         { P_XO, 0 },
1567         { P_GPLL0, 2 },
1568         { P_PI_SLEEP, 6 },
1569 };
1570
1571 static struct clk_rcg2 pcie0_aux_clk_src = {
1572         .cmd_rcgr = 0x75024,
1573         .freq_tbl = ftbl_pcie_aux_clk_src,
1574         .mnd_width = 16,
1575         .hid_width = 5,
1576         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1577         .clkr.hw.init = &(struct clk_init_data){
1578                 .name = "pcie0_aux_clk_src",
1579                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1580                 .num_parents = 3,
1581                 .ops = &clk_rcg2_ops,
1582         },
1583 };
1584
1585 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
1586         { .fw_name = "pcie20_phy0_pipe_clk" },
1587         { .fw_name = "xo" },
1588 };
1589
1590 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1591         { P_PCIE20_PHY0_PIPE, 0 },
1592         { P_XO, 2 },
1593 };
1594
1595 static struct clk_regmap_mux pcie0_pipe_clk_src = {
1596         .reg = 0x7501c,
1597         .shift = 8,
1598         .width = 2,
1599         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1600         .clkr = {
1601                 .hw.init = &(struct clk_init_data){
1602                         .name = "pcie0_pipe_clk_src",
1603                         .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1604                         .num_parents = 2,
1605                         .ops = &clk_regmap_mux_closest_ops,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                 },
1608         },
1609 };
1610
1611 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1612         F(144000, P_XO, 16, 12, 125),
1613         F(400000, P_XO, 12, 1, 5),
1614         F(24000000, P_GPLL2, 12, 1, 4),
1615         F(48000000, P_GPLL2, 12, 1, 2),
1616         F(96000000, P_GPLL2, 12, 0, 0),
1617         F(177777778, P_GPLL0, 4.5, 0, 0),
1618         F(192000000, P_GPLL2, 6, 0, 0),
1619         F(384000000, P_GPLL2, 3, 0, 0),
1620         { }
1621 };
1622
1623 static const struct clk_parent_data
1624                         gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1625         { .fw_name = "xo" },
1626         { .hw = &gpll0.clkr.hw },
1627         { .hw = &gpll2.clkr.hw },
1628         { .hw = &gpll0_out_main_div2.hw },
1629 };
1630
1631 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1632         { P_XO, 0 },
1633         { P_GPLL0, 1 },
1634         { P_GPLL2, 2 },
1635         { P_GPLL0_DIV2, 4 },
1636 };
1637
1638 static struct clk_rcg2 sdcc1_apps_clk_src = {
1639         .cmd_rcgr = 0x42004,
1640         .freq_tbl = ftbl_sdcc_apps_clk_src,
1641         .mnd_width = 8,
1642         .hid_width = 5,
1643         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1644         .clkr.hw.init = &(struct clk_init_data){
1645                 .name = "sdcc1_apps_clk_src",
1646                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1647                 .num_parents = 4,
1648                 .ops = &clk_rcg2_floor_ops,
1649         },
1650 };
1651
1652 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1653         F(24000000, P_XO, 1, 0, 0),
1654         { }
1655 };
1656
1657 static struct clk_rcg2 usb0_aux_clk_src = {
1658         .cmd_rcgr = 0x3e05c,
1659         .freq_tbl = ftbl_usb_aux_clk_src,
1660         .mnd_width = 16,
1661         .hid_width = 5,
1662         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1663         .clkr.hw.init = &(struct clk_init_data){
1664                 .name = "usb0_aux_clk_src",
1665                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1666                 .num_parents = 3,
1667                 .ops = &clk_rcg2_ops,
1668         },
1669 };
1670
1671 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1672         F(24000000, P_XO, 1, 0, 0),
1673         F(60000000, P_GPLL6, 6, 1, 3),
1674         { }
1675 };
1676
1677 static const struct clk_parent_data
1678                         gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1679         { .fw_name = "xo" },
1680         { .hw = &gpll6.clkr.hw },
1681         { .hw = &gpll0.clkr.hw },
1682         { .hw = &gpll0_out_main_div2.hw },
1683 };
1684
1685 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1686         { P_XO, 0 },
1687         { P_GPLL6, 1 },
1688         { P_GPLL0, 3 },
1689         { P_GPLL0_DIV2, 4 },
1690 };
1691
1692 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1693         .cmd_rcgr = 0x3e020,
1694         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1695         .mnd_width = 8,
1696         .hid_width = 5,
1697         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1698         .clkr.hw.init = &(struct clk_init_data){
1699                 .name = "usb0_mock_utmi_clk_src",
1700                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1701                 .num_parents = 4,
1702                 .ops = &clk_rcg2_ops,
1703         },
1704 };
1705
1706 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1707         { .fw_name = "usb3phy_0_cc_pipe_clk" },
1708         { .fw_name = "xo" },
1709 };
1710
1711 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1712         { P_USB3PHY_0_PIPE, 0 },
1713         { P_XO, 2 },
1714 };
1715
1716 static struct clk_regmap_mux usb0_pipe_clk_src = {
1717         .reg = 0x3e048,
1718         .shift = 8,
1719         .width = 2,
1720         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1721         .clkr = {
1722                 .hw.init = &(struct clk_init_data){
1723                         .name = "usb0_pipe_clk_src",
1724                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1725                         .num_parents = 2,
1726                         .ops = &clk_regmap_mux_closest_ops,
1727                         .flags = CLK_SET_RATE_PARENT,
1728                 },
1729         },
1730 };
1731
1732 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1733         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1734         F(160000000, P_GPLL0, 5, 0, 0),
1735         F(216000000, P_GPLL6, 5, 0, 0),
1736         F(308570000, P_GPLL6, 3.5, 0, 0),
1737 };
1738
1739 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1740         { .fw_name = "xo"},
1741         { .hw = &gpll0.clkr.hw },
1742         { .hw = &gpll6.clkr.hw },
1743         { .hw = &gpll0_out_main_div2.hw },
1744 };
1745
1746 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1747         { P_XO, 0 },
1748         { P_GPLL0, 1 },
1749         { P_GPLL6, 2 },
1750         { P_GPLL0_DIV2, 4 },
1751 };
1752
1753 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1754         .cmd_rcgr = 0x5d000,
1755         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1756         .mnd_width = 8,
1757         .hid_width = 5,
1758         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1759         .clkr.hw.init = &(struct clk_init_data){
1760                 .name = "sdcc1_ice_core_clk_src",
1761                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1762                 .num_parents = 4,
1763                 .ops = &clk_rcg2_ops,
1764         },
1765 };
1766
1767 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1768         F(24000000, P_XO, 1, 0, 0),
1769         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1770         F(100000000, P_GPLL0, 8, 0, 0),
1771         F(200000000, P_GPLL0, 4, 0, 0),
1772         { }
1773 };
1774
1775 static struct clk_rcg2 qdss_stm_clk_src = {
1776         .cmd_rcgr = 0x2902C,
1777         .freq_tbl = ftbl_qdss_stm_clk_src,
1778         .hid_width = 5,
1779         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1780         .clkr.hw.init = &(struct clk_init_data){
1781                 .name = "qdss_stm_clk_src",
1782                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1783                 .num_parents = 3,
1784                 .ops = &clk_rcg2_ops,
1785         },
1786 };
1787
1788 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1789         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1790         F(160000000, P_GPLL0, 5, 0, 0),
1791         F(300000000, P_GPLL4, 4, 0, 0),
1792         { }
1793 };
1794
1795 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
1796         { .fw_name = "xo" },
1797         { .hw = &gpll4.clkr.hw },
1798         { .hw = &gpll0.clkr.hw },
1799         { .hw = &gpll0_out_main_div2.hw },
1800 };
1801
1802 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
1803         { P_XO, 0 },
1804         { P_GPLL4, 1 },
1805         { P_GPLL0, 2 },
1806         { P_GPLL0_DIV2, 4 },
1807 };
1808
1809 static struct clk_rcg2 qdss_traceclkin_clk_src = {
1810         .cmd_rcgr = 0x29048,
1811         .freq_tbl = ftbl_qdss_traceclkin_clk_src,
1812         .hid_width = 5,
1813         .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
1814         .clkr.hw.init = &(struct clk_init_data){
1815                 .name = "qdss_traceclkin_clk_src",
1816                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
1817                 .num_parents = 4,
1818                 .ops = &clk_rcg2_ops,
1819         },
1820 };
1821
1822 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1823         .cmd_rcgr = 0x3f020,
1824         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1825         .mnd_width = 8,
1826         .hid_width = 5,
1827         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1828         .clkr.hw.init = &(struct clk_init_data){
1829                 .name = "usb1_mock_utmi_clk_src",
1830                 .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1831                 .num_parents = 4,
1832                 .ops = &clk_rcg2_ops,
1833         },
1834 };
1835
1836 static struct clk_branch gcc_adss_pwm_clk = {
1837         .halt_reg = 0x1c020,
1838         .clkr = {
1839                 .enable_reg = 0x1c020,
1840                 .enable_mask = BIT(0),
1841                 .hw.init = &(struct clk_init_data){
1842                         .name = "gcc_adss_pwm_clk",
1843                         .parent_hws = (const struct clk_hw *[]){
1844                                         &adss_pwm_clk_src.clkr.hw },
1845                         .num_parents = 1,
1846                         .flags = CLK_SET_RATE_PARENT,
1847                         .ops = &clk_branch2_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch gcc_apss_ahb_clk = {
1853         .halt_reg = 0x4601c,
1854         .halt_check = BRANCH_HALT_VOTED,
1855         .clkr = {
1856                 .enable_reg = 0x0b004,
1857                 .enable_mask = BIT(14),
1858                 .hw.init = &(struct clk_init_data){
1859                         .name = "gcc_apss_ahb_clk",
1860                         .parent_hws = (const struct clk_hw *[]){
1861                                         &apss_ahb_postdiv_clk_src.clkr.hw },
1862                         .num_parents = 1,
1863                         .flags = CLK_SET_RATE_PARENT,
1864                         .ops = &clk_branch2_ops,
1865                 },
1866         },
1867 };
1868
1869 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1870         F(24000000, P_XO, 1, 0, 0),
1871         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1872         F(100000000, P_GPLL0, 8, 0, 0),
1873         F(133333333, P_GPLL0, 6, 0, 0),
1874         F(160000000, P_GPLL0, 5, 0, 0),
1875         F(200000000, P_GPLL0, 4, 0, 0),
1876         F(266666667, P_GPLL0, 3, 0, 0),
1877         { }
1878 };
1879
1880 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1881         .cmd_rcgr = 0x26004,
1882         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1883         .hid_width = 5,
1884         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1885         .clkr.hw.init = &(struct clk_init_data){
1886                 .name = "system_noc_bfdcd_clk_src",
1887                 .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1888                 .num_parents = 4,
1889                 .ops = &clk_rcg2_ops,
1890         },
1891 };
1892
1893 static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
1894         F(24000000, P_XO, 1, 0, 0),
1895         F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1896         F(533333333, P_GPLL0, 1.5, 0, 0),
1897         { }
1898 };
1899
1900 static const struct clk_parent_data
1901                         gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
1902         { .fw_name = "xo" },
1903         { .hw = &gpll0.clkr.hw },
1904         { .hw = &gpll2.clkr.hw },
1905         { .fw_name = "bias_pll_nss_noc_clk" },
1906 };
1907
1908 static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
1909         { P_XO, 0 },
1910         { P_GPLL0, 1 },
1911         { P_GPLL2, 3 },
1912         { P_BIAS_PLL_NSS_NOC, 4 },
1913 };
1914
1915 static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
1916         .cmd_rcgr = 0x68088,
1917         .freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
1918         .hid_width = 5,
1919         .parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
1920         .clkr.hw.init = &(struct clk_init_data){
1921                 .name = "ubi32_mem_noc_bfdcd_clk_src",
1922                 .parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
1923                 .num_parents = 4,
1924                 .ops = &clk_rcg2_ops,
1925         },
1926 };
1927
1928 static struct clk_branch gcc_apss_axi_clk = {
1929         .halt_reg = 0x46020,
1930         .halt_check = BRANCH_HALT_VOTED,
1931         .clkr = {
1932                 .enable_reg = 0x0b004,
1933                 .enable_mask = BIT(13),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "gcc_apss_axi_clk",
1936                         .parent_hws = (const struct clk_hw *[]){
1937                                         &apss_axi_clk_src.clkr.hw },
1938                         .num_parents = 1,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch gcc_blsp1_ahb_clk = {
1946         .halt_reg = 0x01008,
1947         .halt_check = BRANCH_HALT_VOTED,
1948         .clkr = {
1949                 .enable_reg = 0x0b004,
1950                 .enable_mask = BIT(10),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_blsp1_ahb_clk",
1953                         .parent_hws = (const struct clk_hw *[]){
1954                                         &pcnoc_bfdcd_clk_src.clkr.hw },
1955                         .num_parents = 1,
1956                         .flags = CLK_SET_RATE_PARENT,
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1963         .halt_reg = 0x02008,
1964         .clkr = {
1965                 .enable_reg = 0x02008,
1966                 .enable_mask = BIT(0),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1969                         .parent_hws = (const struct clk_hw *[]){
1970                                         &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1971                         .num_parents = 1,
1972                         .flags = CLK_SET_RATE_PARENT,
1973                         .ops = &clk_branch2_ops,
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1979         .halt_reg = 0x02004,
1980         .clkr = {
1981                 .enable_reg = 0x02004,
1982                 .enable_mask = BIT(0),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1985                         .parent_hws = (const struct clk_hw *[]){
1986                                         &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1987                         .num_parents = 1,
1988                         .flags = CLK_SET_RATE_PARENT,
1989                         .ops = &clk_branch2_ops,
1990                 },
1991         },
1992 };
1993
1994 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1995         .halt_reg = 0x03010,
1996         .clkr = {
1997                 .enable_reg = 0x03010,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2001                         .parent_hws = (const struct clk_hw *[]){
2002                                         &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2003                         .num_parents = 1,
2004                         .flags = CLK_SET_RATE_PARENT,
2005                         .ops = &clk_branch2_ops,
2006                 },
2007         },
2008 };
2009
2010 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2011         .halt_reg = 0x0300c,
2012         .clkr = {
2013                 .enable_reg = 0x0300c,
2014                 .enable_mask = BIT(0),
2015                 .hw.init = &(struct clk_init_data){
2016                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2017                         .parent_hws = (const struct clk_hw *[]){
2018                                         &blsp1_qup2_spi_apps_clk_src.clkr.hw },
2019                         .num_parents = 1,
2020                         .flags = CLK_SET_RATE_PARENT,
2021                         .ops = &clk_branch2_ops,
2022                 },
2023         },
2024 };
2025
2026 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2027         .halt_reg = 0x04010,
2028         .clkr = {
2029                 .enable_reg = 0x04010,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2033                         .parent_hws = (const struct clk_hw *[]){
2034                                         &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2035                         .num_parents = 1,
2036                         .flags = CLK_SET_RATE_PARENT,
2037                         .ops = &clk_branch2_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2043         .halt_reg = 0x0400c,
2044         .clkr = {
2045                 .enable_reg = 0x0400c,
2046                 .enable_mask = BIT(0),
2047                 .hw.init = &(struct clk_init_data){
2048                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2049                         .parent_hws = (const struct clk_hw *[]){
2050                                         &blsp1_qup3_spi_apps_clk_src.clkr.hw },
2051                         .num_parents = 1,
2052                         .flags = CLK_SET_RATE_PARENT,
2053                         .ops = &clk_branch2_ops,
2054                 },
2055         },
2056 };
2057
2058 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2059         .halt_reg = 0x05010,
2060         .clkr = {
2061                 .enable_reg = 0x05010,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(struct clk_init_data){
2064                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2065                         .parent_hws = (const struct clk_hw *[]){
2066                                         &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2067                         .num_parents = 1,
2068                         .flags = CLK_SET_RATE_PARENT,
2069                         .ops = &clk_branch2_ops,
2070                 },
2071         },
2072 };
2073
2074 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2075         .halt_reg = 0x0500c,
2076         .clkr = {
2077                 .enable_reg = 0x0500c,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data){
2080                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2081                         .parent_hws = (const struct clk_hw *[]){
2082                                         &blsp1_qup4_spi_apps_clk_src.clkr.hw },
2083                         .num_parents = 1,
2084                         .flags = CLK_SET_RATE_PARENT,
2085                         .ops = &clk_branch2_ops,
2086                 },
2087         },
2088 };
2089
2090 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2091         .halt_reg = 0x06010,
2092         .clkr = {
2093                 .enable_reg = 0x06010,
2094                 .enable_mask = BIT(0),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2097                         .parent_hws = (const struct clk_hw *[]){
2098                                         &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2099                         .num_parents = 1,
2100                         .flags = CLK_SET_RATE_PARENT,
2101                         .ops = &clk_branch2_ops,
2102                 },
2103         },
2104 };
2105
2106 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2107         .halt_reg = 0x0600c,
2108         .clkr = {
2109                 .enable_reg = 0x0600c,
2110                 .enable_mask = BIT(0),
2111                 .hw.init = &(struct clk_init_data){
2112                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2113                         .parent_hws = (const struct clk_hw *[]){
2114                                         &blsp1_qup5_spi_apps_clk_src.clkr.hw },
2115                         .num_parents = 1,
2116                         .flags = CLK_SET_RATE_PARENT,
2117                         .ops = &clk_branch2_ops,
2118                 },
2119         },
2120 };
2121
2122 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2123         .halt_reg = 0x07010,
2124         .clkr = {
2125                 .enable_reg = 0x07010,
2126                 .enable_mask = BIT(0),
2127                 .hw.init = &(struct clk_init_data){
2128                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2129                         .parent_hws = (const struct clk_hw *[]){
2130                                         &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2131                         .num_parents = 1,
2132                         /*
2133                          * RPM uses QUP6 I2C to communicate with the external
2134                          * PMIC so it must not be disabled.
2135                          */
2136                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2137                         .ops = &clk_branch2_ops,
2138                 },
2139         },
2140 };
2141
2142 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2143         .halt_reg = 0x0700c,
2144         .clkr = {
2145                 .enable_reg = 0x0700c,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2149                         .parent_hws = (const struct clk_hw *[]){
2150                                         &blsp1_qup6_spi_apps_clk_src.clkr.hw },
2151                         .num_parents = 1,
2152                         .flags = CLK_SET_RATE_PARENT,
2153                         .ops = &clk_branch2_ops,
2154                 },
2155         },
2156 };
2157
2158 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2159         .halt_reg = 0x0203c,
2160         .clkr = {
2161                 .enable_reg = 0x0203c,
2162                 .enable_mask = BIT(0),
2163                 .hw.init = &(struct clk_init_data){
2164                         .name = "gcc_blsp1_uart1_apps_clk",
2165                         .parent_hws = (const struct clk_hw *[]){
2166                                         &blsp1_uart1_apps_clk_src.clkr.hw },
2167                         .num_parents = 1,
2168                         .flags = CLK_SET_RATE_PARENT,
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2175         .halt_reg = 0x0302c,
2176         .clkr = {
2177                 .enable_reg = 0x0302c,
2178                 .enable_mask = BIT(0),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "gcc_blsp1_uart2_apps_clk",
2181                         .parent_hws = (const struct clk_hw *[]){
2182                                         &blsp1_uart2_apps_clk_src.clkr.hw },
2183                         .num_parents = 1,
2184                         .flags = CLK_SET_RATE_PARENT,
2185                         .ops = &clk_branch2_ops,
2186                 },
2187         },
2188 };
2189
2190 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2191         .halt_reg = 0x0402c,
2192         .clkr = {
2193                 .enable_reg = 0x0402c,
2194                 .enable_mask = BIT(0),
2195                 .hw.init = &(struct clk_init_data){
2196                         .name = "gcc_blsp1_uart3_apps_clk",
2197                         .parent_hws = (const struct clk_hw *[]){
2198                                         &blsp1_uart3_apps_clk_src.clkr.hw },
2199                         .num_parents = 1,
2200                         .flags = CLK_SET_RATE_PARENT,
2201                         .ops = &clk_branch2_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2207         .halt_reg = 0x0502c,
2208         .clkr = {
2209                 .enable_reg = 0x0502c,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_blsp1_uart4_apps_clk",
2213                         .parent_hws = (const struct clk_hw *[]){
2214                                         &blsp1_uart4_apps_clk_src.clkr.hw },
2215                         .num_parents = 1,
2216                         .flags = CLK_SET_RATE_PARENT,
2217                         .ops = &clk_branch2_ops,
2218                 },
2219         },
2220 };
2221
2222 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2223         .halt_reg = 0x0602c,
2224         .clkr = {
2225                 .enable_reg = 0x0602c,
2226                 .enable_mask = BIT(0),
2227                 .hw.init = &(struct clk_init_data){
2228                         .name = "gcc_blsp1_uart5_apps_clk",
2229                         .parent_hws = (const struct clk_hw *[]){
2230                                         &blsp1_uart5_apps_clk_src.clkr.hw },
2231                         .num_parents = 1,
2232                         .flags = CLK_SET_RATE_PARENT,
2233                         .ops = &clk_branch2_ops,
2234                 },
2235         },
2236 };
2237
2238 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2239         .halt_reg = 0x0702c,
2240         .clkr = {
2241                 .enable_reg = 0x0702c,
2242                 .enable_mask = BIT(0),
2243                 .hw.init = &(struct clk_init_data){
2244                         .name = "gcc_blsp1_uart6_apps_clk",
2245                         .parent_hws = (const struct clk_hw *[]){
2246                                         &blsp1_uart6_apps_clk_src.clkr.hw },
2247                         .num_parents = 1,
2248                         .flags = CLK_SET_RATE_PARENT,
2249                         .ops = &clk_branch2_ops,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch gcc_crypto_ahb_clk = {
2255         .halt_reg = 0x16024,
2256         .halt_check = BRANCH_HALT_VOTED,
2257         .clkr = {
2258                 .enable_reg = 0x0b004,
2259                 .enable_mask = BIT(0),
2260                 .hw.init = &(struct clk_init_data){
2261                         .name = "gcc_crypto_ahb_clk",
2262                         .parent_hws = (const struct clk_hw *[]){
2263                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2264                         .num_parents = 1,
2265                         .flags = CLK_SET_RATE_PARENT,
2266                         .ops = &clk_branch2_ops,
2267                 },
2268         },
2269 };
2270
2271 static struct clk_branch gcc_crypto_axi_clk = {
2272         .halt_reg = 0x16020,
2273         .halt_check = BRANCH_HALT_VOTED,
2274         .clkr = {
2275                 .enable_reg = 0x0b004,
2276                 .enable_mask = BIT(1),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "gcc_crypto_axi_clk",
2279                         .parent_hws = (const struct clk_hw *[]){
2280                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2281                         .num_parents = 1,
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_crypto_clk = {
2289         .halt_reg = 0x1601c,
2290         .halt_check = BRANCH_HALT_VOTED,
2291         .clkr = {
2292                 .enable_reg = 0x0b004,
2293                 .enable_mask = BIT(2),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "gcc_crypto_clk",
2296                         .parent_hws = (const struct clk_hw *[]){
2297                                         &crypto_clk_src.clkr.hw },
2298                         .num_parents = 1,
2299                         .flags = CLK_SET_RATE_PARENT,
2300                         .ops = &clk_branch2_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_fixed_factor gpll6_out_main_div2 = {
2306         .mult = 1,
2307         .div = 2,
2308         .hw.init = &(struct clk_init_data){
2309                 .name = "gpll6_out_main_div2",
2310                 .parent_hws = (const struct clk_hw *[]){
2311                                 &gpll6_main.clkr.hw },
2312                 .num_parents = 1,
2313                 .ops = &clk_fixed_factor_ops,
2314                 .flags = CLK_SET_RATE_PARENT,
2315         },
2316 };
2317
2318 static struct clk_branch gcc_xo_clk = {
2319         .halt_reg = 0x30030,
2320         .clkr = {
2321                 .enable_reg = 0x30030,
2322                 .enable_mask = BIT(0),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "gcc_xo_clk",
2325                         .parent_hws = (const struct clk_hw *[]){
2326                                         &gcc_xo_clk_src.clkr.hw },
2327                         .num_parents = 1,
2328                         .flags = CLK_SET_RATE_PARENT,
2329                         .ops = &clk_branch2_ops,
2330                 },
2331         },
2332 };
2333
2334 static struct clk_branch gcc_gp1_clk = {
2335         .halt_reg = 0x08000,
2336         .clkr = {
2337                 .enable_reg = 0x08000,
2338                 .enable_mask = BIT(0),
2339                 .hw.init = &(struct clk_init_data){
2340                         .name = "gcc_gp1_clk",
2341                         .parent_hws = (const struct clk_hw *[]){
2342                                         &gp1_clk_src.clkr.hw },
2343                         .num_parents = 1,
2344                         .flags = CLK_SET_RATE_PARENT,
2345                         .ops = &clk_branch2_ops,
2346                 },
2347         },
2348 };
2349
2350 static struct clk_branch gcc_gp2_clk = {
2351         .halt_reg = 0x09000,
2352         .clkr = {
2353                 .enable_reg = 0x09000,
2354                 .enable_mask = BIT(0),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gcc_gp2_clk",
2357                         .parent_hws = (const struct clk_hw *[]){
2358                                         &gp2_clk_src.clkr.hw },
2359                         .num_parents = 1,
2360                         .flags = CLK_SET_RATE_PARENT,
2361                         .ops = &clk_branch2_ops,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch gcc_gp3_clk = {
2367         .halt_reg = 0x0a000,
2368         .clkr = {
2369                 .enable_reg = 0x0a000,
2370                 .enable_mask = BIT(0),
2371                 .hw.init = &(struct clk_init_data){
2372                         .name = "gcc_gp3_clk",
2373                         .parent_hws = (const struct clk_hw *[]){
2374                                         &gp3_clk_src.clkr.hw },
2375                         .num_parents = 1,
2376                         .flags = CLK_SET_RATE_PARENT,
2377                         .ops = &clk_branch2_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gcc_mdio_ahb_clk = {
2383         .halt_reg = 0x58004,
2384         .clkr = {
2385                 .enable_reg = 0x58004,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(struct clk_init_data){
2388                         .name = "gcc_mdio_ahb_clk",
2389                         .parent_hws = (const struct clk_hw *[]){
2390                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2391                         .num_parents = 1,
2392                         .flags = CLK_SET_RATE_PARENT,
2393                         .ops = &clk_branch2_ops,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch gcc_crypto_ppe_clk = {
2399         .halt_reg = 0x68310,
2400         .clkr = {
2401                 .enable_reg = 0x68310,
2402                 .enable_mask = BIT(0),
2403                 .hw.init = &(struct clk_init_data){
2404                         .name = "gcc_crypto_ppe_clk",
2405                         .parent_hws = (const struct clk_hw *[]){
2406                                         &nss_ppe_clk_src.clkr.hw },
2407                         .num_parents = 1,
2408                         .flags = CLK_SET_RATE_PARENT,
2409                         .ops = &clk_branch2_ops,
2410                 },
2411         },
2412 };
2413
2414 static struct clk_branch gcc_nss_ce_apb_clk = {
2415         .halt_reg = 0x68174,
2416         .clkr = {
2417                 .enable_reg = 0x68174,
2418                 .enable_mask = BIT(0),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "gcc_nss_ce_apb_clk",
2421                         .parent_hws = (const struct clk_hw *[]){
2422                                         &nss_ce_clk_src.clkr.hw },
2423                         .num_parents = 1,
2424                         .flags = CLK_SET_RATE_PARENT,
2425                         .ops = &clk_branch2_ops,
2426                 },
2427         },
2428 };
2429
2430 static struct clk_branch gcc_nss_ce_axi_clk = {
2431         .halt_reg = 0x68170,
2432         .clkr = {
2433                 .enable_reg = 0x68170,
2434                 .enable_mask = BIT(0),
2435                 .hw.init = &(struct clk_init_data){
2436                         .name = "gcc_nss_ce_axi_clk",
2437                         .parent_hws = (const struct clk_hw *[]){
2438                                         &nss_ce_clk_src.clkr.hw },
2439                         .num_parents = 1,
2440                         .flags = CLK_SET_RATE_PARENT,
2441                         .ops = &clk_branch2_ops,
2442                 },
2443         },
2444 };
2445
2446 static struct clk_branch gcc_nss_cfg_clk = {
2447         .halt_reg = 0x68160,
2448         .clkr = {
2449                 .enable_reg = 0x68160,
2450                 .enable_mask = BIT(0),
2451                 .hw.init = &(struct clk_init_data){
2452                         .name = "gcc_nss_cfg_clk",
2453                         .parent_hws = (const struct clk_hw *[]){
2454                                         &pcnoc_bfdcd_clk_src.clkr.hw },
2455                         .num_parents = 1,
2456                         .flags = CLK_SET_RATE_PARENT,
2457                         .ops = &clk_branch2_ops,
2458                 },
2459         },
2460 };
2461
2462 static struct clk_branch gcc_nss_crypto_clk = {
2463         .halt_reg = 0x68164,
2464         .clkr = {
2465                 .enable_reg = 0x68164,
2466                 .enable_mask = BIT(0),
2467                 .hw.init = &(struct clk_init_data){
2468                         .name = "gcc_nss_crypto_clk",
2469                         .parent_hws = (const struct clk_hw *[]){
2470                                         &nss_crypto_clk_src.clkr.hw },
2471                         .num_parents = 1,
2472                         .flags = CLK_SET_RATE_PARENT,
2473                         .ops = &clk_branch2_ops,
2474                 },
2475         },
2476 };
2477
2478 static struct clk_branch gcc_nss_csr_clk = {
2479         .halt_reg = 0x68318,
2480         .clkr = {
2481                 .enable_reg = 0x68318,
2482                 .enable_mask = BIT(0),
2483                 .hw.init = &(struct clk_init_data){
2484                         .name = "gcc_nss_csr_clk",
2485                         .parent_hws = (const struct clk_hw *[]){
2486                                         &nss_ce_clk_src.clkr.hw },
2487                         .num_parents = 1,
2488                         .flags = CLK_SET_RATE_PARENT,
2489                         .ops = &clk_branch2_ops,
2490                 },
2491         },
2492 };
2493
2494 static struct clk_branch gcc_nss_edma_cfg_clk = {
2495         .halt_reg = 0x6819C,
2496         .clkr = {
2497                 .enable_reg = 0x6819C,
2498                 .enable_mask = BIT(0),
2499                 .hw.init = &(struct clk_init_data){
2500                         .name = "gcc_nss_edma_cfg_clk",
2501                         .parent_hws = (const struct clk_hw *[]){
2502                                         &nss_ppe_clk_src.clkr.hw },
2503                         .num_parents = 1,
2504                         .flags = CLK_SET_RATE_PARENT,
2505                         .ops = &clk_branch2_ops,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch gcc_nss_edma_clk = {
2511         .halt_reg = 0x68198,
2512         .clkr = {
2513                 .enable_reg = 0x68198,
2514                 .enable_mask = BIT(0),
2515                 .hw.init = &(struct clk_init_data){
2516                         .name = "gcc_nss_edma_clk",
2517                         .parent_hws = (const struct clk_hw *[]){
2518                                         &nss_ppe_clk_src.clkr.hw },
2519                         .num_parents = 1,
2520                         .flags = CLK_SET_RATE_PARENT,
2521                         .ops = &clk_branch2_ops,
2522                 },
2523         },
2524 };
2525
2526 static struct clk_branch gcc_nss_noc_clk = {
2527         .halt_reg = 0x68168,
2528         .clkr = {
2529                 .enable_reg = 0x68168,
2530                 .enable_mask = BIT(0),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "gcc_nss_noc_clk",
2533                         .parent_hws = (const struct clk_hw *[]){
2534                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2535                         .num_parents = 1,
2536                         .flags = CLK_SET_RATE_PARENT,
2537                         .ops = &clk_branch2_ops,
2538                 },
2539         },
2540 };
2541
2542 static struct clk_branch gcc_ubi0_utcm_clk = {
2543         .halt_reg = 0x2606c,
2544         .clkr = {
2545                 .enable_reg = 0x2606c,
2546                 .enable_mask = BIT(0),
2547                 .hw.init = &(struct clk_init_data){
2548                         .name = "gcc_ubi0_utcm_clk",
2549                         .parent_hws = (const struct clk_hw *[]){
2550                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2551                         .num_parents = 1,
2552                         .flags = CLK_SET_RATE_PARENT,
2553                         .ops = &clk_branch2_ops,
2554                 },
2555         },
2556 };
2557
2558 static struct clk_branch gcc_snoc_nssnoc_clk = {
2559         .halt_reg = 0x26070,
2560         .clkr = {
2561                 .enable_reg = 0x26070,
2562                 .enable_mask = BIT(0),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "gcc_snoc_nssnoc_clk",
2565                         .parent_hws = (const struct clk_hw *[]){
2566                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2567                         .num_parents = 1,
2568                         .flags = CLK_SET_RATE_PARENT,
2569                         .ops = &clk_branch2_ops,
2570                 },
2571         },
2572 };
2573
2574 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2575         F(24000000, P_XO, 1, 0, 0),
2576         F(133333333, P_GPLL0, 6, 0, 0),
2577         { }
2578 };
2579
2580 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
2581         F(24000000, P_XO, 1, 0, 0),
2582         F(400000000, P_GPLL0, 2, 0, 0),
2583         { }
2584 };
2585
2586 static struct clk_rcg2 wcss_ahb_clk_src = {
2587         .cmd_rcgr = 0x59020,
2588         .freq_tbl = ftbl_wcss_ahb_clk_src,
2589         .hid_width = 5,
2590         .parent_map = gcc_xo_gpll0_map,
2591         .clkr.hw.init = &(struct clk_init_data){
2592                 .name = "wcss_ahb_clk_src",
2593                 .parent_data = gcc_xo_gpll0,
2594                 .num_parents = 2,
2595                 .ops = &clk_rcg2_ops,
2596         },
2597 };
2598
2599 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
2600         { .fw_name = "xo" },
2601         { .hw = &gpll0.clkr.hw },
2602         { .hw = &gpll2.clkr.hw },
2603         { .hw = &gpll4.clkr.hw },
2604         { .hw = &gpll6.clkr.hw },
2605 };
2606
2607 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
2608         { P_XO, 0 },
2609         { P_GPLL0, 1 },
2610         { P_GPLL2, 2 },
2611         { P_GPLL4, 3 },
2612         { P_GPLL6, 4 },
2613 };
2614
2615 static struct clk_rcg2 q6_axi_clk_src = {
2616         .cmd_rcgr = 0x59120,
2617         .freq_tbl = ftbl_q6_axi_clk_src,
2618         .hid_width = 5,
2619         .parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
2620         .clkr.hw.init = &(struct clk_init_data){
2621                 .name = "q6_axi_clk_src",
2622                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
2623                 .num_parents = 5,
2624                 .ops = &clk_rcg2_ops,
2625         },
2626 };
2627
2628 static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
2629         F(24000000, P_XO, 1, 0, 0),
2630         F(100000000, P_GPLL0, 8, 0, 0),
2631         { }
2632 };
2633
2634 static struct clk_rcg2 lpass_core_axim_clk_src = {
2635         .cmd_rcgr = 0x1F020,
2636         .freq_tbl = ftbl_lpass_core_axim_clk_src,
2637         .hid_width = 5,
2638         .parent_map = gcc_xo_gpll0_map,
2639         .clkr.hw.init = &(struct clk_init_data){
2640                 .name = "lpass_core_axim_clk_src",
2641                 .parent_data = gcc_xo_gpll0,
2642                 .num_parents = 2,
2643                 .ops = &clk_rcg2_ops,
2644         },
2645 };
2646
2647 static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
2648         F(24000000, P_XO, 1, 0, 0),
2649         F(266666667, P_GPLL0, 3, 0, 0),
2650         { }
2651 };
2652
2653 static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
2654         .cmd_rcgr = 0x1F040,
2655         .freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
2656         .hid_width = 5,
2657         .parent_map = gcc_xo_gpll0_map,
2658         .clkr.hw.init = &(struct clk_init_data){
2659                 .name = "lpass_snoc_cfg_clk_src",
2660                 .parent_data = gcc_xo_gpll0,
2661                 .num_parents = 2,
2662                 .ops = &clk_rcg2_ops,
2663         },
2664 };
2665
2666 static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
2667         F(24000000, P_XO, 1, 0, 0),
2668         F(400000000, P_GPLL0, 2, 0, 0),
2669         { }
2670 };
2671
2672 static struct clk_rcg2 lpass_q6_axim_clk_src = {
2673         .cmd_rcgr = 0x1F008,
2674         .freq_tbl = ftbl_lpass_q6_axim_clk_src,
2675         .hid_width = 5,
2676         .parent_map = gcc_xo_gpll0_map,
2677         .clkr.hw.init = &(struct clk_init_data){
2678                 .name = "lpass_q6_axim_clk_src",
2679                 .parent_data = gcc_xo_gpll0,
2680                 .num_parents = 2,
2681                 .ops = &clk_rcg2_ops,
2682         },
2683 };
2684
2685 static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
2686         F(24000000, P_XO, 1, 0, 0),
2687         F(50000000, P_GPLL0, 16, 0, 0),
2688         { }
2689 };
2690
2691 static struct clk_rcg2 rbcpr_wcss_clk_src = {
2692         .cmd_rcgr = 0x3a00c,
2693         .freq_tbl = ftbl_rbcpr_wcss_clk_src,
2694         .hid_width = 5,
2695         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
2696         .clkr.hw.init = &(struct clk_init_data){
2697                 .name = "rbcpr_wcss_clk_src",
2698                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
2699                 .num_parents = 3,
2700                 .ops = &clk_rcg2_ops,
2701         },
2702 };
2703
2704 static struct clk_branch gcc_lpass_core_axim_clk = {
2705         .halt_reg = 0x1F028,
2706         .clkr = {
2707                 .enable_reg = 0x1F028,
2708                 .enable_mask = BIT(0),
2709                 .hw.init = &(struct clk_init_data){
2710                         .name = "gcc_lpass_core_axim_clk",
2711                         .parent_hws = (const struct clk_hw *[]){
2712                                         &lpass_core_axim_clk_src.clkr.hw },
2713                         .num_parents = 1,
2714                         .flags = CLK_SET_RATE_PARENT,
2715                         .ops = &clk_branch2_ops,
2716                 },
2717         },
2718 };
2719
2720 static struct clk_branch gcc_lpass_snoc_cfg_clk = {
2721         .halt_reg = 0x1F048,
2722         .clkr = {
2723                 .enable_reg = 0x1F048,
2724                 .enable_mask = BIT(0),
2725                 .hw.init = &(struct clk_init_data){
2726                         .name = "gcc_lpass_snoc_cfg_clk",
2727                         .parent_hws = (const struct clk_hw *[]){
2728                                         &lpass_snoc_cfg_clk_src.clkr.hw },
2729                         .num_parents = 1,
2730                         .flags = CLK_SET_RATE_PARENT,
2731                         .ops = &clk_branch2_ops,
2732                 },
2733         },
2734 };
2735
2736 static struct clk_branch gcc_lpass_q6_axim_clk = {
2737         .halt_reg = 0x1F010,
2738         .clkr = {
2739                 .enable_reg = 0x1F010,
2740                 .enable_mask = BIT(0),
2741                 .hw.init = &(struct clk_init_data){
2742                         .name = "gcc_lpass_q6_axim_clk",
2743                         .parent_hws = (const struct clk_hw *[]){
2744                                         &lpass_q6_axim_clk_src.clkr.hw },
2745                         .num_parents = 1,
2746                         .flags = CLK_SET_RATE_PARENT,
2747                         .ops = &clk_branch2_ops,
2748                 },
2749         },
2750 };
2751
2752 static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
2753         .halt_reg = 0x1F018,
2754         .clkr = {
2755                 .enable_reg = 0x1F018,
2756                 .enable_mask = BIT(0),
2757                 .hw.init = &(struct clk_init_data){
2758                         .name = "gcc_lpass_q6_atbm_at_clk",
2759                         .parent_hws = (const struct clk_hw *[]){
2760                                         &qdss_at_clk_src.clkr.hw },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
2769         .halt_reg = 0x1F01C,
2770         .clkr = {
2771                 .enable_reg = 0x1F01C,
2772                 .enable_mask = BIT(0),
2773                 .hw.init = &(struct clk_init_data){
2774                         .name = "gcc_lpass_q6_pclkdbg_clk",
2775                         .parent_hws = (const struct clk_hw *[]){
2776                                         &qdss_dap_sync_clk_src.hw },
2777                         .num_parents = 1,
2778                         .flags = CLK_SET_RATE_PARENT,
2779                         .ops = &clk_branch2_ops,
2780                 },
2781         },
2782 };
2783
2784 static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
2785         .halt_reg = 0x1F014,
2786         .clkr = {
2787                 .enable_reg = 0x1F014,
2788                 .enable_mask = BIT(0),
2789                 .hw.init = &(struct clk_init_data){
2790                         .name = "gcc_lpass_q6ss_tsctr_1to2_clk",
2791                         .parent_hws = (const struct clk_hw *[]){
2792                                         &qdss_tsctr_div2_clk_src.hw },
2793                         .num_parents = 1,
2794                         .flags = CLK_SET_RATE_PARENT,
2795                         .ops = &clk_branch2_ops,
2796                 },
2797         },
2798 };
2799
2800 static struct clk_branch gcc_lpass_q6ss_trig_clk = {
2801         .halt_reg = 0x1F038,
2802         .clkr = {
2803                 .enable_reg = 0x1F038,
2804                 .enable_mask = BIT(0),
2805                 .hw.init = &(struct clk_init_data){
2806                         .name = "gcc_lpass_q6ss_trig_clk",
2807                         .parent_hws = (const struct clk_hw *[]){
2808                                         &qdss_dap_sync_clk_src.hw },
2809                         .num_parents = 1,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch gcc_lpass_tbu_clk = {
2817         .halt_reg = 0x12094,
2818         .clkr = {
2819                 .enable_reg = 0xb00c,
2820                 .enable_mask = BIT(10),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "gcc_lpass_tbu_clk",
2823                         .parent_hws = (const struct clk_hw *[]){
2824                                         &lpass_q6_axim_clk_src.clkr.hw },
2825                         .num_parents = 1,
2826                         .flags = CLK_SET_RATE_PARENT,
2827                         .ops = &clk_branch2_ops,
2828                 },
2829         },
2830 };
2831
2832 static struct clk_branch gcc_pcnoc_lpass_clk = {
2833         .halt_reg = 0x27020,
2834         .clkr = {
2835                 .enable_reg = 0x27020,
2836                 .enable_mask = BIT(0),
2837                 .hw.init = &(struct clk_init_data){
2838                         .name = "gcc_pcnoc_lpass_clk",
2839                         .parent_hws = (const struct clk_hw *[]){
2840                                         &lpass_core_axim_clk_src.clkr.hw },
2841                         .num_parents = 1,
2842                         .flags = CLK_SET_RATE_PARENT,
2843                         .ops = &clk_branch2_ops,
2844                 },
2845         },
2846 };
2847
2848 static struct clk_branch gcc_mem_noc_lpass_clk = {
2849         .halt_reg = 0x1D044,
2850         .clkr = {
2851                 .enable_reg = 0x1D044,
2852                 .enable_mask = BIT(0),
2853                 .hw.init = &(struct clk_init_data){
2854                         .name = "gcc_mem_noc_lpass_clk",
2855                         .parent_hws = (const struct clk_hw *[]){
2856                                         &lpass_q6_axim_clk_src.clkr.hw },
2857                         .num_parents = 1,
2858                         .flags = CLK_SET_RATE_PARENT,
2859                         .ops = &clk_branch2_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2865         .halt_reg = 0x26074,
2866         .clkr = {
2867                 .enable_reg = 0x26074,
2868                 .enable_mask = BIT(0),
2869                 .hw.init = &(struct clk_init_data){
2870                         .name = "gcc_snoc_lpass_cfg_clk",
2871                         .parent_hws = (const struct clk_hw *[]){
2872                                         &lpass_snoc_cfg_clk_src.clkr.hw },
2873                         .num_parents = 1,
2874                         .flags = CLK_SET_RATE_PARENT,
2875                         .ops = &clk_branch2_ops,
2876                 },
2877         },
2878 };
2879
2880 static struct clk_branch gcc_mem_noc_ubi32_clk = {
2881         .halt_reg = 0x1D03C,
2882         .clkr = {
2883                 .enable_reg = 0x1D03C,
2884                 .enable_mask = BIT(0),
2885                 .hw.init = &(struct clk_init_data){
2886                         .name = "gcc_mem_noc_ubi32_clk",
2887                         .parent_hws = (const struct clk_hw *[]){
2888                                         &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
2889                         .num_parents = 1,
2890                         .flags = CLK_SET_RATE_PARENT,
2891                         .ops = &clk_branch2_ops,
2892                 },
2893         },
2894 };
2895
2896 static struct clk_branch gcc_nss_port1_rx_clk = {
2897         .halt_reg = 0x68240,
2898         .clkr = {
2899                 .enable_reg = 0x68240,
2900                 .enable_mask = BIT(0),
2901                 .hw.init = &(struct clk_init_data){
2902                         .name = "gcc_nss_port1_rx_clk",
2903                         .parent_hws = (const struct clk_hw *[]){
2904                                         &nss_port1_rx_div_clk_src.clkr.hw },
2905                         .num_parents = 1,
2906                         .flags = CLK_SET_RATE_PARENT,
2907                         .ops = &clk_branch2_ops,
2908                 },
2909         },
2910 };
2911
2912 static struct clk_branch gcc_nss_port1_tx_clk = {
2913         .halt_reg = 0x68244,
2914         .clkr = {
2915                 .enable_reg = 0x68244,
2916                 .enable_mask = BIT(0),
2917                 .hw.init = &(struct clk_init_data){
2918                         .name = "gcc_nss_port1_tx_clk",
2919                         .parent_hws = (const struct clk_hw *[]){
2920                                         &nss_port1_tx_div_clk_src.clkr.hw },
2921                         .num_parents = 1,
2922                         .flags = CLK_SET_RATE_PARENT,
2923                         .ops = &clk_branch2_ops,
2924                 },
2925         },
2926 };
2927
2928 static struct clk_branch gcc_nss_port2_rx_clk = {
2929         .halt_reg = 0x68248,
2930         .clkr = {
2931                 .enable_reg = 0x68248,
2932                 .enable_mask = BIT(0),
2933                 .hw.init = &(struct clk_init_data){
2934                         .name = "gcc_nss_port2_rx_clk",
2935                         .parent_hws = (const struct clk_hw *[]){
2936                                         &nss_port2_rx_div_clk_src.clkr.hw },
2937                         .num_parents = 1,
2938                         .flags = CLK_SET_RATE_PARENT,
2939                         .ops = &clk_branch2_ops,
2940                 },
2941         },
2942 };
2943
2944 static struct clk_branch gcc_nss_port2_tx_clk = {
2945         .halt_reg = 0x6824c,
2946         .clkr = {
2947                 .enable_reg = 0x6824c,
2948                 .enable_mask = BIT(0),
2949                 .hw.init = &(struct clk_init_data){
2950                         .name = "gcc_nss_port2_tx_clk",
2951                         .parent_hws = (const struct clk_hw *[]){
2952                                         &nss_port2_tx_div_clk_src.clkr.hw },
2953                         .num_parents = 1,
2954                         .flags = CLK_SET_RATE_PARENT,
2955                         .ops = &clk_branch2_ops,
2956                 },
2957         },
2958 };
2959
2960 static struct clk_branch gcc_nss_port3_rx_clk = {
2961         .halt_reg = 0x68250,
2962         .clkr = {
2963                 .enable_reg = 0x68250,
2964                 .enable_mask = BIT(0),
2965                 .hw.init = &(struct clk_init_data){
2966                         .name = "gcc_nss_port3_rx_clk",
2967                         .parent_hws = (const struct clk_hw *[]){
2968                                         &nss_port3_rx_div_clk_src.clkr.hw },
2969                         .num_parents = 1,
2970                         .flags = CLK_SET_RATE_PARENT,
2971                         .ops = &clk_branch2_ops,
2972                 },
2973         },
2974 };
2975
2976 static struct clk_branch gcc_nss_port3_tx_clk = {
2977         .halt_reg = 0x68254,
2978         .clkr = {
2979                 .enable_reg = 0x68254,
2980                 .enable_mask = BIT(0),
2981                 .hw.init = &(struct clk_init_data){
2982                         .name = "gcc_nss_port3_tx_clk",
2983                         .parent_hws = (const struct clk_hw *[]){
2984                                         &nss_port3_tx_div_clk_src.clkr.hw },
2985                         .num_parents = 1,
2986                         .flags = CLK_SET_RATE_PARENT,
2987                         .ops = &clk_branch2_ops,
2988                 },
2989         },
2990 };
2991
2992 static struct clk_branch gcc_nss_port4_rx_clk = {
2993         .halt_reg = 0x68258,
2994         .clkr = {
2995                 .enable_reg = 0x68258,
2996                 .enable_mask = BIT(0),
2997                 .hw.init = &(struct clk_init_data){
2998                         .name = "gcc_nss_port4_rx_clk",
2999                         .parent_hws = (const struct clk_hw *[]){
3000                                         &nss_port4_rx_div_clk_src.clkr.hw },
3001                         .num_parents = 1,
3002                         .flags = CLK_SET_RATE_PARENT,
3003                         .ops = &clk_branch2_ops,
3004                 },
3005         },
3006 };
3007
3008 static struct clk_branch gcc_nss_port4_tx_clk = {
3009         .halt_reg = 0x6825c,
3010         .clkr = {
3011                 .enable_reg = 0x6825c,
3012                 .enable_mask = BIT(0),
3013                 .hw.init = &(struct clk_init_data){
3014                         .name = "gcc_nss_port4_tx_clk",
3015                         .parent_hws = (const struct clk_hw *[]){
3016                                         &nss_port4_tx_div_clk_src.clkr.hw },
3017                         .num_parents = 1,
3018                         .flags = CLK_SET_RATE_PARENT,
3019                         .ops = &clk_branch2_ops,
3020                 },
3021         },
3022 };
3023
3024 static struct clk_branch gcc_nss_port5_rx_clk = {
3025         .halt_reg = 0x68260,
3026         .clkr = {
3027                 .enable_reg = 0x68260,
3028                 .enable_mask = BIT(0),
3029                 .hw.init = &(struct clk_init_data){
3030                         .name = "gcc_nss_port5_rx_clk",
3031                         .parent_hws = (const struct clk_hw *[]){
3032                                         &nss_port5_rx_div_clk_src.clkr.hw },
3033                         .num_parents = 1,
3034                         .flags = CLK_SET_RATE_PARENT,
3035                         .ops = &clk_branch2_ops,
3036                 },
3037         },
3038 };
3039
3040 static struct clk_branch gcc_nss_port5_tx_clk = {
3041         .halt_reg = 0x68264,
3042         .clkr = {
3043                 .enable_reg = 0x68264,
3044                 .enable_mask = BIT(0),
3045                 .hw.init = &(struct clk_init_data){
3046                         .name = "gcc_nss_port5_tx_clk",
3047                         .parent_hws = (const struct clk_hw *[]){
3048                                         &nss_port5_tx_div_clk_src.clkr.hw },
3049                         .num_parents = 1,
3050                         .flags = CLK_SET_RATE_PARENT,
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3057         .halt_reg = 0x68194,
3058         .clkr = {
3059                 .enable_reg = 0x68194,
3060                 .enable_mask = BIT(0),
3061                 .hw.init = &(struct clk_init_data){
3062                         .name = "gcc_nss_ppe_cfg_clk",
3063                         .parent_hws = (const struct clk_hw *[]){
3064                                         &nss_ppe_clk_src.clkr.hw },
3065                         .num_parents = 1,
3066                         .flags = CLK_SET_RATE_PARENT,
3067                         .ops = &clk_branch2_ops,
3068                 },
3069         },
3070 };
3071
3072 static struct clk_branch gcc_nss_ppe_clk = {
3073         .halt_reg = 0x68190,
3074         .clkr = {
3075                 .enable_reg = 0x68190,
3076                 .enable_mask = BIT(0),
3077                 .hw.init = &(struct clk_init_data){
3078                         .name = "gcc_nss_ppe_clk",
3079                         .parent_hws = (const struct clk_hw *[]){
3080                                         &nss_ppe_clk_src.clkr.hw },
3081                         .num_parents = 1,
3082                         .flags = CLK_SET_RATE_PARENT,
3083                         .ops = &clk_branch2_ops,
3084                 },
3085         },
3086 };
3087
3088 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3089         .halt_reg = 0x68338,
3090         .clkr = {
3091                 .enable_reg = 0x68338,
3092                 .enable_mask = BIT(0),
3093                 .hw.init = &(struct clk_init_data){
3094                         .name = "gcc_nss_ppe_ipe_clk",
3095                         .parent_hws = (const struct clk_hw *[]){
3096                                         &nss_ppe_clk_src.clkr.hw },
3097                         .num_parents = 1,
3098                         .flags = CLK_SET_RATE_PARENT,
3099                         .ops = &clk_branch2_ops,
3100                 },
3101         },
3102 };
3103
3104 static struct clk_branch gcc_nss_ptp_ref_clk = {
3105         .halt_reg = 0x6816C,
3106         .clkr = {
3107                 .enable_reg = 0x6816C,
3108                 .enable_mask = BIT(0),
3109                 .hw.init = &(struct clk_init_data){
3110                         .name = "gcc_nss_ptp_ref_clk",
3111                         .parent_hws = (const struct clk_hw *[]){
3112                                         &nss_ppe_cdiv_clk_src.hw },
3113                         .num_parents = 1,
3114                         .flags = CLK_SET_RATE_PARENT,
3115                         .ops = &clk_branch2_ops,
3116                 },
3117         },
3118 };
3119
3120 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3121         .halt_reg = 0x6830C,
3122         .clkr = {
3123                 .enable_reg = 0x6830C,
3124                 .enable_mask = BIT(0),
3125                 .hw.init = &(struct clk_init_data){
3126                         .name = "gcc_nssnoc_ce_apb_clk",
3127                         .parent_hws = (const struct clk_hw *[]){
3128                                         &nss_ce_clk_src.clkr.hw },
3129                         .num_parents = 1,
3130                         .flags = CLK_SET_RATE_PARENT,
3131                         .ops = &clk_branch2_ops,
3132                 },
3133         },
3134 };
3135
3136 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3137         .halt_reg = 0x68308,
3138         .clkr = {
3139                 .enable_reg = 0x68308,
3140                 .enable_mask = BIT(0),
3141                 .hw.init = &(struct clk_init_data){
3142                         .name = "gcc_nssnoc_ce_axi_clk",
3143                         .parent_hws = (const struct clk_hw *[]){
3144                                         &nss_ce_clk_src.clkr.hw },
3145                         .num_parents = 1,
3146                         .flags = CLK_SET_RATE_PARENT,
3147                         .ops = &clk_branch2_ops,
3148                 },
3149         },
3150 };
3151
3152 static struct clk_branch gcc_nssnoc_crypto_clk = {
3153         .halt_reg = 0x68314,
3154         .clkr = {
3155                 .enable_reg = 0x68314,
3156                 .enable_mask = BIT(0),
3157                 .hw.init = &(struct clk_init_data){
3158                         .name = "gcc_nssnoc_crypto_clk",
3159                         .parent_hws = (const struct clk_hw *[]){
3160                                         &nss_crypto_clk_src.clkr.hw },
3161                         .num_parents = 1,
3162                         .flags = CLK_SET_RATE_PARENT,
3163                         .ops = &clk_branch2_ops,
3164                 },
3165         },
3166 };
3167
3168 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3169         .halt_reg = 0x68304,
3170         .clkr = {
3171                 .enable_reg = 0x68304,
3172                 .enable_mask = BIT(0),
3173                 .hw.init = &(struct clk_init_data){
3174                         .name = "gcc_nssnoc_ppe_cfg_clk",
3175                         .parent_hws = (const struct clk_hw *[]){
3176                                         &nss_ppe_clk_src.clkr.hw },
3177                         .flags = CLK_SET_RATE_PARENT,
3178                         .ops = &clk_branch2_ops,
3179                 },
3180         },
3181 };
3182
3183 static struct clk_branch gcc_nssnoc_ppe_clk = {
3184         .halt_reg = 0x68300,
3185         .clkr = {
3186                 .enable_reg = 0x68300,
3187                 .enable_mask = BIT(0),
3188                 .hw.init = &(struct clk_init_data){
3189                         .name = "gcc_nssnoc_ppe_clk",
3190                         .parent_hws = (const struct clk_hw *[]){
3191                                         &nss_ppe_clk_src.clkr.hw },
3192                         .num_parents = 1,
3193                         .flags = CLK_SET_RATE_PARENT,
3194                         .ops = &clk_branch2_ops,
3195                 },
3196         },
3197 };
3198
3199 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3200         .halt_reg = 0x68180,
3201         .clkr = {
3202                 .enable_reg = 0x68180,
3203                 .enable_mask = BIT(0),
3204                 .hw.init = &(struct clk_init_data){
3205                         .name = "gcc_nssnoc_qosgen_ref_clk",
3206                         .parent_hws = (const struct clk_hw *[]){
3207                                         &gcc_xo_clk_src.clkr.hw },
3208                         .num_parents = 1,
3209                         .flags = CLK_SET_RATE_PARENT,
3210                         .ops = &clk_branch2_ops,
3211                 },
3212         },
3213 };
3214
3215 static struct clk_branch gcc_nssnoc_snoc_clk = {
3216         .halt_reg = 0x68188,
3217         .clkr = {
3218                 .enable_reg = 0x68188,
3219                 .enable_mask = BIT(0),
3220                 .hw.init = &(struct clk_init_data){
3221                         .name = "gcc_nssnoc_snoc_clk",
3222                         .parent_hws = (const struct clk_hw *[]){
3223                                         &system_noc_bfdcd_clk_src.clkr.hw },
3224                         .num_parents = 1,
3225                         .flags = CLK_SET_RATE_PARENT,
3226                         .ops = &clk_branch2_ops,
3227                 },
3228         },
3229 };
3230
3231 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3232         .halt_reg = 0x68184,
3233         .clkr = {
3234                 .enable_reg = 0x68184,
3235                 .enable_mask = BIT(0),
3236                 .hw.init = &(struct clk_init_data){
3237                         .name = "gcc_nssnoc_timeout_ref_clk",
3238                         .parent_hws = (const struct clk_hw *[]){
3239                                         &gcc_xo_div4_clk_src.hw },
3240                         .num_parents = 1,
3241                         .flags = CLK_SET_RATE_PARENT,
3242                         .ops = &clk_branch2_ops,
3243                 },
3244         },
3245 };
3246
3247 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3248         .halt_reg = 0x68270,
3249         .clkr = {
3250                 .enable_reg = 0x68270,
3251                 .enable_mask = BIT(0),
3252                 .hw.init = &(struct clk_init_data){
3253                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3254                         .parent_hws = (const struct clk_hw *[]){
3255                                         &nss_ce_clk_src.clkr.hw },
3256                         .num_parents = 1,
3257                         .flags = CLK_SET_RATE_PARENT,
3258                         .ops = &clk_branch2_ops,
3259                 },
3260         },
3261 };
3262
3263 static struct clk_branch gcc_port1_mac_clk = {
3264         .halt_reg = 0x68320,
3265         .clkr = {
3266                 .enable_reg = 0x68320,
3267                 .enable_mask = BIT(0),
3268                 .hw.init = &(struct clk_init_data){
3269                         .name = "gcc_port1_mac_clk",
3270                         .parent_hws = (const struct clk_hw *[]){
3271                                         &nss_ppe_clk_src.clkr.hw },
3272                         .num_parents = 1,
3273                         .flags = CLK_SET_RATE_PARENT,
3274                         .ops = &clk_branch2_ops,
3275                 },
3276         },
3277 };
3278
3279 static struct clk_branch gcc_port2_mac_clk = {
3280         .halt_reg = 0x68324,
3281         .clkr = {
3282                 .enable_reg = 0x68324,
3283                 .enable_mask = BIT(0),
3284                 .hw.init = &(struct clk_init_data){
3285                         .name = "gcc_port2_mac_clk",
3286                         .parent_hws = (const struct clk_hw *[]){
3287                                         &nss_ppe_clk_src.clkr.hw },
3288                         .num_parents = 1,
3289                         .flags = CLK_SET_RATE_PARENT,
3290                         .ops = &clk_branch2_ops,
3291                 },
3292         },
3293 };
3294
3295 static struct clk_branch gcc_port3_mac_clk = {
3296         .halt_reg = 0x68328,
3297         .clkr = {
3298                 .enable_reg = 0x68328,
3299                 .enable_mask = BIT(0),
3300                 .hw.init = &(struct clk_init_data){
3301                         .name = "gcc_port3_mac_clk",
3302                         .parent_hws = (const struct clk_hw *[]){
3303                                         &nss_ppe_clk_src.clkr.hw },
3304                         .num_parents = 1,
3305                         .flags = CLK_SET_RATE_PARENT,
3306                         .ops = &clk_branch2_ops,
3307                 },
3308         },
3309 };
3310
3311 static struct clk_branch gcc_port4_mac_clk = {
3312         .halt_reg = 0x6832c,
3313         .clkr = {
3314                 .enable_reg = 0x6832c,
3315                 .enable_mask = BIT(0),
3316                 .hw.init = &(struct clk_init_data){
3317                         .name = "gcc_port4_mac_clk",
3318                         .parent_hws = (const struct clk_hw *[]){
3319                                         &nss_ppe_clk_src.clkr.hw },
3320                         .num_parents = 1,
3321                         .flags = CLK_SET_RATE_PARENT,
3322                         .ops = &clk_branch2_ops,
3323                 },
3324         },
3325 };
3326
3327 static struct clk_branch gcc_port5_mac_clk = {
3328         .halt_reg = 0x68330,
3329         .clkr = {
3330                 .enable_reg = 0x68330,
3331                 .enable_mask = BIT(0),
3332                 .hw.init = &(struct clk_init_data){
3333                         .name = "gcc_port5_mac_clk",
3334                         .parent_hws = (const struct clk_hw *[]){
3335                                         &nss_ppe_clk_src.clkr.hw },
3336                         .num_parents = 1,
3337                         .flags = CLK_SET_RATE_PARENT,
3338                         .ops = &clk_branch2_ops,
3339                 },
3340         },
3341 };
3342
3343 static struct clk_branch gcc_ubi0_ahb_clk = {
3344         .halt_reg = 0x6820C,
3345         .halt_check = BRANCH_HALT_DELAY,
3346         .clkr = {
3347                 .enable_reg = 0x6820C,
3348                 .enable_mask = BIT(0),
3349                 .hw.init = &(struct clk_init_data){
3350                         .name = "gcc_ubi0_ahb_clk",
3351                         .parent_hws = (const struct clk_hw *[]){
3352                                         &nss_ce_clk_src.clkr.hw },
3353                         .num_parents = 1,
3354                         .flags = CLK_SET_RATE_PARENT,
3355                         .ops = &clk_branch2_ops,
3356                 },
3357         },
3358 };
3359
3360 static struct clk_branch gcc_ubi0_axi_clk = {
3361         .halt_reg = 0x68200,
3362         .halt_check = BRANCH_HALT_DELAY,
3363         .clkr = {
3364                 .enable_reg = 0x68200,
3365                 .enable_mask = BIT(0),
3366                 .hw.init = &(struct clk_init_data){
3367                         .name = "gcc_ubi0_axi_clk",
3368                         .parent_hws = (const struct clk_hw *[]){
3369                                         &ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
3370                         .num_parents = 1,
3371                         .flags = CLK_SET_RATE_PARENT,
3372                         .ops = &clk_branch2_ops,
3373                 },
3374         },
3375 };
3376
3377 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3378         .halt_reg = 0x68204,
3379         .halt_check = BRANCH_HALT_DELAY,
3380         .clkr = {
3381                 .enable_reg = 0x68204,
3382                 .enable_mask = BIT(0),
3383                 .hw.init = &(struct clk_init_data){
3384                         .name = "gcc_ubi0_nc_axi_clk",
3385                         .parent_hws = (const struct clk_hw *[]){
3386                                         &snoc_nssnoc_bfdcd_clk_src.clkr.hw },
3387                         .num_parents = 1,
3388                         .flags = CLK_SET_RATE_PARENT,
3389                         .ops = &clk_branch2_ops,
3390                 },
3391         },
3392 };
3393
3394 static struct clk_branch gcc_ubi0_core_clk = {
3395         .halt_reg = 0x68210,
3396         .halt_check = BRANCH_HALT_DELAY,
3397         .clkr = {
3398                 .enable_reg = 0x68210,
3399                 .enable_mask = BIT(0),
3400                 .hw.init = &(struct clk_init_data){
3401                         .name = "gcc_ubi0_core_clk",
3402                         .parent_hws = (const struct clk_hw *[]){
3403                                         &nss_ubi0_div_clk_src.clkr.hw },
3404                         .num_parents = 1,
3405                         .flags = CLK_SET_RATE_PARENT,
3406                         .ops = &clk_branch2_ops,
3407                 },
3408         },
3409 };
3410
3411 static struct clk_branch gcc_pcie0_ahb_clk = {
3412         .halt_reg = 0x75010,
3413         .clkr = {
3414                 .enable_reg = 0x75010,
3415                 .enable_mask = BIT(0),
3416                 .hw.init = &(struct clk_init_data){
3417                         .name = "gcc_pcie0_ahb_clk",
3418                         .parent_hws = (const struct clk_hw *[]){
3419                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3420                         .num_parents = 1,
3421                         .flags = CLK_SET_RATE_PARENT,
3422                         .ops = &clk_branch2_ops,
3423                 },
3424         },
3425 };
3426
3427 static struct clk_branch gcc_pcie0_aux_clk = {
3428         .halt_reg = 0x75014,
3429         .clkr = {
3430                 .enable_reg = 0x75014,
3431                 .enable_mask = BIT(0),
3432                 .hw.init = &(struct clk_init_data){
3433                         .name = "gcc_pcie0_aux_clk",
3434                         .parent_hws = (const struct clk_hw *[]){
3435                                         &pcie0_aux_clk_src.clkr.hw },
3436                         .num_parents = 1,
3437                         .flags = CLK_SET_RATE_PARENT,
3438                         .ops = &clk_branch2_ops,
3439                 },
3440         },
3441 };
3442
3443 static struct clk_branch gcc_pcie0_axi_m_clk = {
3444         .halt_reg = 0x75008,
3445         .clkr = {
3446                 .enable_reg = 0x75008,
3447                 .enable_mask = BIT(0),
3448                 .hw.init = &(struct clk_init_data){
3449                         .name = "gcc_pcie0_axi_m_clk",
3450                         .parent_hws = (const struct clk_hw *[]){
3451                                         &pcie0_axi_clk_src.clkr.hw },
3452                         .num_parents = 1,
3453                         .flags = CLK_SET_RATE_PARENT,
3454                         .ops = &clk_branch2_ops,
3455                 },
3456         },
3457 };
3458
3459 static struct clk_branch gcc_pcie0_axi_s_clk = {
3460         .halt_reg = 0x7500c,
3461         .clkr = {
3462                 .enable_reg = 0x7500c,
3463                 .enable_mask = BIT(0),
3464                 .hw.init = &(struct clk_init_data){
3465                         .name = "gcc_pcie0_axi_s_clk",
3466                         .parent_hws = (const struct clk_hw *[]){
3467                                         &pcie0_axi_clk_src.clkr.hw },
3468                         .num_parents = 1,
3469                         .flags = CLK_SET_RATE_PARENT,
3470                         .ops = &clk_branch2_ops,
3471                 },
3472         },
3473 };
3474
3475 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
3476         .halt_reg = 0x26048,
3477         .clkr = {
3478                 .enable_reg = 0x26048,
3479                 .enable_mask = BIT(0),
3480                 .hw.init = &(struct clk_init_data){
3481                         .name = "gcc_sys_noc_pcie0_axi_clk",
3482                         .parent_hws = (const struct clk_hw *[]){
3483                                         &pcie0_axi_clk_src.clkr.hw },
3484                         .num_parents = 1,
3485                         .flags = CLK_SET_RATE_PARENT,
3486                         .ops = &clk_branch2_ops,
3487                 },
3488         },
3489 };
3490
3491 static struct clk_branch gcc_pcie0_pipe_clk = {
3492         .halt_reg = 0x75018,
3493         .halt_check = BRANCH_HALT_DELAY,
3494         .clkr = {
3495                 .enable_reg = 0x75018,
3496                 .enable_mask = BIT(0),
3497                 .hw.init = &(struct clk_init_data){
3498                         .name = "gcc_pcie0_pipe_clk",
3499                         .parent_hws = (const struct clk_hw *[]){
3500                                         &pcie0_pipe_clk_src.clkr.hw },
3501                         .num_parents = 1,
3502                         .flags = CLK_SET_RATE_PARENT,
3503                         .ops = &clk_branch2_ops,
3504                 },
3505         },
3506 };
3507
3508 static struct clk_branch gcc_prng_ahb_clk = {
3509         .halt_reg = 0x13004,
3510         .halt_check = BRANCH_HALT_VOTED,
3511         .clkr = {
3512                 .enable_reg = 0x0b004,
3513                 .enable_mask = BIT(8),
3514                 .hw.init = &(struct clk_init_data){
3515                         .name = "gcc_prng_ahb_clk",
3516                         .parent_hws = (const struct clk_hw *[]){
3517                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3518                         .num_parents = 1,
3519                         .flags = CLK_SET_RATE_PARENT,
3520                         .ops = &clk_branch2_ops,
3521                 },
3522         },
3523 };
3524
3525 static struct clk_branch gcc_qdss_dap_clk = {
3526         .halt_reg = 0x29084,
3527         .clkr = {
3528                 .enable_reg = 0x29084,
3529                 .enable_mask = BIT(0),
3530                 .hw.init = &(struct clk_init_data){
3531                         .name = "gcc_qdss_dap_clk",
3532                         .parent_hws = (const struct clk_hw *[]){
3533                                         &qdss_dap_sync_clk_src.hw },
3534                         .num_parents = 1,
3535                         .flags = CLK_SET_RATE_PARENT,
3536                         .ops = &clk_branch2_ops,
3537                 },
3538         },
3539 };
3540
3541 static struct clk_branch gcc_qpic_ahb_clk = {
3542         .halt_reg = 0x57024,
3543         .clkr = {
3544                 .enable_reg = 0x57024,
3545                 .enable_mask = BIT(0),
3546                 .hw.init = &(struct clk_init_data){
3547                         .name = "gcc_qpic_ahb_clk",
3548                         .parent_hws = (const struct clk_hw *[]){
3549                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3550                         .num_parents = 1,
3551                         .flags = CLK_SET_RATE_PARENT,
3552                         .ops = &clk_branch2_ops,
3553                 },
3554         },
3555 };
3556
3557 static struct clk_branch gcc_qpic_clk = {
3558         .halt_reg = 0x57020,
3559         .clkr = {
3560                 .enable_reg = 0x57020,
3561                 .enable_mask = BIT(0),
3562                 .hw.init = &(struct clk_init_data){
3563                         .name = "gcc_qpic_clk",
3564                         .parent_hws = (const struct clk_hw *[]){
3565                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3566                         .num_parents = 1,
3567                         .flags = CLK_SET_RATE_PARENT,
3568                         .ops = &clk_branch2_ops,
3569                 },
3570         },
3571 };
3572
3573 static struct clk_branch gcc_sdcc1_ahb_clk = {
3574         .halt_reg = 0x4201c,
3575         .clkr = {
3576                 .enable_reg = 0x4201c,
3577                 .enable_mask = BIT(0),
3578                 .hw.init = &(struct clk_init_data){
3579                         .name = "gcc_sdcc1_ahb_clk",
3580                         .parent_hws = (const struct clk_hw *[]){
3581                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3582                         .num_parents = 1,
3583                         .flags = CLK_SET_RATE_PARENT,
3584                         .ops = &clk_branch2_ops,
3585                 },
3586         },
3587 };
3588
3589 static struct clk_branch gcc_sdcc1_apps_clk = {
3590         .halt_reg = 0x42018,
3591         .clkr = {
3592                 .enable_reg = 0x42018,
3593                 .enable_mask = BIT(0),
3594                 .hw.init = &(struct clk_init_data){
3595                         .name = "gcc_sdcc1_apps_clk",
3596                         .parent_hws = (const struct clk_hw *[]){
3597                                         &sdcc1_apps_clk_src.clkr.hw },
3598                         .num_parents = 1,
3599                         .flags = CLK_SET_RATE_PARENT,
3600                         .ops = &clk_branch2_ops,
3601                 },
3602         },
3603 };
3604
3605 static struct clk_branch gcc_uniphy0_ahb_clk = {
3606         .halt_reg = 0x56008,
3607         .clkr = {
3608                 .enable_reg = 0x56008,
3609                 .enable_mask = BIT(0),
3610                 .hw.init = &(struct clk_init_data){
3611                         .name = "gcc_uniphy0_ahb_clk",
3612                         .parent_hws = (const struct clk_hw *[]){
3613                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3614                         .num_parents = 1,
3615                         .flags = CLK_SET_RATE_PARENT,
3616                         .ops = &clk_branch2_ops,
3617                 },
3618         },
3619 };
3620
3621 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3622         .halt_reg = 0x56010,
3623         .clkr = {
3624                 .enable_reg = 0x56010,
3625                 .enable_mask = BIT(0),
3626                 .hw.init = &(struct clk_init_data){
3627                         .name = "gcc_uniphy0_port1_rx_clk",
3628                         .parent_hws = (const struct clk_hw *[]){
3629                                         &nss_port1_rx_div_clk_src.clkr.hw },
3630                         .num_parents = 1,
3631                         .flags = CLK_SET_RATE_PARENT,
3632                         .ops = &clk_branch2_ops,
3633                 },
3634         },
3635 };
3636
3637 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3638         .halt_reg = 0x56014,
3639         .clkr = {
3640                 .enable_reg = 0x56014,
3641                 .enable_mask = BIT(0),
3642                 .hw.init = &(struct clk_init_data){
3643                         .name = "gcc_uniphy0_port1_tx_clk",
3644                         .parent_hws = (const struct clk_hw *[]){
3645                                         &nss_port1_tx_div_clk_src.clkr.hw },
3646                         .num_parents = 1,
3647                         .flags = CLK_SET_RATE_PARENT,
3648                         .ops = &clk_branch2_ops,
3649                 },
3650         },
3651 };
3652
3653 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3654         .halt_reg = 0x56018,
3655         .clkr = {
3656                 .enable_reg = 0x56018,
3657                 .enable_mask = BIT(0),
3658                 .hw.init = &(struct clk_init_data){
3659                         .name = "gcc_uniphy0_port2_rx_clk",
3660                         .parent_hws = (const struct clk_hw *[]){
3661                                         &nss_port2_rx_div_clk_src.clkr.hw },
3662                         .num_parents = 1,
3663                         .flags = CLK_SET_RATE_PARENT,
3664                         .ops = &clk_branch2_ops,
3665                 },
3666         },
3667 };
3668
3669 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3670         .halt_reg = 0x5601c,
3671         .clkr = {
3672                 .enable_reg = 0x5601c,
3673                 .enable_mask = BIT(0),
3674                 .hw.init = &(struct clk_init_data){
3675                         .name = "gcc_uniphy0_port2_tx_clk",
3676                         .parent_hws = (const struct clk_hw *[]){
3677                                         &nss_port2_tx_div_clk_src.clkr.hw },
3678                         .num_parents = 1,
3679                         .flags = CLK_SET_RATE_PARENT,
3680                         .ops = &clk_branch2_ops,
3681                 },
3682         },
3683 };
3684
3685 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3686         .halt_reg = 0x56020,
3687         .clkr = {
3688                 .enable_reg = 0x56020,
3689                 .enable_mask = BIT(0),
3690                 .hw.init = &(struct clk_init_data){
3691                         .name = "gcc_uniphy0_port3_rx_clk",
3692                         .parent_hws = (const struct clk_hw *[]){
3693                                         &nss_port3_rx_div_clk_src.clkr.hw },
3694                         .num_parents = 1,
3695                         .flags = CLK_SET_RATE_PARENT,
3696                         .ops = &clk_branch2_ops,
3697                 },
3698         },
3699 };
3700
3701 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3702         .halt_reg = 0x56024,
3703         .clkr = {
3704                 .enable_reg = 0x56024,
3705                 .enable_mask = BIT(0),
3706                 .hw.init = &(struct clk_init_data){
3707                         .name = "gcc_uniphy0_port3_tx_clk",
3708                         .parent_hws = (const struct clk_hw *[]){
3709                                         &nss_port3_tx_div_clk_src.clkr.hw },
3710                         .num_parents = 1,
3711                         .flags = CLK_SET_RATE_PARENT,
3712                         .ops = &clk_branch2_ops,
3713                 },
3714         },
3715 };
3716
3717 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3718         .halt_reg = 0x56028,
3719         .clkr = {
3720                 .enable_reg = 0x56028,
3721                 .enable_mask = BIT(0),
3722                 .hw.init = &(struct clk_init_data){
3723                         .name = "gcc_uniphy0_port4_rx_clk",
3724                         .parent_hws = (const struct clk_hw *[]){
3725                                         &nss_port4_rx_div_clk_src.clkr.hw },
3726                         .num_parents = 1,
3727                         .flags = CLK_SET_RATE_PARENT,
3728                         .ops = &clk_branch2_ops,
3729                 },
3730         },
3731 };
3732
3733 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3734         .halt_reg = 0x5602c,
3735         .clkr = {
3736                 .enable_reg = 0x5602c,
3737                 .enable_mask = BIT(0),
3738                 .hw.init = &(struct clk_init_data){
3739                         .name = "gcc_uniphy0_port4_tx_clk",
3740                         .parent_hws = (const struct clk_hw *[]){
3741                                         &nss_port4_tx_div_clk_src.clkr.hw },
3742                         .num_parents = 1,
3743                         .flags = CLK_SET_RATE_PARENT,
3744                         .ops = &clk_branch2_ops,
3745                 },
3746         },
3747 };
3748
3749 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
3750         .halt_reg = 0x56030,
3751         .clkr = {
3752                 .enable_reg = 0x56030,
3753                 .enable_mask = BIT(0),
3754                 .hw.init = &(struct clk_init_data){
3755                         .name = "gcc_uniphy0_port5_rx_clk",
3756                         .parent_hws = (const struct clk_hw *[]){
3757                                         &nss_port5_rx_div_clk_src.clkr.hw },
3758                         .num_parents = 1,
3759                         .flags = CLK_SET_RATE_PARENT,
3760                         .ops = &clk_branch2_ops,
3761                 },
3762         },
3763 };
3764
3765 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
3766         .halt_reg = 0x56034,
3767         .clkr = {
3768                 .enable_reg = 0x56034,
3769                 .enable_mask = BIT(0),
3770                 .hw.init = &(struct clk_init_data){
3771                         .name = "gcc_uniphy0_port5_tx_clk",
3772                         .parent_hws = (const struct clk_hw *[]){
3773                                         &nss_port5_tx_div_clk_src.clkr.hw },
3774                         .num_parents = 1,
3775                         .flags = CLK_SET_RATE_PARENT,
3776                         .ops = &clk_branch2_ops,
3777                 },
3778         },
3779 };
3780
3781 static struct clk_branch gcc_uniphy0_sys_clk = {
3782         .halt_reg = 0x5600C,
3783         .clkr = {
3784                 .enable_reg = 0x5600C,
3785                 .enable_mask = BIT(0),
3786                 .hw.init = &(struct clk_init_data){
3787                         .name = "gcc_uniphy0_sys_clk",
3788                         .parent_hws = (const struct clk_hw *[]){
3789                                         &gcc_xo_clk_src.clkr.hw },
3790                         .num_parents = 1,
3791                         .flags = CLK_SET_RATE_PARENT,
3792                         .ops = &clk_branch2_ops,
3793                 },
3794         },
3795 };
3796
3797 static struct clk_branch gcc_uniphy1_ahb_clk = {
3798         .halt_reg = 0x56108,
3799         .clkr = {
3800                 .enable_reg = 0x56108,
3801                 .enable_mask = BIT(0),
3802                 .hw.init = &(struct clk_init_data){
3803                         .name = "gcc_uniphy1_ahb_clk",
3804                         .parent_hws = (const struct clk_hw *[]){
3805                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3806                         .num_parents = 1,
3807                         .flags = CLK_SET_RATE_PARENT,
3808                         .ops = &clk_branch2_ops,
3809                 },
3810         },
3811 };
3812
3813 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
3814         .halt_reg = 0x56110,
3815         .clkr = {
3816                 .enable_reg = 0x56110,
3817                 .enable_mask = BIT(0),
3818                 .hw.init = &(struct clk_init_data){
3819                         .name = "gcc_uniphy1_port5_rx_clk",
3820                         .parent_hws = (const struct clk_hw *[]){
3821                                         &nss_port5_rx_div_clk_src.clkr.hw },
3822                         .num_parents = 1,
3823                         .flags = CLK_SET_RATE_PARENT,
3824                         .ops = &clk_branch2_ops,
3825                 },
3826         },
3827 };
3828
3829 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
3830         .halt_reg = 0x56114,
3831         .clkr = {
3832                 .enable_reg = 0x56114,
3833                 .enable_mask = BIT(0),
3834                 .hw.init = &(struct clk_init_data){
3835                         .name = "gcc_uniphy1_port5_tx_clk",
3836                         .parent_hws = (const struct clk_hw *[]){
3837                                         &nss_port5_tx_div_clk_src.clkr.hw },
3838                         .num_parents = 1,
3839                         .flags = CLK_SET_RATE_PARENT,
3840                         .ops = &clk_branch2_ops,
3841                 },
3842         },
3843 };
3844
3845 static struct clk_branch gcc_uniphy1_sys_clk = {
3846         .halt_reg = 0x5610C,
3847         .clkr = {
3848                 .enable_reg = 0x5610C,
3849                 .enable_mask = BIT(0),
3850                 .hw.init = &(struct clk_init_data){
3851                         .name = "gcc_uniphy1_sys_clk",
3852                         .parent_hws = (const struct clk_hw *[]){
3853                                         &gcc_xo_clk_src.clkr.hw },
3854                         .num_parents = 1,
3855                         .flags = CLK_SET_RATE_PARENT,
3856                         .ops = &clk_branch2_ops,
3857                 },
3858         },
3859 };
3860
3861 static struct clk_branch gcc_usb0_aux_clk = {
3862         .halt_reg = 0x3e044,
3863         .clkr = {
3864                 .enable_reg = 0x3e044,
3865                 .enable_mask = BIT(0),
3866                 .hw.init = &(struct clk_init_data){
3867                         .name = "gcc_usb0_aux_clk",
3868                         .parent_hws = (const struct clk_hw *[]){
3869                                         &usb0_aux_clk_src.clkr.hw },
3870                         .num_parents = 1,
3871                         .flags = CLK_SET_RATE_PARENT,
3872                         .ops = &clk_branch2_ops,
3873                 },
3874         },
3875 };
3876
3877 static struct clk_branch gcc_usb0_master_clk = {
3878         .halt_reg = 0x3e000,
3879         .clkr = {
3880                 .enable_reg = 0x3e000,
3881                 .enable_mask = BIT(0),
3882                 .hw.init = &(struct clk_init_data){
3883                         .name = "gcc_usb0_master_clk",
3884                         .parent_hws = (const struct clk_hw *[]){
3885                                         &usb0_master_clk_src.clkr.hw },
3886                         .num_parents = 1,
3887                         .flags = CLK_SET_RATE_PARENT,
3888                         .ops = &clk_branch2_ops,
3889                 },
3890         },
3891 };
3892
3893 static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
3894         .halt_reg = 0x47014,
3895         .clkr = {
3896                 .enable_reg = 0x47014,
3897                 .enable_mask = BIT(0),
3898                 .hw.init = &(struct clk_init_data){
3899                         .name = "gcc_snoc_bus_timeout2_ahb_clk",
3900                         .parent_hws = (const struct clk_hw *[]){
3901                                         &usb0_master_clk_src.clkr.hw },
3902                         .num_parents = 1,
3903                         .flags = CLK_SET_RATE_PARENT,
3904                         .ops = &clk_branch2_ops,
3905                 },
3906         },
3907 };
3908
3909 static struct clk_rcg2 pcie0_rchng_clk_src = {
3910         .cmd_rcgr = 0x75070,
3911         .freq_tbl = ftbl_pcie_rchng_clk_src,
3912         .hid_width = 5,
3913         .parent_map = gcc_xo_gpll0_map,
3914         .clkr.hw.init = &(struct clk_init_data){
3915                 .name = "pcie0_rchng_clk_src",
3916                 .parent_data = gcc_xo_gpll0,
3917                 .num_parents = 2,
3918                 .ops = &clk_rcg2_ops,
3919         },
3920 };
3921
3922 static struct clk_branch gcc_pcie0_rchng_clk = {
3923         .halt_reg = 0x75070,
3924         .clkr = {
3925                 .enable_reg = 0x75070,
3926                 .enable_mask = BIT(1),
3927                 .hw.init = &(struct clk_init_data){
3928                         .name = "gcc_pcie0_rchng_clk",
3929                         .parent_hws = (const struct clk_hw *[]){
3930                                         &pcie0_rchng_clk_src.clkr.hw },
3931                         .num_parents = 1,
3932                         .flags = CLK_SET_RATE_PARENT,
3933                         .ops = &clk_branch2_ops,
3934                 },
3935         },
3936 };
3937
3938 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
3939         .halt_reg = 0x75048,
3940         .clkr = {
3941                 .enable_reg = 0x75048,
3942                 .enable_mask = BIT(0),
3943                 .hw.init = &(struct clk_init_data){
3944                         .name = "gcc_pcie0_axi_s_bridge_clk",
3945                         .parent_hws = (const struct clk_hw *[]){
3946                                         &pcie0_axi_clk_src.clkr.hw },
3947                         .num_parents = 1,
3948                         .flags = CLK_SET_RATE_PARENT,
3949                         .ops = &clk_branch2_ops,
3950                 },
3951         },
3952 };
3953
3954 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
3955         .halt_reg = 0x26040,
3956         .clkr = {
3957                 .enable_reg = 0x26040,
3958                 .enable_mask = BIT(0),
3959                 .hw.init = &(struct clk_init_data){
3960                         .name = "gcc_sys_noc_usb0_axi_clk",
3961                         .parent_hws = (const struct clk_hw *[]){
3962                                         &usb0_master_clk_src.clkr.hw },
3963                         .num_parents = 1,
3964                         .flags = CLK_SET_RATE_PARENT,
3965                         .ops = &clk_branch2_ops,
3966                 },
3967         },
3968 };
3969
3970 static struct clk_branch gcc_usb0_mock_utmi_clk = {
3971         .halt_reg = 0x3e008,
3972         .clkr = {
3973                 .enable_reg = 0x3e008,
3974                 .enable_mask = BIT(0),
3975                 .hw.init = &(struct clk_init_data){
3976                         .name = "gcc_usb0_mock_utmi_clk",
3977                         .parent_hws = (const struct clk_hw *[]){
3978                                         &usb0_mock_utmi_clk_src.clkr.hw },
3979                         .num_parents = 1,
3980                         .flags = CLK_SET_RATE_PARENT,
3981                         .ops = &clk_branch2_ops,
3982                 },
3983         },
3984 };
3985
3986 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3987         .halt_reg = 0x3e080,
3988         .clkr = {
3989                 .enable_reg = 0x3e080,
3990                 .enable_mask = BIT(0),
3991                 .hw.init = &(struct clk_init_data){
3992                         .name = "gcc_usb0_phy_cfg_ahb_clk",
3993                         .parent_hws = (const struct clk_hw *[]){
3994                                         &pcnoc_bfdcd_clk_src.clkr.hw },
3995                         .num_parents = 1,
3996                         .flags = CLK_SET_RATE_PARENT,
3997                         .ops = &clk_branch2_ops,
3998                 },
3999         },
4000 };
4001
4002 static struct clk_branch gcc_usb0_pipe_clk = {
4003         .halt_reg = 0x3e040,
4004         .halt_check = BRANCH_HALT_DELAY,
4005         .clkr = {
4006                 .enable_reg = 0x3e040,
4007                 .enable_mask = BIT(0),
4008                 .hw.init = &(struct clk_init_data){
4009                         .name = "gcc_usb0_pipe_clk",
4010                         .parent_hws = (const struct clk_hw *[]){
4011                                         &usb0_pipe_clk_src.clkr.hw },
4012                         .num_parents = 1,
4013                         .flags = CLK_SET_RATE_PARENT,
4014                         .ops = &clk_branch2_ops,
4015                 },
4016         },
4017 };
4018
4019 static struct clk_branch gcc_usb0_sleep_clk = {
4020         .halt_reg = 0x3e004,
4021         .clkr = {
4022                 .enable_reg = 0x3e004,
4023                 .enable_mask = BIT(0),
4024                 .hw.init = &(struct clk_init_data){
4025                         .name = "gcc_usb0_sleep_clk",
4026                         .parent_hws = (const struct clk_hw *[]){
4027                                         &gcc_sleep_clk_src.clkr.hw },
4028                         .num_parents = 1,
4029                         .flags = CLK_SET_RATE_PARENT,
4030                         .ops = &clk_branch2_ops,
4031                 },
4032         },
4033 };
4034
4035 static struct clk_branch gcc_usb1_master_clk = {
4036         .halt_reg = 0x3f000,
4037         .clkr = {
4038                 .enable_reg = 0x3f000,
4039                 .enable_mask = BIT(0),
4040                 .hw.init = &(struct clk_init_data){
4041                         .name = "gcc_usb1_master_clk",
4042                         .parent_hws = (const struct clk_hw *[]){
4043                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4044                         .num_parents = 1,
4045                         .flags = CLK_SET_RATE_PARENT,
4046                         .ops = &clk_branch2_ops,
4047                 },
4048         },
4049 };
4050
4051 static struct clk_branch gcc_usb1_mock_utmi_clk = {
4052         .halt_reg = 0x3f008,
4053         .clkr = {
4054                 .enable_reg = 0x3f008,
4055                 .enable_mask = BIT(0),
4056                 .hw.init = &(struct clk_init_data){
4057                         .name = "gcc_usb1_mock_utmi_clk",
4058                         .parent_hws = (const struct clk_hw *[]){
4059                                         &usb1_mock_utmi_clk_src.clkr.hw },
4060                         .num_parents = 1,
4061                         .flags = CLK_SET_RATE_PARENT,
4062                         .ops = &clk_branch2_ops,
4063                 },
4064         },
4065 };
4066
4067 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
4068         .halt_reg = 0x3f080,
4069         .clkr = {
4070                 .enable_reg = 0x3f080,
4071                 .enable_mask = BIT(0),
4072                 .hw.init = &(struct clk_init_data){
4073                         .name = "gcc_usb1_phy_cfg_ahb_clk",
4074                         .parent_hws = (const struct clk_hw *[]){
4075                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4076                         .num_parents = 1,
4077                         .flags = CLK_SET_RATE_PARENT,
4078                         .ops = &clk_branch2_ops,
4079                 },
4080         },
4081 };
4082
4083 static struct clk_branch gcc_usb1_sleep_clk = {
4084         .halt_reg = 0x3f004,
4085         .clkr = {
4086                 .enable_reg = 0x3f004,
4087                 .enable_mask = BIT(0),
4088                 .hw.init = &(struct clk_init_data){
4089                         .name = "gcc_usb1_sleep_clk",
4090                         .parent_hws = (const struct clk_hw *[]){
4091                                         &gcc_sleep_clk_src.clkr.hw },
4092                         .num_parents = 1,
4093                         .flags = CLK_SET_RATE_PARENT,
4094                         .ops = &clk_branch2_ops,
4095                 },
4096         },
4097 };
4098
4099 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
4100         .halt_reg = 0x56308,
4101         .clkr = {
4102                 .enable_reg = 0x56308,
4103                 .enable_mask = BIT(0),
4104                 .hw.init = &(struct clk_init_data){
4105                         .name = "gcc_cmn_12gpll_ahb_clk",
4106                         .parent_hws = (const struct clk_hw *[]){
4107                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4108                         .num_parents = 1,
4109                         .flags = CLK_SET_RATE_PARENT,
4110                         .ops = &clk_branch2_ops,
4111                 },
4112         },
4113 };
4114
4115 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
4116         .halt_reg = 0x5630c,
4117         .clkr = {
4118                 .enable_reg = 0x5630c,
4119                 .enable_mask = BIT(0),
4120                 .hw.init = &(struct clk_init_data){
4121                         .name = "gcc_cmn_12gpll_sys_clk",
4122                         .parent_hws = (const struct clk_hw *[]){
4123                                         &gcc_xo_clk_src.clkr.hw },
4124                         .num_parents = 1,
4125                         .flags = CLK_SET_RATE_PARENT,
4126                         .ops = &clk_branch2_ops,
4127                 },
4128         },
4129 };
4130
4131 static struct clk_branch gcc_sdcc1_ice_core_clk = {
4132         .halt_reg = 0x5d014,
4133         .clkr = {
4134                 .enable_reg = 0x5d014,
4135                 .enable_mask = BIT(0),
4136                 .hw.init = &(struct clk_init_data){
4137                         .name = "gcc_sdcc1_ice_core_clk",
4138                         .parent_hws = (const struct clk_hw *[]){
4139                                         &sdcc1_ice_core_clk_src.clkr.hw },
4140                         .num_parents = 1,
4141                         .flags = CLK_SET_RATE_PARENT,
4142                         .ops = &clk_branch2_ops,
4143                 },
4144         },
4145 };
4146
4147 static struct clk_branch gcc_dcc_clk = {
4148         .halt_reg = 0x77004,
4149         .clkr = {
4150                 .enable_reg = 0x77004,
4151                 .enable_mask = BIT(0),
4152                 .hw.init = &(struct clk_init_data){
4153                         .name = "gcc_dcc_clk",
4154                         .parent_hws = (const struct clk_hw *[]){
4155                                         &pcnoc_bfdcd_clk_src.clkr.hw },
4156                         .num_parents = 1,
4157                         .flags = CLK_SET_RATE_PARENT,
4158                         .ops = &clk_branch2_ops,
4159                 },
4160         },
4161 };
4162
4163 static const struct alpha_pll_config ubi32_pll_config = {
4164         .l = 0x3e,
4165         .alpha = 0x6667,
4166         .config_ctl_val = 0x240d4828,
4167         .config_ctl_hi_val = 0x6,
4168         .main_output_mask = BIT(0),
4169         .aux_output_mask = BIT(1),
4170         .pre_div_val = 0x0,
4171         .pre_div_mask = BIT(12),
4172         .post_div_val = 0x0,
4173         .post_div_mask = GENMASK(9, 8),
4174         .alpha_en_mask = BIT(24),
4175         .test_ctl_val = 0x1C0000C0,
4176         .test_ctl_hi_val = 0x4000,
4177 };
4178
4179 static const struct alpha_pll_config nss_crypto_pll_config = {
4180         .l = 0x32,
4181         .alpha = 0x0,
4182         .alpha_hi = 0x0,
4183         .config_ctl_val = 0x4001055b,
4184         .main_output_mask = BIT(0),
4185         .pre_div_val = 0x0,
4186         .pre_div_mask = GENMASK(14, 12),
4187         .post_div_val = 0x1 << 8,
4188         .post_div_mask = GENMASK(11, 8),
4189         .vco_mask = GENMASK(21, 20),
4190         .vco_val = 0x0,
4191         .alpha_en_mask = BIT(24),
4192 };
4193
4194 static struct clk_hw *gcc_ipq6018_hws[] = {
4195         &gpll0_out_main_div2.hw,
4196         &gcc_xo_div4_clk_src.hw,
4197         &nss_ppe_cdiv_clk_src.hw,
4198         &gpll6_out_main_div2.hw,
4199         &qdss_dap_sync_clk_src.hw,
4200         &qdss_tsctr_div2_clk_src.hw,
4201 };
4202
4203 static struct clk_regmap *gcc_ipq6018_clks[] = {
4204         [GPLL0_MAIN] = &gpll0_main.clkr,
4205         [GPLL0] = &gpll0.clkr,
4206         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4207         [UBI32_PLL] = &ubi32_pll.clkr,
4208         [GPLL6_MAIN] = &gpll6_main.clkr,
4209         [GPLL6] = &gpll6.clkr,
4210         [GPLL4_MAIN] = &gpll4_main.clkr,
4211         [GPLL4] = &gpll4.clkr,
4212         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4213         [GPLL2_MAIN] = &gpll2_main.clkr,
4214         [GPLL2] = &gpll2.clkr,
4215         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4216         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4217         [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4218         [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4219         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4220         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4221         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4222         [SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
4223         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4224         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4225         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4226         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4227         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4228         [UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
4229         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4230         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4231         [APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
4232         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4233         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4234         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4235         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4236         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4237         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4238         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4239         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4240         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4241         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4242         [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4243         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4244         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4245         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4246         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4247         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4248         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4249         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4250         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4251         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4252         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4253         [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4254         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4255         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4256         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4257         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4258         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4259         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4260         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4261         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4262         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4263         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4264         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4265         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4266         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4267         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4268         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4269         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4270         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4271         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4272         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4273         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4274         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4275         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4276         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4277         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4278         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4279         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4280         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4281         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4282         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4283         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4284         [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4285         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4286         [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4287         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4288         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4289         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4290         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4291         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4292         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4293         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4294         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4295         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4296         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4297         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4298         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4299         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4300         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4301         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4302         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4303         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4304         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4305         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4306         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4307         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4308         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4309         [GCC_XO_CLK] = &gcc_xo_clk.clkr,
4310         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4311         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4312         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4313         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4314         [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4315         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4316         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4317         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4318         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4319         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4320         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4321         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4322         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4323         [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
4324         [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
4325         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4326         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4327         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4328         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4329         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4330         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4331         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4332         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4333         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4334         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4335         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4336         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4337         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4338         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4339         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4340         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4341         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4342         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4343         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4344         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4345         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4346         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4347         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4348         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4349         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4350         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4351         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4352         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4353         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4354         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4355         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4356         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4357         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4358         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4359         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4360         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4361         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4362         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4363         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4364         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4365         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4366         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4367         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4368         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4369         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4370         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4371         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4372         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4373         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4374         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4375         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4376         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4377         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4378         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4379         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4380         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4381         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4382         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4383         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4384         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4385         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4386         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4387         [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
4388         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4389         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4390         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4391         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4392         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4393         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4394         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4395         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4396         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4397         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4398         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4399         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4400         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4401         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4402         [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4403         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4404         [PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4405         [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4406         [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4407         [RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
4408         [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
4409         [LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
4410         [GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
4411         [LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
4412         [GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
4413         [LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
4414         [GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
4415         [GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
4416         [GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
4417         [GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
4418         [GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
4419         [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
4420         [GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
4421         [GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
4422         [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
4423         [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4424         [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4425 };
4426
4427 static const struct qcom_reset_map gcc_ipq6018_resets[] = {
4428         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4429         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4430         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4431         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4432         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4433         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4434         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4435         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4436         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4437         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4438         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4439         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4440         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4441         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4442         [GCC_SMMU_BCR] = { 0x12000, 0 },
4443         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4444         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4445         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4446         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4447         [GCC_PRNG_BCR] = { 0x13000, 0 },
4448         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4449         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4450         [GCC_WCSS_BCR] = { 0x18000, 0 },
4451         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4452         [GCC_NSS_BCR] = { 0x19000, 0 },
4453         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4454         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4455         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4456         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4457         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4458         [GCC_TCSR_BCR] = { 0x28000, 0 },
4459         [GCC_QDSS_BCR] = { 0x29000, 0 },
4460         [GCC_DCD_BCR] = { 0x2a000, 0 },
4461         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4462         [GCC_MPM_BCR] = { 0x2c000, 0 },
4463         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4464         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4465         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4466         [GCC_TLMM_BCR] = { 0x34000, 0 },
4467         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4468         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4469         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4470         [GCC_USB0_BCR] = { 0x3e070, 0 },
4471         [GCC_USB1_BCR] = { 0x3f070, 0 },
4472         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4473         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4474         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4475         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4476         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4477         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4478         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4479         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4480         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4481         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4482         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4483         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4484         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4485         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4486         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4487         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4488         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4489         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4490         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4491         [GCC_QPIC_BCR] = { 0x57018, 0 },
4492         [GCC_MDIO_BCR] = { 0x58000, 0 },
4493         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4494         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4495         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4496         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4497         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4498         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4499         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4500         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4501         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4502         [GCC_DCC_BCR] = { 0x77000, 0 },
4503         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4504         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4505         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4506         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4507         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4508         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4509         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4510         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4511         [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4512         [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4513         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4514         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4515         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4516         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4517         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4518         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4519         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4520         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4521         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4522         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4523         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4524         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4525         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4526         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4527         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4528         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4529         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4530         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4531         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4532         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4533         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4534         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4535         [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4536         [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4537         [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4538         [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4539         [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4540         [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4541         [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4542         [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4543         [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4544         [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4545         [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4546         [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4547         [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4548         [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4549         [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4550         [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4551         [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4552         [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4553         [GCC_LPASS_BCR] = {0x1F000, 0},
4554         [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4555         [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4556         [GCC_WCSSAON_RESET] = {0x59010, 0},
4557         [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4558         [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4559         [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4560         [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4561         [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4562         [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4563         [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4564         [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4565         [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4566         [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4567         [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4568         [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4569         [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4570         [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4571         [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4572         [GCC_Q6_AHB_ARES] = {0x59110, 2},
4573         [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4574         [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4575 };
4576
4577 static const struct of_device_id gcc_ipq6018_match_table[] = {
4578         { .compatible = "qcom,gcc-ipq6018" },
4579         { }
4580 };
4581 MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
4582
4583 static const struct regmap_config gcc_ipq6018_regmap_config = {
4584         .reg_bits       = 32,
4585         .reg_stride     = 4,
4586         .val_bits       = 32,
4587         .max_register   = 0x7fffc,
4588         .fast_io        = true,
4589 };
4590
4591 static const struct qcom_cc_desc gcc_ipq6018_desc = {
4592         .config = &gcc_ipq6018_regmap_config,
4593         .clks = gcc_ipq6018_clks,
4594         .num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
4595         .resets = gcc_ipq6018_resets,
4596         .num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
4597         .clk_hws = gcc_ipq6018_hws,
4598         .num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
4599 };
4600
4601 static int gcc_ipq6018_probe(struct platform_device *pdev)
4602 {
4603         struct regmap *regmap;
4604
4605         regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
4606         if (IS_ERR(regmap))
4607                 return PTR_ERR(regmap);
4608
4609         /* Disable SW_COLLAPSE for USB0 GDSCR */
4610         regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
4611         /* Enable SW_OVERRIDE for USB0 GDSCR */
4612         regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
4613         /* Disable SW_COLLAPSE for USB1 GDSCR */
4614         regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
4615         /* Enable SW_OVERRIDE for USB1 GDSCR */
4616         regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
4617
4618         /* SW Workaround for UBI Huyara PLL */
4619         regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4620
4621         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4622
4623         clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4624                                 &nss_crypto_pll_config);
4625
4626         return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
4627 }
4628
4629 static struct platform_driver gcc_ipq6018_driver = {
4630         .probe = gcc_ipq6018_probe,
4631         .driver = {
4632                 .name   = "qcom,gcc-ipq6018",
4633                 .of_match_table = gcc_ipq6018_match_table,
4634         },
4635 };
4636
4637 static int __init gcc_ipq6018_init(void)
4638 {
4639         return platform_driver_register(&gcc_ipq6018_driver);
4640 }
4641 core_initcall(gcc_ipq6018_init);
4642
4643 static void __exit gcc_ipq6018_exit(void)
4644 {
4645         platform_driver_unregister(&gcc_ipq6018_driver);
4646 }
4647 module_exit(gcc_ipq6018_exit);
4648
4649 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
4650 MODULE_LICENSE("GPL v2");