gcc-ipq5018.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2023, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/clk-provider.h>
   6 #include <linux/mod_devicetable.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
  12 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
  13
  14 #include "clk-alpha-pll.h"
  15 #include "clk-branch.h"
  16 #include "clk-rcg.h"
  17 #include "clk-regmap.h"
  18 #include "clk-regmap-divider.h"
  19 #include "clk-regmap-mux.h"
  20 #include "clk-regmap-phy-mux.h"
  21 #include "reset.h"
  22
  23 /* Need to match the order of clocks in DT binding */
  24 enum {
  25         DT_XO,
  26         DT_SLEEP_CLK,
  27         DT_PCIE20_PHY0_PIPE_CLK,
  28         DT_PCIE20_PHY1_PIPE_CLK,
  29         DT_USB3_PHY0_CC_PIPE_CLK,
  30         DT_GEPHY_RX_CLK,
  31         DT_GEPHY_TX_CLK,
  32         DT_UNIPHY_RX_CLK,
  33         DT_UNIPHY_TX_CLK,
  34 };
  35
  36 enum {
  37         P_XO,
  38         P_CORE_PI_SLEEP_CLK,
  39         P_PCIE20_PHY0_PIPE,
  40         P_PCIE20_PHY1_PIPE,
  41         P_USB3PHY_0_PIPE,
  42         P_GEPHY_RX,
  43         P_GEPHY_TX,
  44         P_UNIPHY_RX,
  45         P_UNIPHY_TX,
  46         P_GPLL0,
  47         P_GPLL0_DIV2,
  48         P_GPLL2,
  49         P_GPLL4,
  50         P_UBI32_PLL,
  51 };
  52
  53 static const struct clk_parent_data gcc_xo_data[] = {
  54         { .index = DT_XO },
  55 };
  56
  57 static const struct clk_parent_data gcc_sleep_clk_data[] = {
  58         { .index = DT_SLEEP_CLK },
  59 };
  60
  61 static struct clk_alpha_pll gpll0_main = {
  62         .offset = 0x21000,
  63         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  64         .clkr = {
  65                 .enable_reg = 0x0b000,
  66                 .enable_mask = BIT(0),
  67                 .hw.init = &(struct clk_init_data) {
  68                         .name = "gpll0_main",
  69                         .parent_data = gcc_xo_data,
  70                         .num_parents = ARRAY_SIZE(gcc_xo_data),
  71                         .ops = &clk_alpha_pll_stromer_ops,
  72                 },
  73         },
  74 };
  75
  76 static struct clk_alpha_pll gpll2_main = {
  77         .offset = 0x4a000,
  78         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  79         .clkr = {
  80                 .enable_reg = 0x0b000,
  81                 .enable_mask = BIT(2),
  82                 .hw.init = &(struct clk_init_data) {
  83                         .name = "gpll2_main",
  84                         .parent_data = gcc_xo_data,
  85                         .num_parents = ARRAY_SIZE(gcc_xo_data),
  86                         .ops = &clk_alpha_pll_stromer_ops,
  87                 },
  88         },
  89 };
  90
  91 static struct clk_alpha_pll gpll4_main = {
  92         .offset = 0x24000,
  93         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  94         .clkr = {
  95                 .enable_reg = 0x0b000,
  96                 .enable_mask = BIT(5),
  97                 .hw.init = &(struct clk_init_data) {
  98                         .name = "gpll4_main",
  99                         .parent_data = gcc_xo_data,
 100                         .num_parents = ARRAY_SIZE(gcc_xo_data),
 101                         .ops = &clk_alpha_pll_stromer_ops,
 102                 },
 103         },
 104 };
 105
 106 static struct clk_alpha_pll ubi32_pll_main = {
 107         .offset = 0x25000,
 108         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 109         .clkr = {
 110                 .enable_reg = 0x0b000,
 111                 .enable_mask = BIT(6),
 112                 .hw.init = &(struct clk_init_data) {
 113                         .name = "ubi32_pll_main",
 114                         .parent_data = gcc_xo_data,
 115                         .num_parents = ARRAY_SIZE(gcc_xo_data),
 116                         .ops = &clk_alpha_pll_stromer_ops,
 117                 },
 118         },
 119 };
 120
 121 static struct clk_alpha_pll_postdiv gpll0 = {
 122         .offset = 0x21000,
 123         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 124         .width = 4,
 125         .clkr.hw.init = &(struct clk_init_data) {
 126                 .name = "gpll0",
 127                 .parent_hws = (const struct clk_hw *[]) {
 128                         &gpll0_main.clkr.hw,
 129                 },
 130                 .num_parents = 1,
 131                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 132         },
 133 };
 134
 135 static struct clk_alpha_pll_postdiv gpll2 = {
 136         .offset = 0x4a000,
 137         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 138         .width = 4,
 139         .clkr.hw.init = &(struct clk_init_data) {
 140                 .name = "gpll2",
 141                 .parent_hws = (const struct clk_hw *[]) {
 142                         &gpll2_main.clkr.hw,
 143                 },
 144                 .num_parents = 1,
 145                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 146         },
 147 };
 148
 149 static struct clk_alpha_pll_postdiv gpll4 = {
 150         .offset = 0x24000,
 151         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 152         .width = 4,
 153         .clkr.hw.init = &(struct clk_init_data) {
 154                 .name = "gpll4",
 155                 .parent_hws = (const struct clk_hw *[]) {
 156                         &gpll4_main.clkr.hw,
 157                 },
 158                 .num_parents = 1,
 159                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 160         },
 161 };
 162
 163 static struct clk_alpha_pll_postdiv ubi32_pll = {
 164         .offset = 0x25000,
 165         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 166         .width = 4,
 167         .clkr.hw.init = &(struct clk_init_data) {
 168                 .name = "ubi32_pll",
 169                 .parent_hws = (const struct clk_hw *[]) {
 170                         &ubi32_pll_main.clkr.hw,
 171                 },
 172                 .num_parents = 1,
 173                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 174                 .flags = CLK_SET_RATE_PARENT,
 175         },
 176 };
 177
 178 static struct clk_fixed_factor gpll0_out_main_div2 = {
 179         .mult = 1,
 180         .div = 2,
 181         .hw.init = &(struct clk_init_data) {
 182                 .name = "gpll0_out_main_div2",
 183                 .parent_hws = (const struct clk_hw *[]) {
 184                         &gpll0_main.clkr.hw,
 185                 },
 186                 .num_parents = 1,
 187                 .ops = &clk_fixed_factor_ops,
 188                 .flags = CLK_SET_RATE_PARENT,
 189         },
 190 };
 191
 192 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 193         { .index = DT_XO },
 194         { .hw = &gpll0.clkr.hw },
 195         { .hw = &gpll0_out_main_div2.hw },
 196 };
 197
 198 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 199         { P_XO, 0 },
 200         { P_GPLL0, 1 },
 201         { P_GPLL0_DIV2, 4 },
 202 };
 203
 204 static const struct clk_parent_data gcc_xo_gpll0[] = {
 205         { .index = DT_XO },
 206         { .hw = &gpll0.clkr.hw },
 207 };
 208
 209 static const struct parent_map gcc_xo_gpll0_map[] = {
 210         { P_XO, 0 },
 211         { P_GPLL0, 1 },
 212 };
 213
 214 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 215         { .index = DT_XO },
 216         { .hw = &gpll0_out_main_div2.hw },
 217         { .hw = &gpll0.clkr.hw },
 218 };
 219
 220 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 221         { P_XO, 0 },
 222         { P_GPLL0_DIV2, 2 },
 223         { P_GPLL0, 1 },
 224 };
 225
 226 static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
 227         { .index = DT_XO },
 228         { .hw = &ubi32_pll.clkr.hw },
 229         { .hw = &gpll0.clkr.hw },
 230 };
 231
 232 static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
 233         { P_XO, 0 },
 234         { P_UBI32_PLL, 1 },
 235         { P_GPLL0, 2 },
 236 };
 237
 238 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 239         { .index = DT_XO },
 240         { .hw = &gpll0.clkr.hw },
 241         { .hw = &gpll2.clkr.hw },
 242 };
 243
 244 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 245         { P_XO, 0 },
 246         { P_GPLL0, 1 },
 247         { P_GPLL2, 2 },
 248 };
 249
 250 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
 251         { .index = DT_XO },
 252         { .hw = &gpll0.clkr.hw },
 253         { .hw = &gpll2.clkr.hw },
 254         { .hw = &gpll4.clkr.hw },
 255 };
 256
 257 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 258         { P_XO, 0 },
 259         { P_GPLL0, 1 },
 260         { P_GPLL2, 2 },
 261         { P_GPLL4, 3 },
 262 };
 263
 264 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 265         { .index = DT_XO },
 266         { .hw = &gpll0.clkr.hw },
 267         { .hw = &gpll4.clkr.hw },
 268 };
 269
 270 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 271         { P_XO, 0 },
 272         { P_GPLL0, 1 },
 273         { P_GPLL4, 2 },
 274 };
 275
 276 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
 277         { .index = DT_XO },
 278         { .hw = &gpll0.clkr.hw },
 279         { .index = DT_SLEEP_CLK },
 280 };
 281
 282 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
 283         { P_XO, 0 },
 284         { P_GPLL0, 2 },
 285         { P_CORE_PI_SLEEP_CLK, 6 },
 286 };
 287
 288 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
 289         { .index = DT_XO },
 290         { .hw = &gpll0.clkr.hw },
 291         { .hw = &gpll0_out_main_div2.hw },
 292         { .index = DT_SLEEP_CLK },
 293 };
 294
 295 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
 296         { P_XO, 0 },
 297         { P_GPLL0, 1 },
 298         { P_GPLL0_DIV2, 4 },
 299         { P_CORE_PI_SLEEP_CLK, 6 },
 300 };
 301
 302 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 303         { .index = DT_XO },
 304         { .hw = &gpll0.clkr.hw },
 305         { .hw = &gpll2.clkr.hw },
 306         { .hw = &gpll0_out_main_div2.hw },
 307 };
 308
 309 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 310         { P_XO, 0 },
 311         { P_GPLL0, 1 },
 312         { P_GPLL2, 2 },
 313         { P_GPLL0_DIV2, 4 },
 314 };
 315
 316 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
 317         { .index = DT_XO },
 318         { .hw = &gpll4.clkr.hw },
 319         { .hw = &gpll0.clkr.hw },
 320         { .hw = &gpll0_out_main_div2.hw },
 321 };
 322
 323 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
 324         { P_XO, 0 },
 325         { P_GPLL4, 1 },
 326         { P_GPLL0, 2 },
 327         { P_GPLL0_DIV2, 4 },
 328 };
 329
 330 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
 331         { P_XO, 0 },
 332         { P_GPLL4, 1 },
 333         { P_GPLL0, 3 },
 334         { P_GPLL0_DIV2, 4 },
 335 };
 336
 337 static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
 338         { .index = DT_XO },
 339         { .index = DT_GEPHY_RX_CLK },
 340         { .index = DT_GEPHY_TX_CLK },
 341         { .hw = &ubi32_pll.clkr.hw },
 342         { .hw = &gpll0.clkr.hw },
 343 };
 344
 345 static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
 346         { P_XO, 0 },
 347         { P_GEPHY_RX, 1 },
 348         { P_GEPHY_TX, 2 },
 349         { P_UBI32_PLL, 3 },
 350         { P_GPLL0, 4 },
 351 };
 352
 353 static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
 354         { .index = DT_XO },
 355         { .index = DT_GEPHY_TX_CLK },
 356         { .index = DT_GEPHY_RX_CLK },
 357         { .hw = &ubi32_pll.clkr.hw },
 358         { .hw = &gpll0.clkr.hw },
 359 };
 360
 361 static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
 362         { P_XO, 0 },
 363         { P_GEPHY_TX, 1 },
 364         { P_GEPHY_RX, 2 },
 365         { P_UBI32_PLL, 3 },
 366         { P_GPLL0, 4 },
 367 };
 368
 369 static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
 370         { .index = DT_XO },
 371         { .index = DT_UNIPHY_RX_CLK },
 372         { .index = DT_UNIPHY_TX_CLK },
 373         { .hw = &ubi32_pll.clkr.hw },
 374         { .hw = &gpll0.clkr.hw },
 375 };
 376
 377 static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
 378         { P_XO, 0 },
 379         { P_UNIPHY_RX, 1 },
 380         { P_UNIPHY_TX, 2 },
 381         { P_UBI32_PLL, 3 },
 382         { P_GPLL0, 4 },
 383 };
 384
 385 static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
 386         { .index = DT_XO },
 387         { .index = DT_UNIPHY_TX_CLK },
 388         { .index = DT_UNIPHY_RX_CLK },
 389         { .hw = &ubi32_pll.clkr.hw },
 390         { .hw = &gpll0.clkr.hw },
 391 };
 392
 393 static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
 394         { P_XO, 0 },
 395         { P_UNIPHY_TX, 1 },
 396         { P_UNIPHY_RX, 2 },
 397         { P_UBI32_PLL, 3 },
 398         { P_GPLL0, 4 },
 399 };
 400
 401 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
 402         { .index = DT_PCIE20_PHY0_PIPE_CLK },
 403         { .index = DT_XO },
 404 };
 405
 406 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 407         { P_PCIE20_PHY0_PIPE, 0 },
 408         { P_XO, 2 },
 409 };
 410
 411 static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
 412         { .index = DT_PCIE20_PHY1_PIPE_CLK },
 413         { .index = DT_XO },
 414 };
 415
 416 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 417         { P_PCIE20_PHY1_PIPE, 0 },
 418         { P_XO, 2 },
 419 };
 420
 421 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 422         { .index = DT_USB3_PHY0_CC_PIPE_CLK },
 423         { .index = DT_XO },
 424 };
 425
 426 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 427         { P_USB3PHY_0_PIPE, 0 },
 428         { P_XO, 2 },
 429 };
 430
 431 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
 432         F(24000000, P_XO, 1, 0, 0),
 433         F(100000000, P_GPLL0, 8, 0, 0),
 434         { }
 435 };
 436
 437 static struct clk_rcg2 adss_pwm_clk_src = {
 438         .cmd_rcgr = 0x1f008,
 439         .freq_tbl = ftbl_adss_pwm_clk_src,
 440         .hid_width = 5,
 441         .parent_map = gcc_xo_gpll0_map,
 442         .clkr.hw.init = &(struct clk_init_data) {
 443                 .name = "adss_pwm_clk_src",
 444                 .parent_data = gcc_xo_gpll0,
 445                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 446                 .ops = &clk_rcg2_ops,
 447         },
 448 };
 449
 450 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 451         F(50000000, P_GPLL0, 16, 0, 0),
 452         { }
 453 };
 454
 455 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 456         .cmd_rcgr = 0x0200c,
 457         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 458         .hid_width = 5,
 459         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 460         .clkr.hw.init = &(struct clk_init_data) {
 461                 .name = "blsp1_qup1_i2c_apps_clk_src",
 462                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 463                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 464                 .ops = &clk_rcg2_ops,
 465         },
 466 };
 467
 468 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 469         .cmd_rcgr = 0x03000,
 470         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 471         .hid_width = 5,
 472         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 473         .clkr.hw.init = &(struct clk_init_data) {
 474                 .name = "blsp1_qup2_i2c_apps_clk_src",
 475                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 476                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 477                 .ops = &clk_rcg2_ops,
 478         },
 479 };
 480
 481 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 482         .cmd_rcgr = 0x04000,
 483         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 484         .hid_width = 5,
 485         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 486         .clkr.hw.init = &(struct clk_init_data) {
 487                 .name = "blsp1_qup3_i2c_apps_clk_src",
 488                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 489                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 490                 .ops = &clk_rcg2_ops,
 491         },
 492 };
 493
 494 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 495         F(960000, P_XO, 10, 2, 5),
 496         F(4800000, P_XO, 5, 0, 0),
 497         F(9600000, P_XO, 2, 4, 5),
 498         F(16000000, P_GPLL0, 10, 1, 5),
 499         F(24000000, P_XO, 1, 0, 0),
 500         F(50000000, P_GPLL0, 16, 0, 0),
 501         { }
 502 };
 503
 504 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 505         .cmd_rcgr = 0x02024,
 506         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 507         .mnd_width = 8,
 508         .hid_width = 5,
 509         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 510         .clkr.hw.init = &(struct clk_init_data) {
 511                 .name = "blsp1_qup1_spi_apps_clk_src",
 512                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 513                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 514                 .ops = &clk_rcg2_ops,
 515         },
 516 };
 517
 518 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 519         .cmd_rcgr = 0x03014,
 520         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 521         .mnd_width = 8,
 522         .hid_width = 5,
 523         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 524         .clkr.hw.init = &(struct clk_init_data) {
 525                 .name = "blsp1_qup2_spi_apps_clk_src",
 526                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 527                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 528                 .ops = &clk_rcg2_ops,
 529         },
 530 };
 531
 532 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 533         .cmd_rcgr = 0x04014,
 534         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 535         .mnd_width = 8,
 536         .hid_width = 5,
 537         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 538         .clkr.hw.init = &(struct clk_init_data) {
 539                 .name = "blsp1_qup3_spi_apps_clk_src",
 540                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 541                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 542                 .ops = &clk_rcg2_ops,
 543         },
 544 };
 545
 546 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 547         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 548         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 549         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 550         F(24000000, P_XO, 1, 0, 0),
 551         F(25000000, P_GPLL0, 16, 1, 2),
 552         F(40000000, P_GPLL0, 1, 1, 20),
 553         F(46400000, P_GPLL0, 1, 29, 500),
 554         F(48000000, P_GPLL0, 1, 3, 50),
 555         F(51200000, P_GPLL0, 1, 8, 125),
 556         F(56000000, P_GPLL0, 1, 7, 100),
 557         F(58982400, P_GPLL0, 1, 1152, 15625),
 558         F(60000000, P_GPLL0, 1, 3, 40),
 559         F(64000000, P_GPLL0, 10, 4, 5),
 560         { }
 561 };
 562
 563 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 564         .cmd_rcgr = 0x02044,
 565         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 566         .mnd_width = 16,
 567         .hid_width = 5,
 568         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 569         .clkr.hw.init = &(struct clk_init_data) {
 570                 .name = "blsp1_uart1_apps_clk_src",
 571                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 572                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 573                 .ops = &clk_rcg2_ops,
 574         },
 575 };
 576
 577 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 578         .cmd_rcgr = 0x03034,
 579         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 580         .mnd_width = 16,
 581         .hid_width = 5,
 582         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 583         .clkr.hw.init = &(struct clk_init_data) {
 584                 .name = "blsp1_uart2_apps_clk_src",
 585                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 586                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 587                 .ops = &clk_rcg2_ops,
 588         },
 589 };
 590
 591 static const struct freq_tbl ftbl_crypto_clk_src[] = {
 592         F(160000000, P_GPLL0, 5, 0, 0),
 593         { }
 594 };
 595
 596 static struct clk_rcg2 crypto_clk_src = {
 597         .cmd_rcgr = 0x16004,
 598         .freq_tbl = ftbl_crypto_clk_src,
 599         .hid_width = 5,
 600         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 601         .clkr.hw.init = &(struct clk_init_data) {
 602                 .name = "crypto_clk_src",
 603                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 604                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 605                 .ops = &clk_rcg2_ops,
 606         },
 607 };
 608
 609 static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
 610         F(2500000, P_GEPHY_TX, 5, 0, 0),
 611         F(24000000, P_XO, 1, 0, 0),
 612         F(25000000, P_GEPHY_TX, 5, 0, 0),
 613         F(125000000, P_GEPHY_TX, 1, 0, 0),
 614         { }
 615 };
 616
 617 static struct clk_rcg2 gmac0_rx_clk_src = {
 618         .cmd_rcgr = 0x68020,
 619         .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
 620         .hid_width = 5,
 621         .freq_tbl = ftbl_gmac0_tx_clk_src,
 622         .clkr.hw.init = &(struct clk_init_data) {
 623                 .name = "gmac0_rx_clk_src",
 624                 .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
 625                 .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
 626                 .ops = &clk_rcg2_ops,
 627         },
 628 };
 629
 630 static struct clk_regmap_div gmac0_rx_div_clk_src = {
 631         .reg = 0x68420,
 632         .shift = 0,
 633         .width = 4,
 634         .clkr = {
 635                 .hw.init = &(struct clk_init_data) {
 636                         .name = "gmac0_rx_div_clk_src",
 637                         .parent_hws = (const struct clk_hw *[]) {
 638                                 &gmac0_rx_clk_src.clkr.hw,
 639                         },
 640                         .num_parents = 1,
 641                         .ops = &clk_regmap_div_ops,
 642                         .flags = CLK_SET_RATE_PARENT,
 643                 },
 644         },
 645 };
 646
 647 static struct clk_rcg2 gmac0_tx_clk_src = {
 648         .cmd_rcgr = 0x68028,
 649         .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
 650         .hid_width = 5,
 651         .freq_tbl = ftbl_gmac0_tx_clk_src,
 652         .clkr.hw.init = &(struct clk_init_data) {
 653                 .name = "gmac0_tx_clk_src",
 654                 .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
 655                 .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
 656                 .ops = &clk_rcg2_ops,
 657         },
 658 };
 659
 660 static struct clk_regmap_div gmac0_tx_div_clk_src = {
 661         .reg = 0x68424,
 662         .shift = 0,
 663         .width = 4,
 664         .clkr = {
 665                 .hw.init = &(struct clk_init_data) {
 666                         .name = "gmac0_tx_div_clk_src",
 667                         .parent_hws = (const struct clk_hw *[]) {
 668                                 &gmac0_tx_clk_src.clkr.hw,
 669                         },
 670                         .num_parents = 1,
 671                         .ops = &clk_regmap_div_ops,
 672                         .flags = CLK_SET_RATE_PARENT,
 673                 },
 674         },
 675 };
 676
 677 static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
 678         F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
 679         F(24000000, P_XO, 1, 0, 0),
 680         F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
 681         F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
 682         F(125000000, P_UNIPHY_RX, 1, 0, 0),
 683         F(312500000, P_UNIPHY_RX, 1, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 gmac1_rx_clk_src = {
 688         .cmd_rcgr = 0x68030,
 689         .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
 690         .hid_width = 5,
 691         .freq_tbl = ftbl_gmac1_rx_clk_src,
 692         .clkr.hw.init = &(struct clk_init_data) {
 693                 .name = "gmac1_rx_clk_src",
 694                 .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
 695                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_regmap_div gmac1_rx_div_clk_src = {
 701         .reg = 0x68430,
 702         .shift = 0,
 703         .width = 4,
 704         .clkr = {
 705                 .hw.init = &(struct clk_init_data) {
 706                         .name = "gmac1_rx_div_clk_src",
 707                         .parent_hws = (const struct clk_hw *[]) {
 708                                 &gmac1_rx_clk_src.clkr.hw,
 709                         },
 710                         .num_parents = 1,
 711                         .ops = &clk_regmap_div_ops,
 712                         .flags = CLK_SET_RATE_PARENT,
 713                 },
 714         },
 715 };
 716
 717 static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
 718         F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
 719         F(24000000, P_XO, 1, 0, 0),
 720         F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
 721         F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
 722         F(125000000, P_UNIPHY_TX, 1, 0, 0),
 723         F(312500000, P_UNIPHY_TX, 1, 0, 0),
 724         { }
 725 };
 726
 727 static struct clk_rcg2 gmac1_tx_clk_src = {
 728         .cmd_rcgr = 0x68038,
 729         .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
 730         .hid_width = 5,
 731         .freq_tbl = ftbl_gmac1_tx_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data) {
 733                 .name = "gmac1_tx_clk_src",
 734                 .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
 735                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct clk_regmap_div gmac1_tx_div_clk_src = {
 741         .reg = 0x68434,
 742         .shift = 0,
 743         .width = 4,
 744         .clkr = {
 745                 .hw.init = &(struct clk_init_data) {
 746                         .name = "gmac1_tx_div_clk_src",
 747                         .parent_hws = (const struct clk_hw *[]) {
 748                                 &gmac1_tx_clk_src.clkr.hw,
 749                         },
 750                         .num_parents = 1,
 751                         .ops = &clk_regmap_div_ops,
 752                         .flags = CLK_SET_RATE_PARENT,
 753                 },
 754         },
 755 };
 756
 757 static const struct freq_tbl ftbl_gmac_clk_src[] = {
 758         F(240000000, P_GPLL4, 5, 0, 0),
 759         { }
 760 };
 761
 762 static struct clk_rcg2 gmac_clk_src = {
 763         .cmd_rcgr = 0x68080,
 764         .parent_map = gcc_xo_gpll0_gpll4_map,
 765         .hid_width = 5,
 766         .freq_tbl = ftbl_gmac_clk_src,
 767         .clkr.hw.init = &(struct clk_init_data) {
 768                 .name = "gmac_clk_src",
 769                 .parent_data = gcc_xo_gpll0_gpll4,
 770                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 771                 .ops = &clk_rcg2_ops,
 772         },
 773 };
 774
 775 static const struct freq_tbl ftbl_gp_clk_src[] = {
 776         F(200000000, P_GPLL0, 4, 0, 0),
 777         { }
 778 };
 779
 780 static struct clk_rcg2 gp1_clk_src = {
 781         .cmd_rcgr = 0x08004,
 782         .freq_tbl = ftbl_gp_clk_src,
 783         .mnd_width = 8,
 784         .hid_width = 5,
 785         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 786         .clkr.hw.init = &(struct clk_init_data) {
 787                 .name = "gp1_clk_src",
 788                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 789                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 790                 .ops = &clk_rcg2_ops,
 791         },
 792 };
 793
 794 static struct clk_rcg2 gp2_clk_src = {
 795         .cmd_rcgr = 0x09004,
 796         .freq_tbl = ftbl_gp_clk_src,
 797         .mnd_width = 8,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 800         .clkr.hw.init = &(struct clk_init_data) {
 801                 .name = "gp2_clk_src",
 802                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 803                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 804                 .ops = &clk_rcg2_ops,
 805         },
 806 };
 807
 808 static struct clk_rcg2 gp3_clk_src = {
 809         .cmd_rcgr = 0x0a004,
 810         .freq_tbl = ftbl_gp_clk_src,
 811         .mnd_width = 8,
 812         .hid_width = 5,
 813         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 814         .clkr.hw.init = &(struct clk_init_data) {
 815                 .name = "gp3_clk_src",
 816                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 817                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
 823         F(133333334, P_GPLL0, 6, 0, 0),
 824         { }
 825 };
 826
 827 static struct clk_rcg2 lpass_axim_clk_src = {
 828         .cmd_rcgr = 0x2e028,
 829         .freq_tbl = ftbl_lpass_axim_clk_src,
 830         .hid_width = 5,
 831         .parent_map = gcc_xo_gpll0_map,
 832         .clkr.hw.init = &(struct clk_init_data) {
 833                 .name = "lpass_axim_clk_src",
 834                 .parent_data = gcc_xo_gpll0,
 835                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 836                 .ops = &clk_rcg2_ops,
 837         },
 838 };
 839
 840 static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
 841         F(66666667, P_GPLL0, 12, 0, 0),
 842         { }
 843 };
 844
 845 static struct clk_rcg2 lpass_sway_clk_src = {
 846         .cmd_rcgr = 0x2e040,
 847         .freq_tbl = ftbl_lpass_sway_clk_src,
 848         .hid_width = 5,
 849         .parent_map = gcc_xo_gpll0_map,
 850         .clkr.hw.init = &(struct clk_init_data) {
 851                 .name = "lpass_sway_clk_src",
 852                 .parent_data = gcc_xo_gpll0,
 853                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 854                 .ops = &clk_rcg2_ops,
 855         },
 856 };
 857
 858 static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
 859         F(2000000, P_XO, 12, 0, 0),
 860 };
 861
 862 static struct clk_rcg2 pcie0_aux_clk_src = {
 863         .cmd_rcgr = 0x75020,
 864         .freq_tbl = ftbl_pcie0_aux_clk_src,
 865         .mnd_width = 16,
 866         .hid_width = 5,
 867         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
 868         .clkr.hw.init = &(struct clk_init_data) {
 869                 .name = "pcie0_aux_clk_src",
 870                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
 871                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
 872                 .ops = &clk_rcg2_ops,
 873         },
 874 };
 875
 876 static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
 877         F(240000000, P_GPLL4, 5, 0, 0),
 878         { }
 879 };
 880
 881 static struct clk_rcg2 pcie0_axi_clk_src = {
 882         .cmd_rcgr = 0x75050,
 883         .freq_tbl = ftbl_pcie0_axi_clk_src,
 884         .hid_width = 5,
 885         .parent_map = gcc_xo_gpll0_gpll4_map,
 886         .clkr.hw.init = &(struct clk_init_data) {
 887                 .name = "pcie0_axi_clk_src",
 888                 .parent_data = gcc_xo_gpll0_gpll4,
 889                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 890                 .ops = &clk_rcg2_ops,
 891         },
 892 };
 893
 894 static struct clk_rcg2 pcie1_aux_clk_src = {
 895         .cmd_rcgr = 0x76020,
 896         .freq_tbl = ftbl_pcie0_aux_clk_src,
 897         .mnd_width = 16,
 898         .hid_width = 5,
 899         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
 900         .clkr.hw.init = &(struct clk_init_data) {
 901                 .name = "pcie1_aux_clk_src",
 902                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
 903                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
 904                 .ops = &clk_rcg2_ops,
 905         },
 906 };
 907
 908 static struct clk_rcg2 pcie1_axi_clk_src = {
 909         .cmd_rcgr = 0x76050,
 910         .freq_tbl = ftbl_gp_clk_src,
 911         .hid_width = 5,
 912         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 913         .clkr.hw.init = &(struct clk_init_data) {
 914                 .name = "pcie1_axi_clk_src",
 915                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 916                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 917                 .ops = &clk_rcg2_ops,
 918         },
 919 };
 920
 921 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 922         .reg = 0x7501c,
 923         .shift = 8,
 924         .width = 2,
 925         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 926         .clkr = {
 927                 .hw.init = &(struct clk_init_data) {
 928                         .name = "pcie0_pipe_clk_src",
 929                         .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
 930                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
 931                         .ops = &clk_regmap_mux_closest_ops,
 932                         .flags = CLK_SET_RATE_PARENT,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_regmap_mux pcie1_pipe_clk_src = {
 938         .reg = 0x7601c,
 939         .shift = 8,
 940         .width = 2,
 941         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
 942                 .hw.init = &(struct clk_init_data) {
 943                         .name = "pcie1_pipe_clk_src",
 944                         .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
 945                         .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
 946                         .ops = &clk_regmap_mux_closest_ops,
 947                         .flags = CLK_SET_RATE_PARENT,
 948                 },
 949         },
 950 };
 951
 952 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 953         F(100000000, P_GPLL0, 8, 0, 0),
 954         { }
 955 };
 956
 957 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 958         .cmd_rcgr = 0x27000,
 959         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 960         .hid_width = 5,
 961         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 962         .clkr.hw.init = &(struct clk_init_data) {
 963                 .name = "pcnoc_bfdcd_clk_src",
 964                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 965                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 966                 .ops = &clk_rcg2_ops,
 967         },
 968 };
 969
 970 static struct clk_fixed_factor pcnoc_clk_src = {
 971         .mult = 1,
 972         .div = 1,
 973         .hw.init = &(struct clk_init_data) {
 974                 .name = "pcnoc_clk_src",
 975                 .parent_hws = (const struct clk_hw *[]) {
 976                         &pcnoc_bfdcd_clk_src.clkr.hw,
 977                 },
 978                 .num_parents = 1,
 979                 .ops = &clk_fixed_factor_ops,
 980                 .flags = CLK_SET_RATE_PARENT,
 981         },
 982 };
 983
 984 static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 985         F(240000000, P_GPLL4, 5, 0, 0),
 986         { }
 987 };
 988
 989 static struct clk_rcg2 qdss_at_clk_src = {
 990         .cmd_rcgr = 0x2900c,
 991         .freq_tbl = ftbl_qdss_at_clk_src,
 992         .hid_width = 5,
 993         .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
 994         .clkr.hw.init = &(struct clk_init_data) {
 995                 .name = "qdss_at_clk_src",
 996                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
 997                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
 998                 .ops = &clk_rcg2_ops,
 999         },
1000 };
1001
1002 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1003         F(200000000, P_GPLL0, 4, 0, 0),
1004         { }
1005 };
1006
1007 static struct clk_rcg2 qdss_stm_clk_src = {
1008         .cmd_rcgr = 0x2902c,
1009         .freq_tbl = ftbl_qdss_stm_clk_src,
1010         .hid_width = 5,
1011         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1012         .clkr.hw.init = &(struct clk_init_data) {
1013                 .name = "qdss_stm_clk_src",
1014                 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1015                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1016                 .ops = &clk_rcg2_ops,
1017         },
1018 };
1019
1020 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1021         F(266666667, P_GPLL0, 3, 0, 0),
1022         { }
1023 };
1024
1025 static struct clk_rcg2 qdss_traceclkin_clk_src = {
1026         .cmd_rcgr = 0x29048,
1027         .freq_tbl = ftbl_qdss_traceclkin_clk_src,
1028         .hid_width = 5,
1029         .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1030         .clkr.hw.init = &(struct clk_init_data) {
1031                 .name = "qdss_traceclkin_clk_src",
1032                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1033                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1034                 .ops = &clk_rcg2_ops,
1035         },
1036 };
1037
1038 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
1039         F(600000000, P_GPLL4, 2, 0, 0),
1040         { }
1041 };
1042
1043 static struct clk_rcg2 qdss_tsctr_clk_src = {
1044         .cmd_rcgr = 0x29064,
1045         .freq_tbl = ftbl_qdss_tsctr_clk_src,
1046         .hid_width = 5,
1047         .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1048         .clkr.hw.init = &(struct clk_init_data) {
1049                 .name = "qdss_tsctr_clk_src",
1050                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1051                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1052                 .ops = &clk_rcg2_ops,
1053         },
1054 };
1055
1056 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
1057         .mult = 1,
1058         .div = 2,
1059         .hw.init = &(struct clk_init_data) {
1060                 .name = "qdss_tsctr_div2_clk_src",
1061                 .parent_hws = (const struct clk_hw *[]) {
1062                         &qdss_tsctr_clk_src.clkr.hw,
1063                 },
1064                 .num_parents = 1,
1065                 .flags = CLK_SET_RATE_PARENT,
1066                 .ops = &clk_fixed_factor_ops,
1067         },
1068 };
1069
1070 static struct clk_fixed_factor qdss_dap_sync_clk_src = {
1071         .mult = 1,
1072         .div = 4,
1073         .hw.init = &(struct clk_init_data) {
1074                 .name = "qdss_dap_sync_clk_src",
1075                 .parent_hws = (const struct clk_hw *[]) {
1076                         &qdss_tsctr_clk_src.clkr.hw,
1077                 },
1078                 .num_parents = 1,
1079                 .ops = &clk_fixed_factor_ops,
1080         },
1081 };
1082
1083 static struct clk_fixed_factor eud_at_clk_src = {
1084         .mult = 1,
1085         .div = 6,
1086         .hw.init = &(struct clk_init_data) {
1087                 .name = "eud_at_clk_src",
1088                 .parent_hws = (const struct clk_hw *[]) {
1089                         &qdss_at_clk_src.clkr.hw,
1090                 },
1091                 .num_parents = 1,
1092                 .ops = &clk_fixed_factor_ops,
1093                 .flags = CLK_SET_RATE_PARENT,
1094         },
1095 };
1096
1097 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
1098         F(24000000, P_XO, 1, 0, 0),
1099         F(100000000, P_GPLL0, 8, 0, 0),
1100         F(200000000, P_GPLL0, 4, 0, 0),
1101         F(320000000, P_GPLL0, 2.5, 0, 0),
1102 };
1103
1104 static struct clk_rcg2 qpic_io_macro_clk_src = {
1105         .cmd_rcgr = 0x57010,
1106         .freq_tbl = ftbl_qpic_io_macro_clk_src,
1107         .hid_width = 5,
1108         .parent_map = gcc_xo_gpll0_gpll2_map,
1109         .clkr.hw.init = &(struct clk_init_data) {
1110                 .name = "qpic_io_macro_clk_src",
1111                 .parent_data = gcc_xo_gpll0_gpll2,
1112                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1113                 .ops = &clk_rcg2_ops,
1114         },
1115 };
1116
1117 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1118         F(143713, P_XO, 1, 1, 167),
1119         F(400000, P_XO, 1, 1, 60),
1120         F(24000000, P_XO, 1, 0, 0),
1121         F(48000000, P_GPLL2, 12, 1, 2),
1122         F(96000000, P_GPLL2, 12, 0, 0),
1123         F(177777778, P_GPLL0, 1, 2, 9),
1124         F(192000000, P_GPLL2, 6, 0, 0),
1125         F(200000000, P_GPLL0, 4, 0, 0),
1126         { }
1127 };
1128
1129 static struct clk_rcg2 sdcc1_apps_clk_src = {
1130         .cmd_rcgr = 0x42004,
1131         .freq_tbl = ftbl_sdcc1_apps_clk_src,
1132         .mnd_width = 8,
1133         .hid_width = 5,
1134         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1135         .clkr.hw.init = &(struct clk_init_data) {
1136                 .name = "sdcc1_apps_clk_src",
1137                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1138                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1139                 .ops = &clk_rcg2_floor_ops,
1140         },
1141 };
1142
1143 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1144         F(266666667, P_GPLL0, 3, 0, 0),
1145         { }
1146 };
1147
1148 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1149         .cmd_rcgr = 0x26004,
1150         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1151         .hid_width = 5,
1152         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1153         .clkr.hw.init = &(struct clk_init_data) {
1154                 .name = "system_noc_bfdcd_clk_src",
1155                 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1156                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1157                 .ops = &clk_rcg2_ops,
1158         },
1159 };
1160
1161 static struct clk_fixed_factor system_noc_clk_src = {
1162         .mult = 1,
1163         .div = 1,
1164         .hw.init = &(struct clk_init_data) {
1165                 .name = "system_noc_clk_src",
1166                 .parent_hws = (const struct clk_hw *[]) {
1167                         &system_noc_bfdcd_clk_src.clkr.hw,
1168                 },
1169                 .num_parents = 1,
1170                 .ops = &clk_fixed_factor_ops,
1171                 .flags = CLK_SET_RATE_PARENT,
1172         },
1173 };
1174
1175 static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
1176         F(400000000, P_GPLL0, 2, 0, 0),
1177         { }
1178 };
1179
1180 static struct clk_rcg2 ubi0_axi_clk_src = {
1181         .cmd_rcgr = 0x68088,
1182         .freq_tbl = ftbl_apss_axi_clk_src,
1183         .hid_width = 5,
1184         .parent_map = gcc_xo_gpll0_gpll2_map,
1185         .clkr.hw.init = &(struct clk_init_data) {
1186                 .name = "ubi0_axi_clk_src",
1187                 .parent_data = gcc_xo_gpll0_gpll2,
1188                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1189                 .ops = &clk_rcg2_ops,
1190                 .flags = CLK_SET_RATE_PARENT,
1191         },
1192 };
1193
1194 static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
1195         F(850000000, P_UBI32_PLL, 1, 0, 0),
1196         F(1000000000, P_UBI32_PLL, 1, 0, 0),
1197 };
1198
1199 static struct clk_rcg2 ubi0_core_clk_src = {
1200         .cmd_rcgr = 0x68100,
1201         .freq_tbl = ftbl_ubi0_core_clk_src,
1202         .hid_width = 5,
1203         .parent_map = gcc_xo_ubi32_gpll0_map,
1204         .clkr.hw.init = &(struct clk_init_data) {
1205                 .name = "ubi0_core_clk_src",
1206                 .parent_data = gcc_xo_ubi32_gpll0,
1207                 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
1208                 .ops = &clk_rcg2_ops,
1209                 .flags = CLK_SET_RATE_PARENT,
1210         },
1211 };
1212
1213 static struct clk_rcg2 usb0_aux_clk_src = {
1214         .cmd_rcgr = 0x3e05c,
1215         .freq_tbl = ftbl_pcie0_aux_clk_src,
1216         .mnd_width = 16,
1217         .hid_width = 5,
1218         .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1219         .clkr.hw.init = &(struct clk_init_data) {
1220                 .name = "usb0_aux_clk_src",
1221                 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1222                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1223                 .ops = &clk_rcg2_ops,
1224         },
1225 };
1226
1227 static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
1228         F(25000000, P_GPLL0, 16, 1, 2),
1229         { }
1230 };
1231
1232 static struct clk_rcg2 usb0_lfps_clk_src = {
1233         .cmd_rcgr = 0x3e090,
1234         .freq_tbl = ftbl_usb0_lfps_clk_src,
1235         .mnd_width = 8,
1236         .hid_width = 5,
1237         .parent_map = gcc_xo_gpll0_map,
1238         .clkr.hw.init = &(struct clk_init_data) {
1239                 .name = "usb0_lfps_clk_src",
1240                 .parent_data = gcc_xo_gpll0,
1241                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1242                 .ops = &clk_rcg2_ops,
1243         },
1244 };
1245
1246 static struct clk_rcg2 usb0_master_clk_src = {
1247         .cmd_rcgr = 0x3e00c,
1248         .freq_tbl = ftbl_gp_clk_src,
1249         .mnd_width = 8,
1250         .hid_width = 5,
1251         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1252         .clkr.hw.init = &(struct clk_init_data) {
1253                 .name = "usb0_master_clk_src",
1254                 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1255                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1256                 .ops = &clk_rcg2_ops,
1257         },
1258 };
1259
1260 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1261         F(60000000, P_GPLL4, 10, 1, 2),
1262         { }
1263 };
1264
1265 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1266         .cmd_rcgr = 0x3e020,
1267         .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1268         .mnd_width = 8,
1269         .hid_width = 5,
1270         .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
1271         .clkr.hw.init = &(struct clk_init_data) {
1272                 .name = "usb0_mock_utmi_clk_src",
1273                 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1274                 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1275                 .ops = &clk_rcg2_ops,
1276         },
1277 };
1278
1279 static struct clk_regmap_mux usb0_pipe_clk_src = {
1280         .reg = 0x3e048,
1281         .shift = 8,
1282         .width = 2,
1283         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1284         .clkr = {
1285                 .hw.init = &(struct clk_init_data) {
1286                         .name = "usb0_pipe_clk_src",
1287                         .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1288                         .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1289                         .ops = &clk_regmap_mux_closest_ops,
1290                         .flags = CLK_SET_RATE_PARENT,
1291                 },
1292         },
1293 };
1294
1295 static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
1296         F(400000000, P_GPLL0, 2, 0, 0),
1297         { }
1298 };
1299
1300 static struct clk_rcg2 q6_axi_clk_src = {
1301         .cmd_rcgr = 0x59120,
1302         .freq_tbl = ftbl_q6_axi_clk_src,
1303         .hid_width = 5,
1304         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
1305         .clkr.hw.init = &(struct clk_init_data) {
1306                 .name = "q6_axi_clk_src",
1307                 .parent_data = gcc_xo_gpll0_gpll2_gpll4,
1308                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
1309                 .ops = &clk_rcg2_ops,
1310         },
1311 };
1312
1313 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
1314         F(133333333, P_GPLL0, 6, 0, 0),
1315         { }
1316 };
1317
1318 static struct clk_rcg2 wcss_ahb_clk_src = {
1319         .cmd_rcgr = 0x59020,
1320         .freq_tbl = ftbl_wcss_ahb_clk_src,
1321         .hid_width = 5,
1322         .parent_map = gcc_xo_gpll0_map,
1323         .clkr.hw.init = &(struct clk_init_data) {
1324                 .name = "wcss_ahb_clk_src",
1325                 .parent_data = gcc_xo_gpll0,
1326                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1327                 .ops = &clk_rcg2_ops,
1328         },
1329 };
1330
1331 static struct clk_branch gcc_sleep_clk_src = {
1332         .halt_reg = 0x30000,
1333         .clkr = {
1334                 .enable_reg = 0x30000,
1335                 .enable_mask = BIT(1),
1336                 .hw.init = &(struct clk_init_data) {
1337                         .name = "gcc_sleep_clk_src",
1338                         .parent_data = gcc_sleep_clk_data,
1339                         .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
1340                         .ops = &clk_branch2_ops,
1341                 },
1342         },
1343 };
1344
1345 static struct clk_branch gcc_xo_clk_src = {
1346         .halt_reg = 0x30018,
1347         .clkr = {
1348                 .enable_reg = 0x30018,
1349                 .enable_mask = BIT(1),
1350                 .hw.init = &(struct clk_init_data) {
1351                         .name = "gcc_xo_clk_src",
1352                         .parent_data = gcc_xo_data,
1353                         .num_parents = ARRAY_SIZE(gcc_xo_data),
1354                         .flags = CLK_SET_RATE_PARENT,
1355                         .ops = &clk_branch2_ops,
1356                 },
1357         },
1358 };
1359
1360 static struct clk_branch gcc_xo_clk = {
1361         .halt_reg = 0x30030,
1362         .clkr = {
1363                 .enable_reg = 0x30030,
1364                 .enable_mask = BIT(0),
1365                 .hw.init = &(struct clk_init_data) {
1366                         .name = "gcc_xo_clk",
1367                         .parent_hws = (const struct clk_hw *[]) {
1368                                 &gcc_xo_clk_src.clkr.hw,
1369                         },
1370                         .num_parents = 1,
1371                         .flags = CLK_SET_RATE_PARENT,
1372                         .ops = &clk_branch2_ops,
1373                 },
1374         },
1375 };
1376
1377 static struct clk_branch gcc_adss_pwm_clk = {
1378         .halt_reg = 0x1f020,
1379         .clkr = {
1380                 .enable_reg = 0x1f020,
1381                 .enable_mask = BIT(0),
1382                 .hw.init = &(struct clk_init_data) {
1383                         .name = "gcc_adss_pwm_clk",
1384                         .parent_hws = (const struct clk_hw *[]) {
1385                                 &adss_pwm_clk_src.clkr.hw,
1386                         },
1387                         .num_parents = 1,
1388                         .flags = CLK_SET_RATE_PARENT,
1389                         .ops = &clk_branch2_ops,
1390                 },
1391         },
1392 };
1393
1394 static struct clk_branch gcc_blsp1_ahb_clk = {
1395         .halt_reg = 0x01008,
1396         .halt_check = BRANCH_HALT_VOTED,
1397         .clkr = {
1398                 .enable_reg = 0x0b004,
1399                 .enable_mask = BIT(10),
1400                 .hw.init = &(struct clk_init_data) {
1401                         .name = "gcc_blsp1_ahb_clk",
1402                         .parent_hws = (const struct clk_hw *[]) {
1403                                 &pcnoc_clk_src.hw,
1404                         },
1405                         .num_parents = 1,
1406                         .flags = CLK_SET_RATE_PARENT,
1407                         .ops = &clk_branch2_ops,
1408                 },
1409         },
1410 };
1411
1412 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1413         .halt_reg = 0x02008,
1414         .clkr = {
1415                 .enable_reg = 0x02008,
1416                 .enable_mask = BIT(0),
1417                 .hw.init = &(struct clk_init_data) {
1418                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1419                         .parent_hws = (const struct clk_hw *[]) {
1420                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1421                         },
1422                         .num_parents = 1,
1423                         .flags = CLK_SET_RATE_PARENT,
1424                         .ops = &clk_branch2_ops,
1425                 },
1426         },
1427 };
1428
1429 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1430         .halt_reg = 0x02004,
1431         .clkr = {
1432                 .enable_reg = 0x02004,
1433                 .enable_mask = BIT(0),
1434                 .hw.init = &(struct clk_init_data) {
1435                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1436                         .parent_hws = (const struct clk_hw *[]) {
1437                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1438                         },
1439                         .num_parents = 1,
1440                         .flags = CLK_SET_RATE_PARENT,
1441                         .ops = &clk_branch2_ops,
1442                 },
1443         },
1444 };
1445
1446 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1447         .halt_reg = 0x03010,
1448         .clkr = {
1449                 .enable_reg = 0x03010,
1450                 .enable_mask = BIT(0),
1451                 .hw.init = &(struct clk_init_data) {
1452                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1453                         .parent_hws = (const struct clk_hw *[]) {
1454                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1455                         },
1456                         .num_parents = 1,
1457                         .flags = CLK_SET_RATE_PARENT,
1458                         .ops = &clk_branch2_ops,
1459                 },
1460         },
1461 };
1462
1463 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1464         .halt_reg = 0x0300c,
1465         .clkr = {
1466                 .enable_reg = 0x0300c,
1467                 .enable_mask = BIT(0),
1468                 .hw.init = &(struct clk_init_data) {
1469                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1470                         .parent_hws = (const struct clk_hw *[]) {
1471                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1472                         },
1473                         .num_parents = 1,
1474                         .flags = CLK_SET_RATE_PARENT,
1475                         .ops = &clk_branch2_ops,
1476                 },
1477         },
1478 };
1479
1480 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1481         .halt_reg = 0x04010,
1482         .clkr = {
1483                 .enable_reg = 0x04010,
1484                 .enable_mask = BIT(0),
1485                 .hw.init = &(struct clk_init_data) {
1486                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1487                         .parent_hws = (const struct clk_hw *[]) {
1488                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1489                         },
1490                         .num_parents = 1,
1491                         .flags = CLK_SET_RATE_PARENT,
1492                         .ops = &clk_branch2_ops,
1493                 },
1494         },
1495 };
1496
1497 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1498         .halt_reg = 0x0400c,
1499         .clkr = {
1500                 .enable_reg = 0x0400c,
1501                 .enable_mask = BIT(0),
1502                 .hw.init = &(struct clk_init_data) {
1503                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1504                         .parent_hws = (const struct clk_hw *[]) {
1505                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1506                         },
1507                         .num_parents = 1,
1508                         .flags = CLK_SET_RATE_PARENT,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1515         .halt_reg = 0x0203c,
1516         .clkr = {
1517                 .enable_reg = 0x0203c,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data) {
1520                         .name = "gcc_blsp1_uart1_apps_clk",
1521                         .parent_hws = (const struct clk_hw *[]) {
1522                                 &blsp1_uart1_apps_clk_src.clkr.hw,
1523                         },
1524                         .num_parents = 1,
1525                         .flags = CLK_SET_RATE_PARENT,
1526                         .ops = &clk_branch2_ops,
1527                 },
1528         },
1529 };
1530
1531 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1532         .halt_reg = 0x0302c,
1533         .clkr = {
1534                 .enable_reg = 0x0302c,
1535                 .enable_mask = BIT(0),
1536                 .hw.init = &(struct clk_init_data) {
1537                         .name = "gcc_blsp1_uart2_apps_clk",
1538                         .parent_hws = (const struct clk_hw *[]) {
1539                                 &blsp1_uart2_apps_clk_src.clkr.hw,
1540                         },
1541                         .num_parents = 1,
1542                         .flags = CLK_SET_RATE_PARENT,
1543                         .ops = &clk_branch2_ops,
1544                 },
1545         },
1546 };
1547
1548 static struct clk_branch gcc_btss_lpo_clk = {
1549         .halt_reg = 0x1c004,
1550         .clkr = {
1551                 .enable_reg = 0x1c004,
1552                 .enable_mask = BIT(0),
1553                 .hw.init = &(struct clk_init_data) {
1554                         .name = "gcc_btss_lpo_clk",
1555                         .ops = &clk_branch2_ops,
1556                 },
1557         },
1558 };
1559
1560 static struct clk_branch gcc_cmn_blk_ahb_clk = {
1561         .halt_reg = 0x56308,
1562         .clkr = {
1563                 .enable_reg = 0x56308,
1564                 .enable_mask = BIT(0),
1565                 .hw.init = &(struct clk_init_data) {
1566                         .name = "gcc_cmn_blk_ahb_clk",
1567                         .parent_hws = (const struct clk_hw *[]) {
1568                                 &pcnoc_clk_src.hw,
1569                         },
1570                         .num_parents = 1,
1571                         .flags = CLK_SET_RATE_PARENT,
1572                         .ops = &clk_branch2_ops,
1573                 },
1574         },
1575 };
1576
1577 static struct clk_branch gcc_cmn_blk_sys_clk = {
1578         .halt_reg = 0x5630c,
1579         .clkr = {
1580                 .enable_reg = 0x5630c,
1581                 .enable_mask = BIT(0),
1582                 .hw.init = &(struct clk_init_data) {
1583                         .name = "gcc_cmn_blk_sys_clk",
1584                         .parent_hws = (const struct clk_hw *[]) {
1585                                 &gcc_xo_clk_src.clkr.hw,
1586                         },
1587                         .num_parents = 1,
1588                         .flags = CLK_SET_RATE_PARENT,
1589                         .ops = &clk_branch2_ops,
1590                 },
1591         },
1592 };
1593
1594 static struct clk_branch gcc_crypto_ahb_clk = {
1595         .halt_reg = 0x16024,
1596         .halt_check = BRANCH_HALT_VOTED,
1597         .clkr = {
1598                 .enable_reg = 0x0b004,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data) {
1601                         .name = "gcc_crypto_ahb_clk",
1602                         .parent_hws = (const struct clk_hw *[]) {
1603                                 &pcnoc_clk_src.hw,
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch gcc_crypto_axi_clk = {
1613         .halt_reg = 0x16020,
1614         .halt_check = BRANCH_HALT_VOTED,
1615         .clkr = {
1616                 .enable_reg = 0x0b004,
1617                 .enable_mask = BIT(1),
1618                 .hw.init = &(struct clk_init_data) {
1619                         .name = "gcc_crypto_axi_clk",
1620                         .parent_hws = (const struct clk_hw *[]) {
1621                                 &pcnoc_clk_src.hw,
1622                         },
1623                         .num_parents = 1,
1624                         .flags = CLK_SET_RATE_PARENT,
1625                         .ops = &clk_branch2_ops,
1626                 },
1627         },
1628 };
1629
1630 static struct clk_branch gcc_crypto_clk = {
1631         .halt_reg = 0x1601c,
1632         .halt_check = BRANCH_HALT_VOTED,
1633         .clkr = {
1634                 .enable_reg = 0x0b004,
1635                 .enable_mask = BIT(2),
1636                 .hw.init = &(struct clk_init_data) {
1637                         .name = "gcc_crypto_clk",
1638                         .parent_hws = (const struct clk_hw *[]) {
1639                                 &crypto_clk_src.clkr.hw,
1640                         },
1641                         .num_parents = 1,
1642                         .flags = CLK_SET_RATE_PARENT,
1643                         .ops = &clk_branch2_ops,
1644                 },
1645         },
1646 };
1647
1648 static struct clk_branch gcc_dcc_clk = {
1649         .halt_reg = 0x77004,
1650         .clkr = {
1651                 .enable_reg = 0x77004,
1652                 .enable_mask = BIT(0),
1653                 .hw.init = &(struct clk_init_data) {
1654                         .name = "gcc_dcc_clk",
1655                         .parent_hws = (const struct clk_hw *[]) {
1656                                 &pcnoc_clk_src.hw,
1657                         },
1658                         .num_parents = 1,
1659                         .flags = CLK_SET_RATE_PARENT,
1660                         .ops = &clk_branch2_ops,
1661                 },
1662         },
1663 };
1664
1665 static struct clk_branch gcc_gephy_rx_clk = {
1666         .halt_reg = 0x56010,
1667         .halt_check = BRANCH_HALT_DELAY,
1668         .clkr = {
1669                 .enable_reg = 0x56010,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data) {
1672                         .name = "gcc_gephy_rx_clk",
1673                         .parent_hws = (const struct clk_hw *[]) {
1674                                 &gmac0_rx_div_clk_src.clkr.hw,
1675                         },
1676                         .num_parents = 1,
1677                         .ops = &clk_branch2_ops,
1678                         .flags = CLK_SET_RATE_PARENT,
1679                 },
1680         },
1681 };
1682
1683 static struct clk_branch gcc_gephy_tx_clk = {
1684         .halt_reg = 0x56014,
1685         .halt_check = BRANCH_HALT_DELAY,
1686         .clkr = {
1687                 .enable_reg = 0x56014,
1688                 .enable_mask = BIT(0),
1689                 .hw.init = &(struct clk_init_data) {
1690                         .name = "gcc_gephy_tx_clk",
1691                         .parent_hws = (const struct clk_hw *[]) {
1692                                 &gmac0_tx_div_clk_src.clkr.hw,
1693                         },
1694                         .num_parents = 1,
1695                         .ops = &clk_branch2_ops,
1696                         .flags = CLK_SET_RATE_PARENT,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_gmac0_cfg_clk = {
1702         .halt_reg = 0x68304,
1703         .clkr = {
1704                 .enable_reg = 0x68304,
1705                 .enable_mask = BIT(0),
1706                 .hw.init = &(struct clk_init_data) {
1707                         .name = "gcc_gmac0_cfg_clk",
1708                         .parent_hws = (const struct clk_hw *[]) {
1709                                 &gmac_clk_src.clkr.hw,
1710                         },
1711                         .num_parents = 1,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                         .ops = &clk_branch2_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_gmac0_ptp_clk = {
1719         .halt_reg = 0x68300,
1720         .clkr = {
1721                 .enable_reg = 0x68300,
1722                 .enable_mask = BIT(0),
1723                 .hw.init = &(struct clk_init_data) {
1724                         .name = "gcc_gmac0_ptp_clk",
1725                         .parent_hws = (const struct clk_hw *[]) {
1726                                 &gmac_clk_src.clkr.hw,
1727                         },
1728                         .num_parents = 1,
1729                         .flags = CLK_SET_RATE_PARENT,
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_gmac0_rx_clk = {
1736         .halt_reg = 0x68240,
1737         .clkr = {
1738                 .enable_reg = 0x68240,
1739                 .enable_mask = BIT(0),
1740                 .hw.init = &(struct clk_init_data) {
1741                         .name = "gcc_gmac0_rx_clk",
1742                         .parent_hws = (const struct clk_hw *[]) {
1743                                 &gmac0_rx_div_clk_src.clkr.hw,
1744                         },
1745                         .num_parents = 1,
1746                         .ops = &clk_branch2_ops,
1747                         .flags = CLK_SET_RATE_PARENT,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch gcc_gmac0_sys_clk = {
1753         .halt_reg = 0x68190,
1754         .halt_check = BRANCH_HALT_DELAY,
1755         .halt_bit = 31,
1756         .clkr = {
1757                 .enable_reg = 0x683190,
1758                 .enable_mask = BIT(0),
1759                 .hw.init = &(struct clk_init_data) {
1760                         .name = "gcc_gmac0_sys_clk",
1761                         .parent_hws = (const struct clk_hw *[]) {
1762                                 &gmac_clk_src.clkr.hw,
1763                         },
1764                         .num_parents = 1,
1765                         .flags = CLK_SET_RATE_PARENT,
1766                         .ops = &clk_branch2_ops,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_branch gcc_gmac0_tx_clk = {
1772         .halt_reg = 0x68244,
1773         .clkr = {
1774                 .enable_reg = 0x68244,
1775                 .enable_mask = BIT(0),
1776                 .hw.init = &(struct clk_init_data) {
1777                         .name = "gcc_gmac0_tx_clk",
1778                         .parent_hws = (const struct clk_hw *[]) {
1779                                 &gmac0_tx_div_clk_src.clkr.hw,
1780                         },
1781                         .num_parents = 1,
1782                         .ops = &clk_branch2_ops,
1783                         .flags = CLK_SET_RATE_PARENT,
1784                 },
1785         },
1786 };
1787
1788 static struct clk_branch gcc_gmac1_cfg_clk = {
1789         .halt_reg = 0x68324,
1790         .clkr = {
1791                 .enable_reg = 0x68324,
1792                 .enable_mask = BIT(0),
1793                 .hw.init = &(struct clk_init_data) {
1794                         .name = "gcc_gmac1_cfg_clk",
1795                         .parent_hws = (const struct clk_hw *[]) {
1796                                 &gmac_clk_src.clkr.hw,
1797                         },
1798                         .num_parents = 1,
1799                         .flags = CLK_SET_RATE_PARENT,
1800                         .ops = &clk_branch2_ops,
1801                 },
1802         },
1803 };
1804
1805 static struct clk_branch gcc_gmac1_ptp_clk = {
1806         .halt_reg = 0x68320,
1807         .clkr = {
1808                 .enable_reg = 0x68320,
1809                 .enable_mask = BIT(0),
1810                 .hw.init = &(struct clk_init_data) {
1811                         .name = "gcc_gmac1_ptp_clk",
1812                         .parent_hws = (const struct clk_hw *[]) {
1813                                 &gmac_clk_src.clkr.hw,
1814                         },
1815                         .num_parents = 1,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                         .ops = &clk_branch2_ops,
1818                 },
1819         },
1820 };
1821
1822 static struct clk_branch gcc_gmac1_rx_clk = {
1823         .halt_reg = 0x68248,
1824         .clkr = {
1825                 .enable_reg = 0x68248,
1826                 .enable_mask = BIT(0),
1827                 .hw.init = &(struct clk_init_data) {
1828                         .name = "gcc_gmac1_rx_clk",
1829                         .parent_hws = (const struct clk_hw *[]) {
1830                                 &gmac1_rx_div_clk_src.clkr.hw,
1831                         },
1832                         .num_parents = 1,
1833                         .ops = &clk_branch2_ops,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                 },
1836         },
1837 };
1838
1839 static struct clk_branch gcc_gmac1_sys_clk = {
1840         .halt_reg = 0x68310,
1841         .clkr = {
1842                 .enable_reg = 0x68310,
1843                 .enable_mask = BIT(0),
1844                 .hw.init = &(struct clk_init_data) {
1845                         .name = "gcc_gmac1_sys_clk",
1846                         .parent_hws = (const struct clk_hw *[]) {
1847                                 &gmac_clk_src.clkr.hw,
1848                         },
1849                         .num_parents = 1,
1850                         .flags = CLK_SET_RATE_PARENT,
1851                         .ops = &clk_branch2_ops,
1852                 },
1853         },
1854 };
1855
1856 static struct clk_branch gcc_gmac1_tx_clk = {
1857         .halt_reg = 0x6824c,
1858         .clkr = {
1859                 .enable_reg = 0x6824c,
1860                 .enable_mask = BIT(0),
1861                 .hw.init = &(struct clk_init_data) {
1862                         .name = "gcc_gmac1_tx_clk",
1863                         .parent_hws = (const struct clk_hw *[]) {
1864                                 &gmac1_tx_div_clk_src.clkr.hw,
1865                         },
1866                         .num_parents = 1,
1867                         .ops = &clk_branch2_ops,
1868                         .flags = CLK_SET_RATE_PARENT,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch gcc_gp1_clk = {
1874         .halt_reg = 0x08000,
1875         .clkr = {
1876                 .enable_reg = 0x08000,
1877                 .enable_mask = BIT(0),
1878                 .hw.init = &(struct clk_init_data) {
1879                         .name = "gcc_gp1_clk",
1880                         .parent_hws = (const struct clk_hw *[]) {
1881                                 &gp1_clk_src.clkr.hw,
1882                         },
1883                         .num_parents = 1,
1884                         .flags = CLK_SET_RATE_PARENT,
1885                         .ops = &clk_branch2_ops,
1886                 },
1887         },
1888 };
1889
1890 static struct clk_branch gcc_gp2_clk = {
1891         .halt_reg = 0x09000,
1892         .clkr = {
1893                 .enable_reg = 0x09000,
1894                 .enable_mask = BIT(0),
1895                 .hw.init = &(struct clk_init_data) {
1896                         .name = "gcc_gp2_clk",
1897                         .parent_hws = (const struct clk_hw *[]) {
1898                                 &gp2_clk_src.clkr.hw,
1899                         },
1900                         .num_parents = 1,
1901                         .flags = CLK_SET_RATE_PARENT,
1902                         .ops = &clk_branch2_ops,
1903                 },
1904         },
1905 };
1906
1907 static struct clk_branch gcc_gp3_clk = {
1908         .halt_reg = 0x0a000,
1909         .clkr = {
1910                 .enable_reg = 0x0a000,
1911                 .enable_mask = BIT(0),
1912                 .hw.init = &(struct clk_init_data) {
1913                         .name = "gcc_gp3_clk",
1914                         .parent_hws = (const struct clk_hw *[]) {
1915                                 &gp3_clk_src.clkr.hw,
1916                         },
1917                         .num_parents = 1,
1918                         .flags = CLK_SET_RATE_PARENT,
1919                         .ops = &clk_branch2_ops,
1920                 },
1921         },
1922 };
1923
1924 static struct clk_branch gcc_lpass_core_axim_clk = {
1925         .halt_reg = 0x2e048,
1926         .halt_check = BRANCH_VOTED,
1927         .clkr = {
1928                 .enable_reg = 0x2e048,
1929                 .enable_mask = BIT(0),
1930                 .hw.init = &(struct clk_init_data) {
1931                         .name = "gcc_lpass_core_axim_clk",
1932                         .parent_hws = (const struct clk_hw *[]) {
1933                                 &lpass_axim_clk_src.clkr.hw,
1934                         },
1935                         .num_parents = 1,
1936                         .flags = CLK_SET_RATE_PARENT,
1937                         .ops = &clk_branch2_ops,
1938                 },
1939         },
1940 };
1941
1942 static struct clk_branch gcc_lpass_sway_clk = {
1943         .halt_reg = 0x2e04c,
1944         .clkr = {
1945                 .enable_reg = 0x2e04c,
1946                 .enable_mask = BIT(0),
1947                 .hw.init = &(struct clk_init_data) {
1948                         .name = "gcc_lpass_sway_clk",
1949                         .parent_hws = (const struct clk_hw *[]) {
1950                                 &lpass_sway_clk_src.clkr.hw,
1951                         },
1952                         .num_parents = 1,
1953                         .flags = CLK_SET_RATE_PARENT,
1954                         .ops = &clk_branch2_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch gcc_mdio0_ahb_clk = {
1960         .halt_reg = 0x58004,
1961         .clkr = {
1962                 .enable_reg = 0x58004,
1963                 .enable_mask = BIT(0),
1964                 .hw.init = &(struct clk_init_data) {
1965                         .name = "gcc_mdioi0_ahb_clk",
1966                         .parent_hws = (const struct clk_hw *[]) {
1967                                 &pcnoc_clk_src.hw,
1968                         },
1969                         .num_parents = 1,
1970                         .flags = CLK_SET_RATE_PARENT,
1971                         .ops = &clk_branch2_ops,
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch gcc_mdio1_ahb_clk = {
1977         .halt_reg = 0x58014,
1978         .clkr = {
1979                 .enable_reg = 0x58014,
1980                 .enable_mask = BIT(0),
1981                 .hw.init = &(struct clk_init_data) {
1982                         .name = "gcc_mdio1_ahb_clk",
1983                         .parent_hws = (const struct clk_hw *[]) {
1984                                 &pcnoc_clk_src.hw,
1985                         },
1986                         .num_parents = 1,
1987                         .flags = CLK_SET_RATE_PARENT,
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch gcc_pcie0_ahb_clk = {
1994         .halt_reg = 0x75010,
1995         .clkr = {
1996                 .enable_reg = 0x75010,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data) {
1999                         .name = "gcc_pcie0_ahb_clk",
2000                         .parent_hws = (const struct clk_hw *[]) {
2001                                 &pcnoc_clk_src.hw,
2002                         },
2003                         .num_parents = 1,
2004                         .flags = CLK_SET_RATE_PARENT,
2005                         .ops = &clk_branch2_ops,
2006                 },
2007         },
2008 };
2009
2010 static struct clk_branch gcc_pcie0_aux_clk = {
2011         .halt_reg = 0x75014,
2012         .clkr = {
2013                 .enable_reg = 0x75014,
2014                 .enable_mask = BIT(0),
2015                 .hw.init = &(struct clk_init_data) {
2016                         .name = "gcc_pcie0_aux_clk",
2017                         .parent_hws = (const struct clk_hw *[]) {
2018                                 &pcie0_aux_clk_src.clkr.hw,
2019                         },
2020                         .num_parents = 1,
2021                         .flags = CLK_SET_RATE_PARENT,
2022                         .ops = &clk_branch2_ops,
2023                 },
2024         },
2025 };
2026
2027 static struct clk_branch gcc_pcie0_axi_m_clk = {
2028         .halt_reg = 0x75008,
2029         .clkr = {
2030                 .enable_reg = 0x75008,
2031                 .enable_mask = BIT(0),
2032                 .hw.init = &(struct clk_init_data) {
2033                         .name = "gcc_pcie0_axi_m_clk",
2034                         .parent_hws = (const struct clk_hw *[]) {
2035                                 &pcie0_axi_clk_src.clkr.hw,
2036                         },
2037                         .num_parents = 1,
2038                         .flags = CLK_SET_RATE_PARENT,
2039                         .ops = &clk_branch2_ops,
2040                 },
2041         },
2042 };
2043
2044 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
2045         .halt_reg = 0x75048,
2046         .clkr = {
2047                 .enable_reg = 0x75048,
2048                 .enable_mask = BIT(0),
2049                 .hw.init = &(struct clk_init_data) {
2050                         .name = "gcc_pcie0_axi_s_bridge_clk",
2051                         .parent_hws = (const struct clk_hw *[]) {
2052                                 &pcie0_axi_clk_src.clkr.hw,
2053                         },
2054                         .num_parents = 1,
2055                         .flags = CLK_SET_RATE_PARENT,
2056                         .ops = &clk_branch2_ops,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch gcc_pcie0_axi_s_clk = {
2062         .halt_reg = 0x7500c,
2063         .clkr = {
2064                 .enable_reg = 0x7500c,
2065                 .enable_mask = BIT(0),
2066                 .hw.init = &(struct clk_init_data) {
2067                         .name = "gcc_pcie0_axi_s_clk",
2068                         .parent_hws = (const struct clk_hw *[]) {
2069                                 &pcie0_axi_clk_src.clkr.hw,
2070                         },
2071                         .num_parents = 1,
2072                         .flags = CLK_SET_RATE_PARENT,
2073                         .ops = &clk_branch2_ops,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch gcc_pcie0_pipe_clk = {
2079         .halt_reg = 0x75018,
2080         .halt_check = BRANCH_HALT_DELAY,
2081         .halt_bit = 31,
2082         .clkr = {
2083                 .enable_reg = 0x75018,
2084                 .enable_mask = BIT(0),
2085                 .hw.init = &(struct clk_init_data) {
2086                         .name = "gcc_pcie0_pipe_clk",
2087                         .parent_hws = (const struct clk_hw *[]) {
2088                                 &pcie0_pipe_clk_src.clkr.hw,
2089                         },
2090                         .num_parents = 1,
2091                         .flags = CLK_SET_RATE_PARENT,
2092                         .ops = &clk_branch2_ops,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch gcc_pcie1_ahb_clk = {
2098         .halt_reg = 0x76010,
2099         .clkr = {
2100                 .enable_reg = 0x76010,
2101                 .enable_mask = BIT(0),
2102                 .hw.init = &(struct clk_init_data) {
2103                         .name = "gcc_pcie1_ahb_clk",
2104                         .parent_hws = (const struct clk_hw *[]) {
2105                                 &pcnoc_clk_src.hw,
2106                         },
2107                         .num_parents = 1,
2108                         .flags = CLK_SET_RATE_PARENT,
2109                         .ops = &clk_branch2_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_branch gcc_pcie1_aux_clk = {
2115         .halt_reg = 0x76014,
2116         .clkr = {
2117                 .enable_reg = 0x76014,
2118                 .enable_mask = BIT(0),
2119                 .hw.init = &(struct clk_init_data) {
2120                         .name = "gcc_pcie1_aux_clk",
2121                         .parent_hws = (const struct clk_hw *[]) {
2122                                 &pcie1_aux_clk_src.clkr.hw,
2123                         },
2124                         .num_parents = 1,
2125                         .flags = CLK_SET_RATE_PARENT,
2126                         .ops = &clk_branch2_ops,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch gcc_pcie1_axi_m_clk = {
2132         .halt_reg = 0x76008,
2133         .clkr = {
2134                 .enable_reg = 0x76008,
2135                 .enable_mask = BIT(0),
2136                 .hw.init = &(struct clk_init_data) {
2137                         .name = "gcc_pcie1_axi_m_clk",
2138                         .parent_hws = (const struct clk_hw *[]) {
2139                                 &pcie1_axi_clk_src.clkr.hw,
2140                         },
2141                         .num_parents = 1,
2142                         .flags = CLK_SET_RATE_PARENT,
2143                         .ops = &clk_branch2_ops,
2144                 },
2145         },
2146 };
2147
2148 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
2149         .halt_reg = 0x76048,
2150         .clkr = {
2151                 .enable_reg = 0x76048,
2152                 .enable_mask = BIT(0),
2153                 .hw.init = &(struct clk_init_data) {
2154                         .name = "gcc_pcie1_axi_s_bridge_clk",
2155                         .parent_hws = (const struct clk_hw *[]) {
2156                                 &pcie1_axi_clk_src.clkr.hw,
2157                         },
2158                         .num_parents = 1,
2159                         .flags = CLK_SET_RATE_PARENT,
2160                         .ops = &clk_branch2_ops,
2161                 },
2162         },
2163 };
2164
2165 static struct clk_branch gcc_pcie1_axi_s_clk = {
2166         .halt_reg = 0x7600c,
2167         .clkr = {
2168                 .enable_reg = 0x7600c,
2169                 .enable_mask = BIT(0),
2170                 .hw.init = &(struct clk_init_data) {
2171                         .name = "gcc_pcie1_axi_s_clk",
2172                         .parent_hws = (const struct clk_hw *[]) {
2173                                 &pcie1_axi_clk_src.clkr.hw,
2174                         },
2175                         .num_parents = 1,
2176                         .flags = CLK_SET_RATE_PARENT,
2177                         .ops = &clk_branch2_ops,
2178                 },
2179         },
2180 };
2181
2182 static struct clk_branch gcc_pcie1_pipe_clk = {
2183         .halt_reg = 8,
2184         .halt_check = BRANCH_HALT_DELAY,
2185         .halt_bit = 31,
2186         .clkr = {
2187                 .enable_reg = 0x76018,
2188                 .enable_mask = BIT(0),
2189                 .hw.init = &(struct clk_init_data) {
2190                         .name = "gcc_pcie1_pipe_clk",
2191                         .parent_hws = (const struct clk_hw *[]) {
2192                                 &pcie1_pipe_clk_src.clkr.hw,
2193                         },
2194                         .num_parents = 1,
2195                         .flags = CLK_SET_RATE_PARENT,
2196                         .ops = &clk_branch2_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gcc_prng_ahb_clk = {
2202         .halt_reg = 0x13004,
2203         .halt_check = BRANCH_HALT_VOTED,
2204         .clkr = {
2205                 .enable_reg = 0x0b004,
2206                 .enable_mask = BIT(8),
2207                 .hw.init = &(struct clk_init_data) {
2208                         .name = "gcc_prng_ahb_clk",
2209                         .parent_hws = (const struct clk_hw *[]) {
2210                                 &pcnoc_clk_src.hw,
2211                         },
2212                         .num_parents = 1,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_q6_ahb_clk = {
2220         .halt_reg = 0x59138,
2221         .clkr = {
2222                 .enable_reg = 0x59138,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data) {
2225                         .name = "gcc_q6_ahb_clk",
2226                         .parent_hws = (const struct clk_hw *[]) {
2227                                 &wcss_ahb_clk_src.clkr.hw,
2228                         },
2229                         .num_parents = 1,
2230                         .flags = CLK_SET_RATE_PARENT,
2231                         .ops = &clk_branch2_ops,
2232                 },
2233         },
2234 };
2235
2236 static struct clk_branch gcc_q6_ahb_s_clk = {
2237         .halt_reg = 0x5914c,
2238         .clkr = {
2239                 .enable_reg = 0x5914c,
2240                 .enable_mask = BIT(0),
2241                 .hw.init = &(struct clk_init_data) {
2242                         .name = "gcc_q6_ahb_s_clk",
2243                         .parent_hws = (const struct clk_hw *[]) {
2244                                 &wcss_ahb_clk_src.clkr.hw,
2245                         },
2246                         .num_parents = 1,
2247                         .flags = CLK_SET_RATE_PARENT,
2248                         .ops = &clk_branch2_ops,
2249                 },
2250         },
2251 };
2252
2253 static struct clk_branch gcc_q6_axim_clk = {
2254         .halt_reg = 0x5913c,
2255         .clkr = {
2256                 .enable_reg = 0x5913c,
2257                 .enable_mask = BIT(0),
2258                 .hw.init = &(struct clk_init_data) {
2259                         .name = "gcc_q6_axim_clk",
2260                         .parent_hws = (const struct clk_hw *[]) {
2261                                 &q6_axi_clk_src.clkr.hw,
2262                         },
2263                         .num_parents = 1,
2264                         .flags = CLK_SET_RATE_PARENT,
2265                         .ops = &clk_branch2_ops,
2266                 },
2267         },
2268 };
2269
2270 static struct clk_branch gcc_q6_axim2_clk = {
2271         .halt_reg = 0x59150,
2272         .clkr = {
2273                 .enable_reg = 0x59150,
2274                 .enable_mask = BIT(0),
2275                 .hw.init = &(struct clk_init_data) {
2276                         .name = "gcc_q6_axim2_clk",
2277                         .parent_hws = (const struct clk_hw *[]) {
2278                                 &q6_axi_clk_src.clkr.hw,
2279                         },
2280                         .num_parents = 1,
2281                         .flags = CLK_SET_RATE_PARENT,
2282                         .ops = &clk_branch2_ops,
2283                 },
2284         },
2285 };
2286
2287 static struct clk_branch gcc_q6_axis_clk = {
2288         .halt_reg = 0x59154,
2289         .clkr = {
2290                 .enable_reg = 0x59154,
2291                 .enable_mask = BIT(0),
2292                 .hw.init = &(struct clk_init_data) {
2293                         .name = "gcc_q6_axis_clk",
2294                         .parent_hws = (const struct clk_hw *[]) {
2295                                 &system_noc_clk_src.hw,
2296                         },
2297                         .num_parents = 1,
2298                         .flags = CLK_SET_RATE_PARENT,
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2305         .halt_reg = 0x59148,
2306         .clkr = {
2307                 .enable_reg = 0x59148,
2308                 .enable_mask = BIT(0),
2309                 .hw.init = &(struct clk_init_data) {
2310                         .name = "gcc_q6_tsctr_1to2_clk",
2311                         .parent_hws = (const struct clk_hw *[]) {
2312                                 &qdss_tsctr_div2_clk_src.hw,
2313                         },
2314                         .num_parents = 1,
2315                         .flags = CLK_SET_RATE_PARENT,
2316                         .ops = &clk_branch2_ops,
2317                 },
2318         },
2319 };
2320
2321 static struct clk_branch gcc_q6ss_atbm_clk = {
2322         .halt_reg = 0x59144,
2323         .clkr = {
2324                 .enable_reg = 0x59144,
2325                 .enable_mask = BIT(0),
2326                 .hw.init = &(struct clk_init_data) {
2327                         .name = "gcc_q6ss_atbm_clk",
2328                         .parent_hws = (const struct clk_hw *[]) {
2329                                 &qdss_at_clk_src.clkr.hw,
2330                         },
2331                         .num_parents = 1,
2332                         .flags = CLK_SET_RATE_PARENT,
2333                         .ops = &clk_branch2_ops,
2334                 },
2335         },
2336 };
2337
2338 static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2339         .halt_reg = 0x59140,
2340         .clkr = {
2341                 .enable_reg = 0x59140,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data) {
2344                         .name = "gcc_q6ss_pclkdbg_clk",
2345                         .parent_hws = (const struct clk_hw *[]) {
2346                                 &qdss_dap_sync_clk_src.hw,
2347                         },
2348                         .num_parents = 1,
2349                         .flags = CLK_SET_RATE_PARENT,
2350                         .ops = &clk_branch2_ops,
2351                 },
2352         },
2353 };
2354
2355 static struct clk_branch gcc_q6ss_trig_clk = {
2356         .halt_reg = 0x59128,
2357         .clkr = {
2358                 .enable_reg = 0x59128,
2359                 .enable_mask = BIT(0),
2360                 .hw.init = &(struct clk_init_data) {
2361                         .name = "gcc_q6ss_trig_clk",
2362                         .parent_hws = (const struct clk_hw *[]) {
2363                                 &qdss_dap_sync_clk_src.hw,
2364                         },
2365                         .num_parents = 1,
2366                         .flags = CLK_SET_RATE_PARENT,
2367                         .ops = &clk_branch2_ops,
2368                 },
2369         },
2370 };
2371
2372 static struct clk_branch gcc_qdss_at_clk = {
2373         .halt_reg = 0x29024,
2374         .clkr = {
2375                 .enable_reg = 0x29024,
2376                 .enable_mask = BIT(0),
2377                 .hw.init = &(struct clk_init_data) {
2378                         .name = "gcc_qdss_at_clk",
2379                         .parent_hws = (const struct clk_hw *[]) {
2380                                 &qdss_at_clk_src.clkr.hw,
2381                         },
2382                         .num_parents = 1,
2383                         .flags = CLK_SET_RATE_PARENT,
2384                         .ops = &clk_branch2_ops,
2385                 },
2386         },
2387 };
2388
2389 static struct clk_branch gcc_qdss_dap_clk = {
2390         .halt_reg = 0x29084,
2391         .clkr = {
2392                 .enable_reg = 0x29084,
2393                 .enable_mask = BIT(0),
2394                 .hw.init = &(struct clk_init_data) {
2395                         .name = "gcc_qdss_dap_clk",
2396                         .parent_hws = (const struct clk_hw *[]) {
2397                                 &qdss_tsctr_clk_src.clkr.hw,
2398                         },
2399                         .num_parents = 1,
2400                         .flags = CLK_SET_RATE_PARENT,
2401                         .ops = &clk_branch2_ops,
2402                 },
2403         },
2404 };
2405
2406 static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2407         .halt_reg = 0x29008,
2408         .clkr = {
2409                 .enable_reg = 0x29008,
2410                 .enable_mask = BIT(0),
2411                 .hw.init = &(struct clk_init_data) {
2412                         .name = "gcc_qdss_cfg_ahb_clk",
2413                         .parent_hws = (const struct clk_hw *[]) {
2414                                 &pcnoc_clk_src.hw,
2415                         },
2416                         .num_parents = 1,
2417                         .flags = CLK_SET_RATE_PARENT,
2418                         .ops = &clk_branch2_ops,
2419                 },
2420         },
2421 };
2422
2423 static struct clk_branch gcc_qdss_dap_ahb_clk = {
2424         .halt_reg = 0x29004,
2425         .clkr = {
2426                 .enable_reg = 0x29004,
2427                 .enable_mask = BIT(0),
2428                 .hw.init = &(struct clk_init_data) {
2429                         .name = "gcc_qdss_dap_ahb_clk",
2430                         .parent_hws = (const struct clk_hw *[]) {
2431                                 &pcnoc_clk_src.hw,
2432                         },
2433                         .num_parents = 1,
2434                         .flags = CLK_SET_RATE_PARENT,
2435                         .ops = &clk_branch2_ops,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_branch gcc_qdss_etr_usb_clk = {
2441         .halt_reg = 0x29028,
2442         .clkr = {
2443                 .enable_reg = 0x29028,
2444                 .enable_mask = BIT(0),
2445                 .hw.init = &(struct clk_init_data) {
2446                         .name = "gcc_qdss_etr_usb_clk",
2447                         .parent_hws = (const struct clk_hw *[]) {
2448                                 &system_noc_clk_src.hw,
2449                         },
2450                         .num_parents = 1,
2451                         .flags = CLK_SET_RATE_PARENT,
2452                         .ops = &clk_branch2_ops,
2453                 },
2454         },
2455 };
2456
2457 static struct clk_branch gcc_qdss_eud_at_clk = {
2458         .halt_reg = 0x29020,
2459         .clkr = {
2460                 .enable_reg = 0x29020,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data) {
2463                         .name = "gcc_qdss_eud_at_clk",
2464                         .parent_hws = (const struct clk_hw *[]) {
2465                                 &eud_at_clk_src.hw,
2466                         },
2467                         .num_parents = 1,
2468                         .flags = CLK_SET_RATE_PARENT,
2469                         .ops = &clk_branch2_ops,
2470                 },
2471         },
2472 };
2473
2474 static struct clk_branch gcc_qdss_stm_clk = {
2475         .halt_reg = 0x29044,
2476         .clkr = {
2477                 .enable_reg = 0x29044,
2478                 .enable_mask = BIT(0),
2479                 .hw.init = &(struct clk_init_data) {
2480                         .name = "gcc_qdss_stm_clk",
2481                         .parent_hws = (const struct clk_hw *[]) {
2482                                 &qdss_stm_clk_src.clkr.hw,
2483                         },
2484                         .num_parents = 1,
2485                         .flags = CLK_SET_RATE_PARENT,
2486                         .ops = &clk_branch2_ops,
2487                 },
2488         },
2489 };
2490
2491 static struct clk_branch gcc_qdss_traceclkin_clk = {
2492         .halt_reg = 0x29060,
2493         .clkr = {
2494                 .enable_reg = 0x29060,
2495                 .enable_mask = BIT(0),
2496                 .hw.init = &(struct clk_init_data) {
2497                         .name = "gcc_qdss_traceclkin_clk",
2498                         .parent_hws = (const struct clk_hw *[]) {
2499                                 &qdss_traceclkin_clk_src.clkr.hw,
2500                         },
2501                         .num_parents = 1,
2502                         .flags = CLK_SET_RATE_PARENT,
2503                         .ops = &clk_branch2_ops,
2504                 },
2505         },
2506 };
2507
2508 static struct clk_branch gcc_qdss_tsctr_div8_clk = {
2509         .halt_reg = 0x2908c,
2510         .clkr = {
2511                 .enable_reg = 0x2908c,
2512                 .enable_mask = BIT(0),
2513                 .hw.init = &(struct clk_init_data) {
2514                         .name = "gcc_qdss_tsctr_div8_clk",
2515                         .parent_hws = (const struct clk_hw *[]) {
2516                                 &qdss_tsctr_clk_src.clkr.hw,
2517                         },
2518                         .num_parents = 1,
2519                         .flags = CLK_SET_RATE_PARENT,
2520                         .ops = &clk_branch2_ops,
2521                 },
2522         },
2523 };
2524
2525 static struct clk_branch gcc_qpic_ahb_clk = {
2526         .halt_reg = 0x57024,
2527         .clkr = {
2528                 .enable_reg = 0x57024,
2529                 .enable_mask = BIT(0),
2530                 .hw.init = &(struct clk_init_data) {
2531                         .name = "gcc_qpic_ahb_clk",
2532                         .parent_hws = (const struct clk_hw *[]) {
2533                                 &pcnoc_clk_src.hw,
2534                         },
2535                         .num_parents = 1,
2536                         .flags = CLK_SET_RATE_PARENT,
2537                         .ops = &clk_branch2_ops,
2538                 },
2539         },
2540 };
2541
2542 static struct clk_branch gcc_qpic_clk = {
2543         .halt_reg = 0x57020,
2544         .clkr = {
2545                 .enable_reg = 0x57020,
2546                 .enable_mask = BIT(0),
2547                 .hw.init = &(struct clk_init_data) {
2548                         .name = "gcc_qpic_clk",
2549                         .parent_hws = (const struct clk_hw *[]) {
2550                                 &pcnoc_clk_src.hw,
2551                         },
2552                         .num_parents = 1,
2553                         .flags = CLK_SET_RATE_PARENT,
2554                         .ops = &clk_branch2_ops,
2555                 },
2556         },
2557 };
2558
2559 static struct clk_branch gcc_qpic_io_macro_clk = {
2560         .halt_reg = 0x5701c,
2561         .clkr = {
2562                 .enable_reg = 0x5701c,
2563                 .enable_mask = BIT(0),
2564                 .hw.init = &(struct clk_init_data) {
2565                         .name = "gcc_qpic_io_macro_clk",
2566                         .parent_hws = (const struct clk_hw *[]) {
2567                                 &qpic_io_macro_clk_src.clkr.hw,
2568                         },
2569                         .num_parents = 1,
2570                         .flags = CLK_SET_RATE_PARENT,
2571                         .ops = &clk_branch2_ops,
2572                 },
2573         },
2574 };
2575
2576 static struct clk_branch gcc_sdcc1_ahb_clk = {
2577         .halt_reg = 0x4201c,
2578         .clkr = {
2579                 .enable_reg = 0x4201c,
2580                 .enable_mask = BIT(0),
2581                 .hw.init = &(struct clk_init_data) {
2582                         .name = "gcc_sdcc1_ahb_clk",
2583                         .parent_hws = (const struct clk_hw *[]) {
2584                                 &pcnoc_clk_src.hw,
2585                         },
2586                         .num_parents = 1,
2587                         .flags = CLK_SET_RATE_PARENT,
2588                         .ops = &clk_branch2_ops,
2589                 },
2590         },
2591 };
2592
2593 static struct clk_branch gcc_sdcc1_apps_clk = {
2594         .halt_reg = 0x42018,
2595         .clkr = {
2596                 .enable_reg = 0x42018,
2597                 .enable_mask = BIT(0),
2598                 .hw.init = &(struct clk_init_data) {
2599                         .name = "gcc_sdcc1_apps_clk",
2600                         .parent_hws = (const struct clk_hw *[]) {
2601                                 &sdcc1_apps_clk_src.clkr.hw,
2602                         },
2603                         .num_parents = 1,
2604                         .flags = CLK_SET_RATE_PARENT,
2605                         .ops = &clk_branch2_ops,
2606                 },
2607         },
2608 };
2609
2610 static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
2611         .halt_reg = 0x260a0,
2612         .clkr = {
2613                 .enable_reg = 0x260a0,
2614                 .enable_mask = BIT(0),
2615                 .hw.init = &(struct clk_init_data) {
2616                         .name = "gcc_snoc_gmac0_ahb_clk",
2617                         .parent_hws = (const struct clk_hw *[]) {
2618                                 &gmac_clk_src.clkr.hw,
2619                         },
2620                         .num_parents = 1,
2621                         .flags = CLK_SET_RATE_PARENT,
2622                         .ops = &clk_branch2_ops,
2623                 },
2624         },
2625 };
2626
2627 static struct clk_branch gcc_snoc_gmac0_axi_clk = {
2628         .halt_reg = 0x26084,
2629         .clkr = {
2630                 .enable_reg = 0x26084,
2631                 .enable_mask = BIT(0),
2632                 .hw.init = &(struct clk_init_data) {
2633                         .name = "gcc_snoc_gmac0_axi_clk",
2634                         .parent_hws = (const struct clk_hw *[]) {
2635                                 &gmac_clk_src.clkr.hw,
2636                         },
2637                         .num_parents = 1,
2638                         .flags = CLK_SET_RATE_PARENT,
2639                         .ops = &clk_branch2_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
2645         .halt_reg = 0x260a4,
2646         .clkr = {
2647                 .enable_reg = 0x260a4,
2648                 .enable_mask = BIT(0),
2649                 .hw.init = &(struct clk_init_data) {
2650                         .name = "gcc_snoc_gmac1_ahb_clk",
2651                         .parent_hws = (const struct clk_hw *[]) {
2652                                 &gmac_clk_src.clkr.hw,
2653                         },
2654                         .num_parents = 1,
2655                         .flags = CLK_SET_RATE_PARENT,
2656                         .ops = &clk_branch2_ops,
2657                 },
2658         },
2659 };
2660
2661 static struct clk_branch gcc_snoc_gmac1_axi_clk = {
2662         .halt_reg = 0x26088,
2663         .clkr = {
2664                 .enable_reg = 0x26088,
2665                 .enable_mask = BIT(0),
2666                 .hw.init = &(struct clk_init_data) {
2667                         .name = "gcc_snoc_gmac1_axi_clk",
2668                         .parent_hws = (const struct clk_hw *[]) {
2669                                 &gmac_clk_src.clkr.hw,
2670                         },
2671                         .num_parents = 1,
2672                         .flags = CLK_SET_RATE_PARENT,
2673                         .ops = &clk_branch2_ops,
2674                 },
2675         },
2676 };
2677
2678 static struct clk_branch gcc_snoc_lpass_axim_clk = {
2679         .halt_reg = 0x26074,
2680         .clkr = {
2681                 .enable_reg = 0x26074,
2682                 .enable_mask = BIT(0),
2683                 .hw.init = &(struct clk_init_data) {
2684                         .name = "gcc_snoc_lpass_axim_clk",
2685                         .parent_hws = (const struct clk_hw *[]) {
2686                                 &lpass_axim_clk_src.clkr.hw,
2687                         },
2688                         .num_parents = 1,
2689                         .flags = CLK_SET_RATE_PARENT,
2690                         .ops = &clk_branch2_ops,
2691                 },
2692         },
2693 };
2694
2695 static struct clk_branch gcc_snoc_lpass_sway_clk = {
2696         .halt_reg = 0x26078,
2697         .clkr = {
2698                 .enable_reg = 0x26078,
2699                 .enable_mask = BIT(0),
2700                 .hw.init = &(struct clk_init_data) {
2701                         .name = "gcc_snoc_lpass_sway_clk",
2702                         .parent_hws = (const struct clk_hw *[]) {
2703                                 &lpass_sway_clk_src.clkr.hw,
2704                         },
2705                         .num_parents = 1,
2706                         .flags = CLK_SET_RATE_PARENT,
2707                         .ops = &clk_branch2_ops,
2708                 },
2709         },
2710 };
2711
2712 static struct clk_branch gcc_snoc_ubi0_axi_clk = {
2713         .halt_reg = 0x26094,
2714         .clkr = {
2715                 .enable_reg = 0x26094,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data) {
2718                         .name = "gcc_snoc_ubi0_axi_clk",
2719                         .parent_hws = (const struct clk_hw *[]) {
2720                                 &ubi0_axi_clk_src.clkr.hw,
2721                         },
2722                         .num_parents = 1,
2723                         .flags = CLK_SET_RATE_PARENT,
2724                         .ops = &clk_branch2_ops,
2725                 },
2726         },
2727 };
2728
2729 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2730         .halt_reg = 0x26048,
2731         .clkr = {
2732                 .enable_reg = 0x26048,
2733                 .enable_mask = BIT(0),
2734                 .hw.init = &(struct clk_init_data) {
2735                         .name = "gcc_sys_noc_pcie0_axi_clk",
2736                         .parent_hws = (const struct clk_hw *[]) {
2737                                 &pcie0_axi_clk_src.clkr.hw,
2738                         },
2739                         .num_parents = 1,
2740                         .flags = CLK_SET_RATE_PARENT,
2741                         .ops = &clk_branch2_ops,
2742                 },
2743         },
2744 };
2745
2746 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2747         .halt_reg = 0x2604c,
2748         .clkr = {
2749                 .enable_reg = 0x2604c,
2750                 .enable_mask = BIT(0),
2751                 .hw.init = &(struct clk_init_data) {
2752                         .name = "gcc_sys_noc_pcie1_axi_clk",
2753                         .parent_hws = (const struct clk_hw *[]) {
2754                                 &pcie1_axi_clk_src.clkr.hw,
2755                         },
2756                         .num_parents = 1,
2757                         .flags = CLK_SET_RATE_PARENT,
2758                         .ops = &clk_branch2_ops,
2759                 },
2760         },
2761 };
2762
2763 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2764         .halt_reg = 0x26024,
2765         .clkr = {
2766                 .enable_reg = 0x26024,
2767                 .enable_mask = BIT(0),
2768                 .hw.init = &(struct clk_init_data) {
2769                         .name = "gcc_sys_noc_qdss_stm_axi_clk",
2770                         .parent_hws = (const struct clk_hw *[]) {
2771                                 &qdss_stm_clk_src.clkr.hw,
2772                         },
2773                         .num_parents = 1,
2774                         .flags = CLK_SET_RATE_PARENT,
2775                         .ops = &clk_branch2_ops,
2776                 },
2777         },
2778 };
2779
2780 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2781         .halt_reg = 0x26040,
2782         .clkr = {
2783                 .enable_reg = 0x26040,
2784                 .enable_mask = BIT(0),
2785                 .hw.init = &(struct clk_init_data) {
2786                         .name = "gcc_sys_noc_usb0_axi_clk",
2787                         .parent_hws = (const struct clk_hw *[]) {
2788                                 &usb0_master_clk_src.clkr.hw,
2789                         },
2790                         .num_parents = 1,
2791                         .flags = CLK_SET_RATE_PARENT,
2792                         .ops = &clk_branch2_ops,
2793                 },
2794         },
2795 };
2796
2797 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2798         .halt_reg = 0x26034,
2799         .clkr = {
2800                 .enable_reg = 0x26034,
2801                 .enable_mask = BIT(0),
2802                 .hw.init = &(struct clk_init_data) {
2803                         .name = "gcc_sys_noc_wcss_ahb_clk",
2804                         .parent_hws = (const struct clk_hw *[]) {
2805                                 &wcss_ahb_clk_src.clkr.hw,
2806                         },
2807                         .num_parents = 1,
2808                         .flags = CLK_SET_RATE_PARENT,
2809                         .ops = &clk_branch2_ops,
2810                 },
2811         },
2812 };
2813
2814 static struct clk_branch gcc_ubi0_axi_clk = {
2815         .halt_reg = 0x68200,
2816         .halt_check = BRANCH_HALT_DELAY,
2817         .clkr = {
2818                 .enable_reg = 0x68200,
2819                 .enable_mask = BIT(0),
2820                 .hw.init = &(struct clk_init_data) {
2821                         .name = "gcc_ubi0_axi_clk",
2822                         .parent_hws = (const struct clk_hw *[]) {
2823                                 &ubi0_axi_clk_src.clkr.hw,
2824                         },
2825                         .num_parents = 1,
2826                         .flags = CLK_SET_RATE_PARENT,
2827                         .ops = &clk_branch2_ops,
2828                 },
2829         },
2830 };
2831
2832 static struct clk_branch gcc_ubi0_cfg_clk = {
2833         .halt_reg = 0x68160,
2834         .halt_check = BRANCH_HALT_DELAY,
2835         .clkr = {
2836                 .enable_reg = 0x68160,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(struct clk_init_data) {
2839                         .name = "gcc_ubi0_cfg_clk",
2840                         .parent_hws = (const struct clk_hw *[]) {
2841                                 &pcnoc_clk_src.hw,
2842                         },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch gcc_ubi0_dbg_clk = {
2851         .halt_reg = 0x68214,
2852         .halt_check = BRANCH_HALT_DELAY,
2853         .clkr = {
2854                 .enable_reg = 0x68214,
2855                 .enable_mask = BIT(0),
2856                 .hw.init = &(struct clk_init_data) {
2857                         .name = "gcc_ubi0_dbg_clk",
2858                         .parent_hws = (const struct clk_hw *[]) {
2859                                 &qdss_tsctr_clk_src.clkr.hw,
2860                         },
2861                         .num_parents = 1,
2862                         .flags = CLK_SET_RATE_PARENT,
2863                         .ops = &clk_branch2_ops,
2864                 },
2865         },
2866 };
2867
2868 static struct clk_branch gcc_ubi0_core_clk = {
2869         .halt_reg = 0x68210,
2870         .halt_check = BRANCH_HALT_DELAY,
2871         .clkr = {
2872                 .enable_reg = 0x68210,
2873                 .enable_mask = BIT(0),
2874                 .hw.init = &(struct clk_init_data) {
2875                         .name = "gcc_ubi0_core_clk",
2876                         .parent_hws = (const struct clk_hw *[]) {
2877                                 &ubi0_core_clk_src.clkr.hw,
2878                         },
2879                         .num_parents = 1,
2880                         .flags = CLK_SET_RATE_PARENT,
2881                         .ops = &clk_branch2_ops,
2882                 },
2883         },
2884 };
2885
2886 static struct clk_branch gcc_ubi0_nc_axi_clk = {
2887         .halt_reg = 0x68204,
2888         .halt_check = BRANCH_HALT_DELAY,
2889         .clkr = {
2890                 .enable_reg = 0x68204,
2891                 .enable_mask = BIT(0),
2892                 .hw.init = &(struct clk_init_data) {
2893                         .name = "gcc_ubi0_nc_axi_clk",
2894                         .parent_hws = (const struct clk_hw *[]) {
2895                                 &system_noc_clk_src.hw,
2896                         },
2897                         .num_parents = 1,
2898                         .flags = CLK_SET_RATE_PARENT,
2899                         .ops = &clk_branch2_ops,
2900                 },
2901         },
2902 };
2903
2904 static struct clk_branch gcc_ubi0_utcm_clk = {
2905         .halt_reg = 0x68208,
2906         .halt_check = BRANCH_HALT_DELAY,
2907         .clkr = {
2908                 .enable_reg = 0x68208,
2909                 .enable_mask = BIT(0),
2910                 .hw.init = &(struct clk_init_data) {
2911                         .name = "gcc_ubi0_utcm_clk",
2912                         .parent_hws = (const struct clk_hw *[]) {
2913                                 &system_noc_clk_src.hw,
2914                         },
2915                         .num_parents = 1,
2916                         .flags = CLK_SET_RATE_PARENT,
2917                         .ops = &clk_branch2_ops,
2918                 },
2919         },
2920 };
2921
2922 static struct clk_branch gcc_uniphy_ahb_clk = {
2923         .halt_reg = 0x56108,
2924         .clkr = {
2925                 .enable_reg = 0x56108,
2926                 .enable_mask = BIT(0),
2927                 .hw.init = &(struct clk_init_data) {
2928                         .name = "gcc_uniphy_ahb_clk",
2929                         .parent_hws = (const struct clk_hw *[]) {
2930                                 &pcnoc_clk_src.hw,
2931                         },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_uniphy_rx_clk = {
2940         .halt_reg = 0x56110,
2941         .clkr = {
2942                 .enable_reg = 0x56110,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data) {
2945                         .name = "gcc_uniphy_rx_clk",
2946                         .parent_hws = (const struct clk_hw *[]) {
2947                                 &gmac1_rx_div_clk_src.clkr.hw,
2948                         },
2949                         .num_parents = 1,
2950                         .ops = &clk_branch2_ops,
2951                         .flags = CLK_SET_RATE_PARENT,
2952                 },
2953         },
2954 };
2955
2956 static struct clk_branch gcc_uniphy_tx_clk = {
2957         .halt_reg = 0x56114,
2958         .clkr = {
2959                 .enable_reg = 0x56114,
2960                 .enable_mask = BIT(0),
2961                 .hw.init = &(struct clk_init_data) {
2962                         .name = "gcc_uniphy_tx_clk",
2963                         .parent_hws = (const struct clk_hw *[]) {
2964                                 &gmac1_tx_div_clk_src.clkr.hw,
2965                         },
2966                         .num_parents = 1,
2967                         .ops = &clk_branch2_ops,
2968                         .flags = CLK_SET_RATE_PARENT,
2969                 },
2970         },
2971 };
2972
2973 static struct clk_branch gcc_uniphy_sys_clk = {
2974         .halt_reg = 0x5610c,
2975         .clkr = {
2976                 .enable_reg = 0x5610c,
2977                 .enable_mask = BIT(0),
2978                 .hw.init = &(struct clk_init_data) {
2979                         .name = "gcc_uniphy_sys_clk",
2980                         .parent_hws = (const struct clk_hw *[]) {
2981                                 &gcc_xo_clk_src.clkr.hw,
2982                         },
2983                         .num_parents = 1,
2984                         .flags = CLK_SET_RATE_PARENT,
2985                         .ops = &clk_branch2_ops,
2986                 },
2987         },
2988 };
2989
2990 static struct clk_branch gcc_usb0_aux_clk = {
2991         .halt_reg = 0x3e044,
2992         .clkr = {
2993                 .enable_reg = 0x3e044,
2994                 .enable_mask = BIT(0),
2995                 .hw.init = &(struct clk_init_data) {
2996                         .name = "gcc_usb0_aux_clk",
2997                         .parent_hws = (const struct clk_hw *[]) {
2998                                 &usb0_aux_clk_src.clkr.hw,
2999                         },
3000                         .num_parents = 1,
3001                         .flags = CLK_SET_RATE_PARENT,
3002                         .ops = &clk_branch2_ops,
3003                 },
3004         },
3005 };
3006
3007 static struct clk_branch gcc_usb0_eud_at_clk = {
3008         .halt_reg = 0x3e04c,
3009         .halt_check = BRANCH_HALT_VOTED,
3010         .clkr = {
3011                 .enable_reg = 0x3e04c,
3012                 .enable_mask = BIT(0),
3013                 .hw.init = &(struct clk_init_data) {
3014                         .name = "gcc_usb0_eud_at_clk",
3015                         .parent_hws = (const struct clk_hw *[]) {
3016                                 &eud_at_clk_src.hw,
3017                         },
3018                         .num_parents = 1,
3019                         .flags = CLK_SET_RATE_PARENT,
3020                         .ops = &clk_branch2_ops,
3021                 },
3022         },
3023 };
3024
3025 static struct clk_branch gcc_usb0_lfps_clk = {
3026         .halt_reg = 0x3e050,
3027         .clkr = {
3028                 .enable_reg = 0x3e050,
3029                 .enable_mask = BIT(0),
3030                 .hw.init = &(struct clk_init_data) {
3031                         .name = "gcc_usb0_lfps_clk",
3032                         .parent_hws = (const struct clk_hw *[]) {
3033                                 &usb0_lfps_clk_src.clkr.hw,
3034                         },
3035                         .num_parents = 1,
3036                         .flags = CLK_SET_RATE_PARENT,
3037                         .ops = &clk_branch2_ops,
3038                 },
3039         },
3040 };
3041
3042 static struct clk_branch gcc_usb0_master_clk = {
3043         .halt_reg = 0x3e000,
3044         .clkr = {
3045                 .enable_reg = 0x3e000,
3046                 .enable_mask = BIT(0),
3047                 .hw.init = &(struct clk_init_data) {
3048                         .name = "gcc_usb0_master_clk",
3049                         .parent_hws = (const struct clk_hw *[]) {
3050                                 &usb0_master_clk_src.clkr.hw,
3051                         },
3052                         .num_parents = 1,
3053                         .flags = CLK_SET_RATE_PARENT,
3054                         .ops = &clk_branch2_ops,
3055                 },
3056         },
3057 };
3058
3059 static struct clk_branch gcc_usb0_mock_utmi_clk = {
3060         .halt_reg = 0x3e008,
3061         .clkr = {
3062                 .enable_reg = 0x3e008,
3063                 .enable_mask = BIT(0),
3064                 .hw.init = &(struct clk_init_data) {
3065                         .name = "gcc_usb0_mock_utmi_clk",
3066                         .parent_hws = (const struct clk_hw *[]) {
3067                                 &usb0_mock_utmi_clk_src.clkr.hw,
3068                         },
3069                         .num_parents = 1,
3070                         .flags = CLK_SET_RATE_PARENT,
3071                         .ops = &clk_branch2_ops,
3072                 },
3073         },
3074 };
3075
3076 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3077         .halt_reg = 0x3e080,
3078         .clkr = {
3079                 .enable_reg = 0x3e080,
3080                 .enable_mask = BIT(0),
3081                 .hw.init = &(struct clk_init_data) {
3082                         .name = "gcc_usb0_phy_cfg_ahb_clk",
3083                         .parent_hws = (const struct clk_hw *[]) {
3084                                 &pcnoc_clk_src.hw,
3085                         },
3086                         .num_parents = 1,
3087                         .flags = CLK_SET_RATE_PARENT,
3088                         .ops = &clk_branch2_ops,
3089                 },
3090         },
3091 };
3092
3093 static struct clk_branch gcc_usb0_sleep_clk = {
3094         .halt_reg = 0x3e004,
3095         .clkr = {
3096                 .enable_reg = 0x3e004,
3097                 .enable_mask = BIT(0),
3098                 .hw.init = &(struct clk_init_data) {
3099                         .name = "gcc_usb0_sleep_clk",
3100                         .parent_hws = (const struct clk_hw *[]) {
3101                                 &gcc_sleep_clk_src.clkr.hw,
3102                         },
3103                         .num_parents = 1,
3104                         .flags = CLK_SET_RATE_PARENT,
3105                         .ops = &clk_branch2_ops,
3106                 },
3107         },
3108 };
3109
3110 static struct clk_branch gcc_usb0_pipe_clk = {
3111         .halt_reg = 0x3e040,
3112         .halt_check = BRANCH_HALT_DELAY,
3113         .clkr = {
3114                 .enable_reg = 0x3e040,
3115                 .enable_mask = BIT(0),
3116                 .hw.init = &(struct clk_init_data) {
3117                         .name = "gcc_usb0_pipe_clk",
3118                         .parent_hws = (const struct clk_hw *[]) {
3119                                 &usb0_pipe_clk_src.clkr.hw,
3120                         },
3121                         .num_parents = 1,
3122                         .flags = CLK_SET_RATE_PARENT,
3123                         .ops = &clk_branch2_ops,
3124                 },
3125         },
3126 };
3127
3128 static struct clk_branch gcc_wcss_acmt_clk = {
3129         .halt_reg = 0x59064,
3130         .clkr = {
3131                 .enable_reg = 0x59064,
3132                 .enable_mask = BIT(0),
3133                 .hw.init = &(struct clk_init_data) {
3134                         .name = "gcc_wcss_acmt_clk",
3135                         .parent_hws = (const struct clk_hw *[]) {
3136                                 &wcss_ahb_clk_src.clkr.hw,
3137                         },
3138                         .num_parents = 1,
3139                         .flags = CLK_SET_RATE_PARENT,
3140                         .ops = &clk_branch2_ops,
3141                 },
3142         },
3143 };
3144
3145 static struct clk_branch gcc_wcss_ahb_s_clk = {
3146         .halt_reg = 0x59034,
3147         .clkr = {
3148                 .enable_reg = 0x59034,
3149                 .enable_mask = BIT(0),
3150                 .hw.init = &(struct clk_init_data) {
3151                         .name = "gcc_wcss_ahb_s_clk",
3152                         .parent_hws = (const struct clk_hw *[]) {
3153                                 &wcss_ahb_clk_src.clkr.hw,
3154                         },
3155                         .num_parents = 1,
3156                         .flags = CLK_SET_RATE_PARENT,
3157                         .ops = &clk_branch2_ops,
3158                 },
3159         },
3160 };
3161
3162 static struct clk_branch gcc_wcss_axi_m_clk = {
3163         .halt_reg = 0x5903c,
3164         .clkr = {
3165                 .enable_reg = 0x5903c,
3166                 .enable_mask = BIT(0),
3167                 .hw.init = &(struct clk_init_data) {
3168                         .name = "gcc_wcss_axi_m_clk",
3169                         .parent_hws = (const struct clk_hw *[]) {
3170                                 &system_noc_clk_src.hw,
3171                         },
3172                         .num_parents = 1,
3173                         .flags = CLK_SET_RATE_PARENT,
3174                         .ops = &clk_branch2_ops,
3175                 },
3176         },
3177 };
3178
3179 static struct clk_branch gcc_wcss_axi_s_clk = {
3180         .halt_reg = 0x59068,
3181         .clkr = {
3182                 .enable_reg = 0x59068,
3183                 .enable_mask = BIT(0),
3184                 .hw.init = &(struct clk_init_data) {
3185                         .name = "gcc_wi_s_clk",
3186                         .parent_hws = (const struct clk_hw *[]) {
3187                                 &system_noc_clk_src.hw,
3188                         },
3189                         .num_parents = 1,
3190                         .flags = CLK_SET_RATE_PARENT,
3191                         .ops = &clk_branch2_ops,
3192                 },
3193         },
3194 };
3195
3196 static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3197         .halt_reg = 0x59050,
3198         .clkr = {
3199                 .enable_reg = 0x59050,
3200                 .enable_mask = BIT(0),
3201                 .hw.init = &(struct clk_init_data) {
3202                         .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3203                         .parent_hws = (const struct clk_hw *[]) {
3204                                 &qdss_dap_sync_clk_src.hw,
3205                         },
3206                         .num_parents = 1,
3207                         .flags = CLK_SET_RATE_PARENT,
3208                         .ops = &clk_branch2_ops,
3209                 },
3210         },
3211 };
3212
3213 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3214         .halt_reg = 0x59040,
3215         .clkr = {
3216                 .enable_reg = 0x59040,
3217                 .enable_mask = BIT(0),
3218                 .hw.init = &(struct clk_init_data) {
3219                         .name = "gcc_wcss_dbg_ifc_apb_clk",
3220                         .parent_hws = (const struct clk_hw *[]) {
3221                                 &qdss_dap_sync_clk_src.hw,
3222                         },
3223                         .num_parents = 1,
3224                         .flags = CLK_SET_RATE_PARENT,
3225                         .ops = &clk_branch2_ops,
3226                 },
3227         },
3228 };
3229
3230 static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3231         .halt_reg = 0x59054,
3232         .clkr = {
3233                 .enable_reg = 0x59054,
3234                 .enable_mask = BIT(0),
3235                 .hw.init = &(struct clk_init_data) {
3236                         .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3237                         .parent_hws = (const struct clk_hw *[]) {
3238                                 &qdss_at_clk_src.clkr.hw,
3239                         },
3240                         .num_parents = 1,
3241                         .flags = CLK_SET_RATE_PARENT,
3242                         .ops = &clk_branch2_ops,
3243                 },
3244         },
3245 };
3246
3247 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3248         .halt_reg = 0x59044,
3249         .clkr = {
3250                 .enable_reg = 0x59044,
3251                 .enable_mask = BIT(0),
3252                 .hw.init = &(struct clk_init_data) {
3253                         .name = "gcc_wcss_dbg_ifc_atb_clk",
3254                         .parent_hws = (const struct clk_hw *[]) {
3255                                 &qdss_at_clk_src.clkr.hw,
3256                         },
3257                         .num_parents = 1,
3258                         .flags = CLK_SET_RATE_PARENT,
3259                         .ops = &clk_branch2_ops,
3260                 },
3261         },
3262 };
3263
3264 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
3265         .halt_reg = 0x59060,
3266         .clkr = {
3267                 .enable_reg = 0x59060,
3268                 .enable_mask = BIT(0),
3269                 .hw.init = &(struct clk_init_data) {
3270                         .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
3271                         .parent_hws = (const struct clk_hw *[]) {
3272                                 &qdss_dap_sync_clk_src.hw,
3273                         },
3274                         .num_parents = 1,
3275                         .flags = CLK_SET_RATE_PARENT,
3276                         .ops = &clk_branch2_ops,
3277                 },
3278         },
3279 };
3280
3281 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3282         .halt_reg = 0x5905c,
3283         .clkr = {
3284                 .enable_reg = 0x5905c,
3285                 .enable_mask = BIT(0),
3286                 .hw.init = &(struct clk_init_data) {
3287                         .name = "gcc_wcss_dbg_ifc_dapbus_clk",
3288                         .parent_hws = (const struct clk_hw *[]) {
3289                                 &qdss_dap_sync_clk_src.hw,
3290                         },
3291                         .num_parents = 1,
3292                         .flags = CLK_SET_RATE_PARENT,
3293                         .ops = &clk_branch2_ops,
3294                 },
3295         },
3296 };
3297
3298 static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3299         .halt_reg = 0x59058,
3300         .clkr = {
3301                 .enable_reg = 0x59058,
3302                 .enable_mask = BIT(0),
3303                 .hw.init = &(struct clk_init_data) {
3304                         .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3305                         .parent_hws = (const struct clk_hw *[]) {
3306                                 &qdss_tsctr_div2_clk_src.hw,
3307                         },
3308                         .num_parents = 1,
3309                         .flags = CLK_SET_RATE_PARENT,
3310                         .ops = &clk_branch2_ops,
3311                 },
3312         },
3313 };
3314
3315 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3316         .halt_reg = 0x59048,
3317         .clkr = {
3318                 .enable_reg = 0x59048,
3319                 .enable_mask = BIT(0),
3320                 .hw.init = &(struct clk_init_data) {
3321                         .name = "gcc_wcss_dbg_ifc_nts_clk",
3322                         .parent_hws = (const struct clk_hw *[]) {
3323                                 &qdss_tsctr_div2_clk_src.hw,
3324                         },
3325                         .num_parents = 1,
3326                         .flags = CLK_SET_RATE_PARENT,
3327                         .ops = &clk_branch2_ops,
3328                 },
3329         },
3330 };
3331
3332 static struct clk_branch gcc_wcss_ecahb_clk = {
3333         .halt_reg = 0x59038,
3334         .clkr = {
3335                 .enable_reg = 0x59038,
3336                 .enable_mask = BIT(0),
3337                 .hw.init = &(struct clk_init_data) {
3338                         .name = "gcc_wcss_ecahb_clk",
3339                         .parent_hws = (const struct clk_hw *[]) {
3340                                 &wcss_ahb_clk_src.clkr.hw,
3341                         },
3342                         .num_parents = 1,
3343                         .flags = CLK_SET_RATE_PARENT,
3344                         .ops = &clk_branch2_ops,
3345                 },
3346         },
3347 };
3348
3349 static struct clk_hw *gcc_ipq5018_hws[] = {
3350         &gpll0_out_main_div2.hw,
3351         &pcnoc_clk_src.hw,
3352         &system_noc_clk_src.hw,
3353         &qdss_dap_sync_clk_src.hw,
3354         &qdss_tsctr_div2_clk_src.hw,
3355         &eud_at_clk_src.hw,
3356 };
3357
3358 static const struct alpha_pll_config ubi32_pll_config = {
3359         .l = 0x29,
3360         .alpha = 0xaaaaaaaa,
3361         .alpha_hi = 0xaa,
3362         .config_ctl_val = 0x4001075b,
3363         .main_output_mask = BIT(0),
3364         .aux_output_mask = BIT(1),
3365         .alpha_en_mask = BIT(24),
3366         .vco_val = 0x1,
3367         .vco_mask = GENMASK(21, 20),
3368         .test_ctl_val = 0x0,
3369         .test_ctl_hi_val = 0x0,
3370 };
3371
3372 static struct clk_regmap *gcc_ipq5018_clks[] = {
3373         [GPLL0_MAIN] = &gpll0_main.clkr,
3374         [GPLL0] = &gpll0.clkr,
3375         [GPLL2_MAIN] = &gpll2_main.clkr,
3376         [GPLL2] = &gpll2.clkr,
3377         [GPLL4_MAIN] = &gpll4_main.clkr,
3378         [GPLL4] = &gpll4.clkr,
3379         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
3380         [UBI32_PLL] = &ubi32_pll.clkr,
3381         [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
3382         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3383         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3384         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3385         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3386         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3387         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3388         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3389         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3390         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3391         [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3392         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3393         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3394         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3395         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3396         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3397         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3398         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3399         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3400         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3401         [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
3402         [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
3403         [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
3404         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3405         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3406         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3407         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3408         [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
3409         [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
3410         [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
3411         [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
3412         [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
3413         [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
3414         [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
3415         [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
3416         [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
3417         [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
3418         [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
3419         [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
3420         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3421         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3422         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3423         [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3424         [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3425         [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
3426         [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
3427         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3428         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3429         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3430         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3431         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3432         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3433         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3434         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3435         [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3436         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3437         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3438         [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3439         [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
3440         [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3441         [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3442         [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3443         [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3444         [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3445         [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3446         [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3447         [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3448         [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3449         [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3450         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3451         [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3452         [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3453         [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3454         [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3455         [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3456         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3457         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3458         [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3459         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3460         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3461         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3462         [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
3463         [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
3464         [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
3465         [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
3466         [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
3467         [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
3468         [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
3469         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
3470         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
3471         [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3472         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
3473         [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3474         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
3475         [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
3476         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
3477         [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
3478         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
3479         [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
3480         [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
3481         [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
3482         [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
3483         [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
3484         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3485         [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3486         [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3487         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3488         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3489         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3490         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3491         [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
3492         [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
3493         [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
3494         [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
3495         [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3496         [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3497         [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3498         [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3499         [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
3500         [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
3501         [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3502         [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3503         [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3504         [GCC_XO_CLK] = &gcc_xo_clk.clkr,
3505         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3506         [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
3507         [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
3508         [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
3509         [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
3510         [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
3511         [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
3512         [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
3513         [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
3514         [GMAC_CLK_SRC] = &gmac_clk_src.clkr,
3515         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3516         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3517         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3518         [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
3519         [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
3520         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
3521         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
3522         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
3523         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
3524         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3525         [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
3526         [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3527         [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3528         [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3529         [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3530         [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
3531         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3532         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3533         [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
3534         [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
3535         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3536         [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
3537         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3538         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3539         [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3540         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3541         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3542         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3543         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3544         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3545         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3546 };
3547
3548 static const struct qcom_reset_map gcc_ipq5018_resets[] = {
3549         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3550         [GCC_BLSP1_BCR] = { 0x01000, 0 },
3551         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3552         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3553         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3554         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3555         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3556         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3557         [GCC_BTSS_BCR] = { 0x1c000, 0 },
3558         [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3559         [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3560         [GCC_CE_BCR] = { 0x33014, 0 },
3561         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3562         [GCC_DCC_BCR] = { 0x77000, 0 },
3563         [GCC_DCD_BCR] = { 0x2a000, 0 },
3564         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
3565         [GCC_EDPD_BCR] = { 0x3a000, 0 },
3566         [GCC_GEPHY_BCR] = { 0x56000, 0 },
3567         [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3568         [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3569         [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3570         [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3571         [GCC_GMAC0_BCR] = { 0x19000, 0 },
3572         [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3573         [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3574         [GCC_GMAC1_BCR] = { 0x19100, 0 },
3575         [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3576         [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3577         [GCC_IMEM_BCR] = { 0x0e000, 0 },
3578         [GCC_LPASS_BCR] = { 0x2e000, 0 },
3579         [GCC_MDIO0_BCR] = { 0x58000, 0 },
3580         [GCC_MDIO1_BCR] = { 0x58010, 0 },
3581         [GCC_MPM_BCR] = { 0x2c000, 0 },
3582         [GCC_PCIE0_BCR] = { 0x75004, 0 },
3583         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3584         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3585         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3586         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3587         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3588         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3589         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3590         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3591         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3592         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3593         [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3594         [GCC_PCIE1_BCR] = { 0x76004, 0 },
3595         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3596         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3597         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3598         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3599         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3600         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3601         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3602         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3603         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3604         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3605         [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3606         [GCC_PCNOC_BCR] = { 0x27018, 0 },
3607         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3608         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3609         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3610         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3611         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3612         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3613         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3614         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3615         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3616         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3617         [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3618         [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3619         [GCC_PRNG_BCR] = { 0x13000, 0 },
3620         [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3621         [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3622         [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3623         [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3624         [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3625         [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3626         [GCC_QDSS_BCR] = { 0x29000, 0 },
3627         [GCC_QPIC_BCR] = { 0x57018, 0 },
3628         [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3629         [GCC_SDCC1_BCR] = { 0x42000, 0 },
3630         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3631         [GCC_SPDM_BCR] = { 0x2f000, 0 },
3632         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3633         [GCC_TCSR_BCR] = { 0x28000, 0 },
3634         [GCC_TLMM_BCR] = { 0x34000, 0 },
3635         [GCC_UBI0_AXI_ARES] = { 0x680},
3636         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3637         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3638         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3639         [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3640         [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3641         [GCC_UBI32_BCR] = { 0x19064, 0 },
3642         [GCC_UNIPHY_BCR] = { 0x56100, 0 },
3643         [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3644         [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3645         [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3646         [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3647         [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3648         [GCC_USB0_BCR] = { 0x3e070, 0 },
3649         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3650         [GCC_WCSS_BCR] = { 0x18000, 0 },
3651         [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3652         [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3653         [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3654         [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3655         [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3656         [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3657         [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3658         [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3659         [GCC_WCSSAON_RESET] = { 0x59010, 0},
3660         [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3661 };
3662
3663 static const struct of_device_id gcc_ipq5018_match_table[] = {
3664         { .compatible = "qcom,gcc-ipq5018" },
3665         { }
3666 };
3667 MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
3668
3669 static const struct regmap_config gcc_ipq5018_regmap_config = {
3670         .reg_bits = 32,
3671         .reg_stride = 4,
3672         .val_bits = 32,
3673         .max_register = 0x7fffc,
3674         .fast_io = true,
3675 };
3676
3677 static const struct qcom_cc_desc gcc_ipq5018_desc = {
3678         .config = &gcc_ipq5018_regmap_config,
3679         .clks = gcc_ipq5018_clks,
3680         .num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
3681         .resets = gcc_ipq5018_resets,
3682         .num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
3683         .clk_hws = gcc_ipq5018_hws,
3684         .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
3685 };
3686
3687 static int gcc_ipq5018_probe(struct platform_device *pdev)
3688 {
3689         struct regmap *regmap;
3690         struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
3691
3692         regmap = qcom_cc_map(pdev, &ipq5018_desc);
3693         if (IS_ERR(regmap))
3694                 return PTR_ERR(regmap);
3695
3696         clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3697
3698         return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
3699 }
3700
3701 static struct platform_driver gcc_ipq5018_driver = {
3702         .probe = gcc_ipq5018_probe,
3703         .driver = {
3704                 .name = "qcom,gcc-ipq5018",
3705                 .of_match_table = gcc_ipq5018_match_table,
3706         },
3707 };
3708
3709 static int __init gcc_ipq5018_init(void)
3710 {
3711         return platform_driver_register(&gcc_ipq5018_driver);
3712 }
3713 core_initcall(gcc_ipq5018_init);
3714
3715 static void __exit gcc_ipq5018_exit(void)
3716 {
3717         platform_driver_unregister(&gcc_ipq5018_driver);
3718 }
3719 module_exit(gcc_ipq5018_exit);
3720
3721 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
3722 MODULE_LICENSE("GPL");