2 * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/bug.h>
18 #include <linux/device.h>
19 #include <linux/kernel.h>
21 #include <soc/tegra/fuse.h>
25 #define SOC_PROCESS_CORNERS 1
26 #define CPU_PROCESS_CORNERS 6
28 #define FUSE_SPEEDO_CALIB_0 0x14
29 #define FUSE_PACKAGE_INFO 0XFC
30 #define FUSE_TEST_PROG_VER 0X28
32 #define G_SPEEDO_BIT_MINUS1 58
33 #define G_SPEEDO_BIT_MINUS1_R 59
34 #define G_SPEEDO_BIT_MINUS2 60
35 #define G_SPEEDO_BIT_MINUS2_R 61
36 #define LP_SPEEDO_BIT_MINUS1 62
37 #define LP_SPEEDO_BIT_MINUS1_R 63
38 #define LP_SPEEDO_BIT_MINUS2 64
39 #define LP_SPEEDO_BIT_MINUS2_R 65
54 THRESHOLD_INDEX_COUNT,
57 static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
72 static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
73 {306, 338, 360, 376, UINT_MAX},
74 {295, 336, 358, 375, UINT_MAX},
75 {325, 325, 358, 375, UINT_MAX},
76 {325, 325, 358, 375, UINT_MAX},
77 {292, 324, 348, 364, UINT_MAX},
78 {324, 324, 348, 364, UINT_MAX},
79 {324, 324, 348, 364, UINT_MAX},
80 {295, 336, 358, 375, UINT_MAX},
81 {358, 358, 358, 358, 397, UINT_MAX},
82 {364, 364, 364, 364, 397, UINT_MAX},
83 {295, 336, 358, 375, 391, UINT_MAX},
84 {295, 336, 358, 375, 391, UINT_MAX},
87 static int threshold_index __initdata;
89 static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
96 reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
98 *speedo_lp = (reg & 0xFFFF) * 4;
99 *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
101 ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
102 pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
105 bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
106 bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
107 bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
108 bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
109 *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
111 bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
112 bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
113 bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
114 bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
115 *speedo_g |= (bit_minus1 << 1) | bit_minus2;
122 static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
124 int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
126 switch (sku_info->revision) {
127 case TEGRA_REVISION_A01:
128 sku_info->cpu_speedo_id = 0;
129 sku_info->soc_speedo_id = 0;
130 threshold_index = THRESHOLD_INDEX_0;
132 case TEGRA_REVISION_A02:
133 case TEGRA_REVISION_A03:
134 switch (sku_info->sku_id) {
137 sku_info->cpu_speedo_id = 1;
138 sku_info->soc_speedo_id = 1;
139 threshold_index = THRESHOLD_INDEX_1;
142 switch (package_id) {
144 sku_info->cpu_speedo_id = 2;
145 sku_info->soc_speedo_id = 2;
146 threshold_index = THRESHOLD_INDEX_2;
149 sku_info->cpu_speedo_id = 4;
150 sku_info->soc_speedo_id = 1;
151 threshold_index = THRESHOLD_INDEX_7;
154 pr_err("Tegra Unknown pkg %d\n", package_id);
159 switch (package_id) {
161 sku_info->cpu_speedo_id = 5;
162 sku_info->soc_speedo_id = 2;
163 threshold_index = THRESHOLD_INDEX_8;
166 sku_info->cpu_speedo_id = 6;
167 sku_info->soc_speedo_id = 2;
168 threshold_index = THRESHOLD_INDEX_9;
171 pr_err("Tegra Unknown pkg %d\n", package_id);
176 switch (package_id) {
178 sku_info->cpu_speedo_id = 7;
179 sku_info->soc_speedo_id = 1;
180 threshold_index = THRESHOLD_INDEX_10;
183 sku_info->cpu_speedo_id = 3;
184 sku_info->soc_speedo_id = 2;
185 threshold_index = THRESHOLD_INDEX_3;
188 pr_err("Tegra Unknown pkg %d\n", package_id);
193 sku_info->cpu_speedo_id = 8;
194 sku_info->soc_speedo_id = 1;
195 threshold_index = THRESHOLD_INDEX_11;
198 sku_info->cpu_speedo_id = 1;
199 sku_info->soc_speedo_id = 1;
200 threshold_index = THRESHOLD_INDEX_4;
203 sku_info->cpu_speedo_id = 2;
204 sku_info->soc_speedo_id = 2;
205 threshold_index = THRESHOLD_INDEX_5;
208 sku_info->cpu_speedo_id = 3;
209 sku_info->soc_speedo_id = 2;
210 threshold_index = THRESHOLD_INDEX_6;
213 switch (package_id) {
215 sku_info->cpu_speedo_id = 2;
216 sku_info->soc_speedo_id = 2;
217 threshold_index = THRESHOLD_INDEX_2;
220 sku_info->cpu_speedo_id = 3;
221 sku_info->soc_speedo_id = 2;
222 threshold_index = THRESHOLD_INDEX_3;
225 pr_err("Tegra Unknown pkg %d\n", package_id);
230 pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id);
231 sku_info->cpu_speedo_id = 0;
232 sku_info->soc_speedo_id = 0;
233 threshold_index = THRESHOLD_INDEX_0;
238 pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision);
239 sku_info->cpu_speedo_id = 0;
240 sku_info->soc_speedo_id = 0;
241 threshold_index = THRESHOLD_INDEX_0;
246 void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
252 BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
253 THRESHOLD_INDEX_COUNT);
254 BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
255 THRESHOLD_INDEX_COUNT);
258 rev_sku_to_speedo_ids(sku_info);
259 fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
260 pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
261 pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
263 for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
264 if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
267 sku_info->cpu_process_id = i - 1;
269 if (sku_info->cpu_process_id == -1) {
270 pr_warn("Tegra CPU speedo value %3d out of range",
272 sku_info->cpu_process_id = 0;
273 sku_info->cpu_speedo_id = 1;
276 for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
277 if (soc_speedo_val < soc_process_speedos[threshold_index][i])
280 sku_info->soc_process_id = i - 1;
282 if (sku_info->soc_process_id == -1) {
283 pr_warn("Tegra SoC speedo value %3d out of range",
285 sku_info->soc_process_id = 0;
286 sku_info->soc_speedo_id = 1;