1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
8 #include <linux/dmaengine.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_platform.h>
12 #include <sound/dmaengine_pcm.h>
13 #include <sound/pcm_params.h>
18 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
19 SNDRV_PCM_FMTBIT_S16_LE | \
20 SNDRV_PCM_FMTBIT_S20_3LE | \
21 SNDRV_PCM_FMTBIT_S24_LE)
24 * fsl_esai: ESAI private data
26 * @dma_params_rx: DMA parameters for receive channel
27 * @dma_params_tx: DMA parameters for transmit channel
28 * @pdev: platform device pointer
29 * @regmap: regmap handler
30 * @coreclk: clock source to access register
31 * @extalclk: esai clock source to derive HCK, SCK and FS
32 * @fsysclk: system clock source to derive HCK, SCK and FS
33 * @spbaclk: SPBA clock (optional, depending on SoC design)
34 * @fifo_depth: depth of tx/rx FIFO
35 * @slot_width: width of each DAI slot
36 * @slots: number of slots
37 * @hck_rate: clock rate of desired HCKx clock
38 * @sck_rate: clock rate of desired SCKx clock
39 * @hck_dir: the direction of HCKx pads
40 * @sck_div: if using PSR/PM dividers for SCKx clock
41 * @slave_mode: if fully using DAI slave mode
42 * @synchronous: if using tx/rx synchronous mode
46 struct snd_dmaengine_dai_dma_data dma_params_rx;
47 struct snd_dmaengine_dai_dma_data dma_params_tx;
48 struct platform_device *pdev;
49 struct regmap *regmap;
68 static irqreturn_t esai_isr(int irq, void *devid)
70 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
71 struct platform_device *pdev = esai_priv->pdev;
74 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
76 if (esr & ESAI_ESR_TINIT_MASK)
77 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
79 if (esr & ESAI_ESR_RFF_MASK)
80 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
82 if (esr & ESAI_ESR_TFE_MASK)
83 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
85 if (esr & ESAI_ESR_TLS_MASK)
86 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
88 if (esr & ESAI_ESR_TDE_MASK)
89 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
91 if (esr & ESAI_ESR_TED_MASK)
92 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
94 if (esr & ESAI_ESR_TD_MASK)
95 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
97 if (esr & ESAI_ESR_RLS_MASK)
98 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
100 if (esr & ESAI_ESR_RDE_MASK)
101 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
103 if (esr & ESAI_ESR_RED_MASK)
104 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
106 if (esr & ESAI_ESR_RD_MASK)
107 dev_dbg(&pdev->dev, "isr: Receiving data\n");
113 * This function is used to calculate the divisors of psr, pm, fp and it is
114 * supposed to be called in set_dai_sysclk() and set_bclk().
116 * @ratio: desired overall ratio for the paticipating dividers
117 * @usefp: for HCK setting, there is no need to set fp divider
118 * @fp: bypass other dividers by setting fp directly if fp != 0
119 * @tx: current setting is for playback or capture
121 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
124 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
125 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
127 maxfp = usefp ? 16 : 1;
132 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
133 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
134 2 * 8 * 256 * maxfp);
136 } else if (ratio % 2) {
137 dev_err(dai->dev, "the raio must be even if using upper divider\n");
143 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
145 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
152 /* Set the max fluctuation -- 0.1% of the max devisor */
153 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
155 /* Find the best value for PM */
156 for (i = 1; i <= 256; i++) {
157 for (j = 1; j <= maxfp; j++) {
158 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
159 prod = (psr ? 1 : 8) * i * j;
163 else if (prod / ratio == 1)
165 else if (ratio / prod == 1)
170 /* Calculate the fraction */
171 sub = sub * 1000 / ratio;
185 dev_err(dai->dev, "failed to calculate proper divisors\n");
190 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
191 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
192 psr | ESAI_xCCR_xPM(pm));
195 /* Bypass fp if not being required */
199 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
200 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
206 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
209 * clk_id: The clock source of HCKT/HCKR
210 * (Input from outside; output from inside, FSYS or EXTAL)
211 * freq: The required clock rate of HCKT/HCKR
212 * dir: The clock direction of HCKT/HCKR
214 * Note: If the direction is input, we do not care about clk_id.
216 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
217 unsigned int freq, int dir)
219 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
220 struct clk *clksrc = esai_priv->extalclk;
221 bool tx = clk_id <= ESAI_HCKT_EXTAL;
222 bool in = dir == SND_SOC_CLOCK_IN;
224 unsigned long clk_rate;
228 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
229 in ? "in" : "out", tx ? 'T' : 'R');
233 /* Bypass divider settings if the requirement doesn't change */
234 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
237 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
238 esai_priv->sck_div[tx] = true;
240 /* Set the direction of HCKT/HCKR pins */
241 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
242 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
250 clksrc = esai_priv->fsysclk;
252 case ESAI_HCKT_EXTAL:
255 case ESAI_HCKR_EXTAL:
262 if (IS_ERR(clksrc)) {
263 dev_err(dai->dev, "no assigned %s clock\n",
264 clk_id % 2 ? "extal" : "fsys");
265 return PTR_ERR(clksrc);
267 clk_rate = clk_get_rate(clksrc);
269 ratio = clk_rate / freq;
270 if (ratio * freq > clk_rate)
271 ret = ratio * freq - clk_rate;
272 else if (ratio * freq < clk_rate)
273 ret = clk_rate - ratio * freq;
277 /* Block if clock source can not be divided into the required rate */
278 if (ret != 0 && clk_rate / ret < 1000) {
279 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
284 /* Only EXTAL source can be output directly without using PSR and PM */
285 if (ratio == 1 && clksrc == esai_priv->extalclk) {
286 /* Bypass all the dividers if not being needed */
287 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
289 } else if (ratio < 2) {
290 /* The ratio should be no less than 2 if using other sources */
291 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
296 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
300 esai_priv->sck_div[tx] = false;
303 esai_priv->hck_dir[tx] = dir;
304 esai_priv->hck_rate[tx] = freq;
306 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
307 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
308 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
314 * This function configures the related dividers according to the bclk rate
316 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
318 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
319 u32 hck_rate = esai_priv->hck_rate[tx];
320 u32 sub, ratio = hck_rate / freq;
323 /* Don't apply for fully slave mode or unchanged bclk */
324 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
327 if (ratio * freq > hck_rate)
328 sub = ratio * freq - hck_rate;
329 else if (ratio * freq < hck_rate)
330 sub = hck_rate - ratio * freq;
334 /* Block if clock source can not be divided into the required rate */
335 if (sub != 0 && hck_rate / sub < 1000) {
336 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
341 /* The ratio should be contented by FP alone if bypassing PM and PSR */
342 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
343 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
347 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
348 esai_priv->sck_div[tx] ? 0 : ratio);
352 /* Save current bclk rate */
353 esai_priv->sck_rate[tx] = freq;
358 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
359 u32 rx_mask, int slots, int slot_width)
361 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
364 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
366 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
367 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
369 esai_priv->slot_width = slot_width;
370 esai_priv->slots = slots;
371 esai_priv->tx_mask = tx_mask;
372 esai_priv->rx_mask = rx_mask;
377 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
379 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
380 u32 xcr = 0, xccr = 0, mask;
383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
384 case SND_SOC_DAIFMT_I2S:
385 /* Data on rising edge of bclk, frame low, 1clk before data */
386 xcr |= ESAI_xCR_xFSR;
387 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
389 case SND_SOC_DAIFMT_LEFT_J:
390 /* Data on rising edge of bclk, frame high */
391 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
393 case SND_SOC_DAIFMT_RIGHT_J:
394 /* Data on rising edge of bclk, frame high, right aligned */
395 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
398 case SND_SOC_DAIFMT_DSP_A:
399 /* Data on rising edge of bclk, frame high, 1clk before data */
400 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
401 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
403 case SND_SOC_DAIFMT_DSP_B:
404 /* Data on rising edge of bclk, frame high */
405 xcr |= ESAI_xCR_xFSL;
406 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
412 /* DAI clock inversion */
413 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
414 case SND_SOC_DAIFMT_NB_NF:
415 /* Nothing to do for both normal cases */
417 case SND_SOC_DAIFMT_IB_NF:
418 /* Invert bit clock */
419 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
421 case SND_SOC_DAIFMT_NB_IF:
422 /* Invert frame clock */
423 xccr ^= ESAI_xCCR_xFSP;
425 case SND_SOC_DAIFMT_IB_IF:
426 /* Invert both clocks */
427 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
433 esai_priv->slave_mode = false;
435 /* DAI clock master masks */
436 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
437 case SND_SOC_DAIFMT_CBM_CFM:
438 esai_priv->slave_mode = true;
440 case SND_SOC_DAIFMT_CBS_CFM:
441 xccr |= ESAI_xCCR_xCKD;
443 case SND_SOC_DAIFMT_CBM_CFS:
444 xccr |= ESAI_xCCR_xFSD;
446 case SND_SOC_DAIFMT_CBS_CFS:
447 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
453 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
454 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
455 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
457 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
458 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
459 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
460 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
465 static int fsl_esai_startup(struct snd_pcm_substream *substream,
466 struct snd_soc_dai *dai)
468 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
472 * Some platforms might use the same bit to gate all three or two of
473 * clocks, so keep all clocks open/close at the same time for safety
475 ret = clk_prepare_enable(esai_priv->coreclk);
478 if (!IS_ERR(esai_priv->spbaclk)) {
479 ret = clk_prepare_enable(esai_priv->spbaclk);
483 if (!IS_ERR(esai_priv->extalclk)) {
484 ret = clk_prepare_enable(esai_priv->extalclk);
488 if (!IS_ERR(esai_priv->fsysclk)) {
489 ret = clk_prepare_enable(esai_priv->fsysclk);
495 /* Set synchronous mode */
496 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
497 ESAI_SAICR_SYNC, esai_priv->synchronous ?
498 ESAI_SAICR_SYNC : 0);
500 /* Set slots count */
501 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
503 ESAI_xCCR_xDC(esai_priv->slots));
504 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
506 ESAI_xCCR_xDC(esai_priv->slots));
512 if (!IS_ERR(esai_priv->extalclk))
513 clk_disable_unprepare(esai_priv->extalclk);
515 if (!IS_ERR(esai_priv->spbaclk))
516 clk_disable_unprepare(esai_priv->spbaclk);
518 clk_disable_unprepare(esai_priv->coreclk);
523 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
524 struct snd_pcm_hw_params *params,
525 struct snd_soc_dai *dai)
527 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
528 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
529 u32 width = params_width(params);
530 u32 channels = params_channels(params);
531 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
532 u32 slot_width = width;
536 /* Override slot_width if being specifically set */
537 if (esai_priv->slot_width)
538 slot_width = esai_priv->slot_width;
540 bclk = params_rate(params) * slot_width * esai_priv->slots;
542 ret = fsl_esai_set_bclk(dai, tx, bclk);
546 /* Use Normal mode to support monaural audio */
547 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
548 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
549 ESAI_xCR_xMOD_NETWORK : 0);
551 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
552 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
554 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
555 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
556 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
557 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
559 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
561 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
562 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
566 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
567 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
568 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
569 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
570 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
574 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
575 struct snd_soc_dai *dai)
577 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
579 if (!IS_ERR(esai_priv->fsysclk))
580 clk_disable_unprepare(esai_priv->fsysclk);
581 if (!IS_ERR(esai_priv->extalclk))
582 clk_disable_unprepare(esai_priv->extalclk);
583 if (!IS_ERR(esai_priv->spbaclk))
584 clk_disable_unprepare(esai_priv->spbaclk);
585 clk_disable_unprepare(esai_priv->coreclk);
588 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
589 struct snd_soc_dai *dai)
591 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
592 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
593 u8 i, channels = substream->runtime->channels;
594 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
598 case SNDRV_PCM_TRIGGER_START:
599 case SNDRV_PCM_TRIGGER_RESUME:
600 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
601 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
602 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
604 /* Write initial words reqiured by ESAI as normal procedure */
605 for (i = 0; tx && i < channels; i++)
606 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
609 * When set the TE/RE in the end of enablement flow, there
610 * will be channel swap issue for multi data line case.
611 * In order to workaround this issue, we switch the bit
612 * enablement sequence to below sequence
613 * 1) clear the xSMB & xSMA: which is done in probe and
617 * 4) set xSMA: xSMA is the last one in this flow, which
618 * will trigger esai to start.
620 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
621 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
622 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
623 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
625 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
626 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
627 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
628 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
631 case SNDRV_PCM_TRIGGER_SUSPEND:
632 case SNDRV_PCM_TRIGGER_STOP:
633 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
634 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
635 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
636 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
637 ESAI_xSMA_xS_MASK, 0);
638 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
639 ESAI_xSMB_xS_MASK, 0);
641 /* Disable and reset FIFO */
642 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
643 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
644 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
654 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
655 .startup = fsl_esai_startup,
656 .shutdown = fsl_esai_shutdown,
657 .trigger = fsl_esai_trigger,
658 .hw_params = fsl_esai_hw_params,
659 .set_sysclk = fsl_esai_set_dai_sysclk,
660 .set_fmt = fsl_esai_set_dai_fmt,
661 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
664 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
666 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
668 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
669 &esai_priv->dma_params_rx);
674 static struct snd_soc_dai_driver fsl_esai_dai = {
675 .probe = fsl_esai_dai_probe,
677 .stream_name = "CPU-Playback",
680 .rates = SNDRV_PCM_RATE_8000_192000,
681 .formats = FSL_ESAI_FORMATS,
684 .stream_name = "CPU-Capture",
687 .rates = SNDRV_PCM_RATE_8000_192000,
688 .formats = FSL_ESAI_FORMATS,
690 .ops = &fsl_esai_dai_ops,
693 static const struct snd_soc_component_driver fsl_esai_component = {
697 static const struct reg_default fsl_esai_reg_defaults[] = {
698 {REG_ESAI_ETDR, 0x00000000},
699 {REG_ESAI_ECR, 0x00000000},
700 {REG_ESAI_TFCR, 0x00000000},
701 {REG_ESAI_RFCR, 0x00000000},
702 {REG_ESAI_TX0, 0x00000000},
703 {REG_ESAI_TX1, 0x00000000},
704 {REG_ESAI_TX2, 0x00000000},
705 {REG_ESAI_TX3, 0x00000000},
706 {REG_ESAI_TX4, 0x00000000},
707 {REG_ESAI_TX5, 0x00000000},
708 {REG_ESAI_TSR, 0x00000000},
709 {REG_ESAI_SAICR, 0x00000000},
710 {REG_ESAI_TCR, 0x00000000},
711 {REG_ESAI_TCCR, 0x00000000},
712 {REG_ESAI_RCR, 0x00000000},
713 {REG_ESAI_RCCR, 0x00000000},
714 {REG_ESAI_TSMA, 0x0000ffff},
715 {REG_ESAI_TSMB, 0x0000ffff},
716 {REG_ESAI_RSMA, 0x0000ffff},
717 {REG_ESAI_RSMB, 0x0000ffff},
718 {REG_ESAI_PRRC, 0x00000000},
719 {REG_ESAI_PCRC, 0x00000000},
722 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
754 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
772 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
803 static const struct regmap_config fsl_esai_regmap_config = {
808 .max_register = REG_ESAI_PCRC,
809 .reg_defaults = fsl_esai_reg_defaults,
810 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
811 .readable_reg = fsl_esai_readable_reg,
812 .volatile_reg = fsl_esai_volatile_reg,
813 .writeable_reg = fsl_esai_writeable_reg,
814 .cache_type = REGCACHE_FLAT,
817 static int fsl_esai_probe(struct platform_device *pdev)
819 struct device_node *np = pdev->dev.of_node;
820 struct fsl_esai *esai_priv;
821 struct resource *res;
826 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
830 esai_priv->pdev = pdev;
831 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
833 /* Get the addresses and IRQ */
834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
835 regs = devm_ioremap_resource(&pdev->dev, res);
837 return PTR_ERR(regs);
839 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
840 "core", regs, &fsl_esai_regmap_config);
841 if (IS_ERR(esai_priv->regmap)) {
842 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
843 PTR_ERR(esai_priv->regmap));
844 return PTR_ERR(esai_priv->regmap);
847 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
848 if (IS_ERR(esai_priv->coreclk)) {
849 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
850 PTR_ERR(esai_priv->coreclk));
851 return PTR_ERR(esai_priv->coreclk);
854 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
855 if (IS_ERR(esai_priv->extalclk))
856 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
857 PTR_ERR(esai_priv->extalclk));
859 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
860 if (IS_ERR(esai_priv->fsysclk))
861 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
862 PTR_ERR(esai_priv->fsysclk));
864 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
865 if (IS_ERR(esai_priv->spbaclk))
866 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
867 PTR_ERR(esai_priv->spbaclk));
869 irq = platform_get_irq(pdev, 0);
871 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
875 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
876 esai_priv->name, esai_priv);
878 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
882 /* Set a default slot number */
883 esai_priv->slots = 2;
885 /* Set a default master/slave state */
886 esai_priv->slave_mode = true;
888 /* Determine the FIFO depth */
889 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
891 esai_priv->fifo_depth = be32_to_cpup(iprop);
893 esai_priv->fifo_depth = 64;
895 esai_priv->dma_params_tx.maxburst = 16;
896 esai_priv->dma_params_rx.maxburst = 16;
897 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
898 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
900 esai_priv->synchronous =
901 of_property_read_bool(np, "fsl,esai-synchronous");
903 /* Implement full symmetry for synchronous mode */
904 if (esai_priv->synchronous) {
905 fsl_esai_dai.symmetric_rates = 1;
906 fsl_esai_dai.symmetric_channels = 1;
907 fsl_esai_dai.symmetric_samplebits = 1;
910 dev_set_drvdata(&pdev->dev, esai_priv);
912 /* Reset ESAI unit */
913 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
915 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
920 * We need to enable ESAI so as to access some of its registers.
921 * Otherwise, we would fail to dump regmap from user space.
923 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
925 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
929 esai_priv->tx_mask = 0xFFFFFFFF;
930 esai_priv->rx_mask = 0xFFFFFFFF;
932 /* Clear the TSMA, TSMB, RSMA, RSMB */
933 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
934 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
935 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
936 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
938 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
941 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
945 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
947 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
952 static const struct of_device_id fsl_esai_dt_ids[] = {
953 { .compatible = "fsl,imx35-esai", },
954 { .compatible = "fsl,vf610-esai", },
957 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
959 #ifdef CONFIG_PM_SLEEP
960 static int fsl_esai_suspend(struct device *dev)
962 struct fsl_esai *esai = dev_get_drvdata(dev);
964 regcache_cache_only(esai->regmap, true);
965 regcache_mark_dirty(esai->regmap);
970 static int fsl_esai_resume(struct device *dev)
972 struct fsl_esai *esai = dev_get_drvdata(dev);
975 regcache_cache_only(esai->regmap, false);
977 /* FIFO reset for safety */
978 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
979 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
980 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
981 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
983 ret = regcache_sync(esai->regmap);
987 /* FIFO reset done */
988 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
989 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
993 #endif /* CONFIG_PM_SLEEP */
995 static const struct dev_pm_ops fsl_esai_pm_ops = {
996 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
999 static struct platform_driver fsl_esai_driver = {
1000 .probe = fsl_esai_probe,
1002 .name = "fsl-esai-dai",
1003 .pm = &fsl_esai_pm_ops,
1004 .of_match_table = fsl_esai_dt_ids,
1008 module_platform_driver(fsl_esai_driver);
1010 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1011 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1012 MODULE_LICENSE("GPL v2");
1013 MODULE_ALIAS("platform:fsl-esai-dai");