1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/regmap.h>
13 #include <linux/slab.h>
14 #include <linux/time.h>
15 #include <sound/core.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
27 static const unsigned int fsl_sai_rates[] = {
28 8000, 11025, 12000, 16000, 22050,
29 24000, 32000, 44100, 48000, 64000,
30 88200, 96000, 176400, 192000
33 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
34 .count = ARRAY_SIZE(fsl_sai_rates),
35 .list = fsl_sai_rates,
38 static irqreturn_t fsl_sai_isr(int irq, void *devid)
40 struct fsl_sai *sai = (struct fsl_sai *)devid;
41 struct device *dev = &sai->pdev->dev;
42 u32 flags, xcsr, mask;
46 * Both IRQ status bits and IRQ mask bits are in the xCSR but
47 * different shifts. And we here create a mask only for those
48 * IRQs that we activated.
50 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
53 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
61 if (flags & FSL_SAI_CSR_WSF)
62 dev_dbg(dev, "isr: Start of Tx word detected\n");
64 if (flags & FSL_SAI_CSR_SEF)
65 dev_warn(dev, "isr: Tx Frame sync error detected\n");
67 if (flags & FSL_SAI_CSR_FEF) {
68 dev_warn(dev, "isr: Transmit underrun detected\n");
69 /* FIFO reset for safety */
70 xcsr |= FSL_SAI_CSR_FR;
73 if (flags & FSL_SAI_CSR_FWF)
74 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
76 if (flags & FSL_SAI_CSR_FRF)
77 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
79 flags &= FSL_SAI_CSR_xF_W_MASK;
80 xcsr &= ~FSL_SAI_CSR_xF_MASK;
83 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
87 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
95 if (flags & FSL_SAI_CSR_WSF)
96 dev_dbg(dev, "isr: Start of Rx word detected\n");
98 if (flags & FSL_SAI_CSR_SEF)
99 dev_warn(dev, "isr: Rx Frame sync error detected\n");
101 if (flags & FSL_SAI_CSR_FEF) {
102 dev_warn(dev, "isr: Receive overflow detected\n");
103 /* FIFO reset for safety */
104 xcsr |= FSL_SAI_CSR_FR;
107 if (flags & FSL_SAI_CSR_FWF)
108 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
110 if (flags & FSL_SAI_CSR_FRF)
111 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
113 flags &= FSL_SAI_CSR_xF_W_MASK;
114 xcsr &= ~FSL_SAI_CSR_xF_MASK;
117 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
126 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
127 u32 rx_mask, int slots, int slot_width)
129 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
132 sai->slot_width = slot_width;
137 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
138 int clk_id, unsigned int freq, int fsl_dir)
140 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
141 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
145 case FSL_SAI_CLK_BUS:
146 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
148 case FSL_SAI_CLK_MAST1:
149 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
151 case FSL_SAI_CLK_MAST2:
152 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
154 case FSL_SAI_CLK_MAST3:
155 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
161 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
162 FSL_SAI_CR2_MSEL_MASK, val_cr2);
167 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
168 int clk_id, unsigned int freq, int dir)
172 if (dir == SND_SOC_CLOCK_IN)
175 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
176 FSL_FMT_TRANSMITTER);
178 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
182 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
185 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
190 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
191 unsigned int fmt, int fsl_dir)
193 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
194 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
195 u32 val_cr2 = 0, val_cr4 = 0;
197 if (!sai->is_lsb_first)
198 val_cr4 |= FSL_SAI_CR4_MF;
201 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
202 case SND_SOC_DAIFMT_I2S:
204 * Frame low, 1clk before data, one word length for frame sync,
205 * frame sync starts one serial clock cycle earlier,
206 * that is, together with the last bit of the previous
209 val_cr2 |= FSL_SAI_CR2_BCP;
210 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
212 case SND_SOC_DAIFMT_LEFT_J:
214 * Frame high, one word length for frame sync,
215 * frame sync asserts with the first bit of the frame.
217 val_cr2 |= FSL_SAI_CR2_BCP;
219 case SND_SOC_DAIFMT_DSP_A:
221 * Frame high, 1clk before data, one bit for frame sync,
222 * frame sync starts one serial clock cycle earlier,
223 * that is, together with the last bit of the previous
226 val_cr2 |= FSL_SAI_CR2_BCP;
227 val_cr4 |= FSL_SAI_CR4_FSE;
228 sai->is_dsp_mode = true;
230 case SND_SOC_DAIFMT_DSP_B:
232 * Frame high, one bit for frame sync,
233 * frame sync asserts with the first bit of the frame.
235 val_cr2 |= FSL_SAI_CR2_BCP;
236 sai->is_dsp_mode = true;
238 case SND_SOC_DAIFMT_RIGHT_J:
244 /* DAI clock inversion */
245 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
246 case SND_SOC_DAIFMT_IB_IF:
247 /* Invert both clocks */
248 val_cr2 ^= FSL_SAI_CR2_BCP;
249 val_cr4 ^= FSL_SAI_CR4_FSP;
251 case SND_SOC_DAIFMT_IB_NF:
252 /* Invert bit clock */
253 val_cr2 ^= FSL_SAI_CR2_BCP;
255 case SND_SOC_DAIFMT_NB_IF:
256 /* Invert frame clock */
257 val_cr4 ^= FSL_SAI_CR4_FSP;
259 case SND_SOC_DAIFMT_NB_NF:
260 /* Nothing to do for both normal cases */
266 /* DAI clock master masks */
267 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
268 case SND_SOC_DAIFMT_CBS_CFS:
269 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
270 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
271 sai->is_slave_mode = false;
273 case SND_SOC_DAIFMT_CBM_CFM:
274 sai->is_slave_mode = true;
276 case SND_SOC_DAIFMT_CBS_CFM:
277 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
278 sai->is_slave_mode = false;
280 case SND_SOC_DAIFMT_CBM_CFS:
281 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
282 sai->is_slave_mode = true;
288 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
289 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
290 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
291 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
292 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
297 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
301 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
303 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
307 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
309 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
314 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
316 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
317 unsigned long clk_rate;
318 u32 savediv = 0, ratio, savesub = freq;
322 /* Don't apply to slave mode */
323 if (sai->is_slave_mode)
326 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
327 clk_rate = clk_get_rate(sai->mclk_clk[id]);
331 ratio = clk_rate / freq;
333 ret = clk_rate - ratio * freq;
336 * Drop the source that can not be
337 * divided into the required rate.
339 if (ret != 0 && clk_rate / ret < 1000)
343 "ratio %d for freq %dHz based on clock %ldHz\n",
344 ratio, freq, clk_rate);
346 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
353 sai->mclk_id[tx] = id;
362 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
363 tx ? 'T' : 'R', freq);
368 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
369 * set TCR2 register for playback.
370 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
372 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
374 * 4) For Tx and Rx are both Synchronous with another SAI, we just
377 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
378 (!tx && !sai->synchronous[RX])) {
379 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
380 FSL_SAI_CR2_MSEL_MASK,
381 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
382 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
383 FSL_SAI_CR2_DIV_MASK, savediv - 1);
384 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
385 (tx && !sai->synchronous[TX])) {
386 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
387 FSL_SAI_CR2_MSEL_MASK,
388 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
389 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
390 FSL_SAI_CR2_DIV_MASK, savediv - 1);
393 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
394 sai->mclk_id[tx], savediv, savesub);
399 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
400 struct snd_pcm_hw_params *params,
401 struct snd_soc_dai *cpu_dai)
403 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
404 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
405 unsigned int channels = params_channels(params);
406 u32 word_width = params_width(params);
407 u32 val_cr4 = 0, val_cr5 = 0;
408 u32 slots = (channels == 1) ? 2 : channels;
409 u32 slot_width = word_width;
416 slot_width = sai->slot_width;
418 if (!sai->is_slave_mode) {
419 ret = fsl_sai_set_bclk(cpu_dai, tx,
420 slots * slot_width * params_rate(params));
424 /* Do not enable the clock if it is already enabled */
425 if (!(sai->mclk_streams & BIT(substream->stream))) {
426 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
430 sai->mclk_streams |= BIT(substream->stream);
434 if (!sai->is_dsp_mode)
435 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
437 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
438 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
440 if (sai->is_lsb_first)
441 val_cr5 |= FSL_SAI_CR5_FBT(0);
443 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
445 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
448 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
449 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
450 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
454 if (!sai->is_slave_mode) {
455 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
456 regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
457 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
459 regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
460 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
461 FSL_SAI_CR5_FBT_MASK, val_cr5);
462 regmap_write(sai->regmap, FSL_SAI_TMR,
463 ~0UL - ((1 << channels) - 1));
464 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
465 regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
466 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
468 regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
469 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
470 FSL_SAI_CR5_FBT_MASK, val_cr5);
471 regmap_write(sai->regmap, FSL_SAI_RMR,
472 ~0UL - ((1 << channels) - 1));
476 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
477 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
479 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
480 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
481 FSL_SAI_CR5_FBT_MASK, val_cr5);
482 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
487 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
488 struct snd_soc_dai *cpu_dai)
490 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
491 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
493 if (!sai->is_slave_mode &&
494 sai->mclk_streams & BIT(substream->stream)) {
495 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
496 sai->mclk_streams &= ~BIT(substream->stream);
503 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
504 struct snd_soc_dai *cpu_dai)
506 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
507 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
508 u32 xcsr, count = 100;
511 * Asynchronous mode: Clear SYNC for both Tx and Rx.
512 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
513 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
515 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
516 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
517 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
518 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
521 * It is recommended that the transmitter is the last enabled
522 * and the first disabled.
525 case SNDRV_PCM_TRIGGER_START:
526 case SNDRV_PCM_TRIGGER_RESUME:
527 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
528 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
529 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
531 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
532 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
533 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
534 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
536 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
537 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
539 case SNDRV_PCM_TRIGGER_STOP:
540 case SNDRV_PCM_TRIGGER_SUSPEND:
541 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
542 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
543 FSL_SAI_CSR_FRDE, 0);
544 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
545 FSL_SAI_CSR_xIE_MASK, 0);
547 /* Check if the opposite FRDE is also disabled */
548 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
549 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
550 /* Disable both directions and reset their FIFOs */
551 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
552 FSL_SAI_CSR_TERE, 0);
553 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
554 FSL_SAI_CSR_TERE, 0);
556 /* TERE will remain set till the end of current frame */
559 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
560 } while (--count && xcsr & FSL_SAI_CSR_TERE);
562 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
563 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
564 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
565 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
568 * For sai master mode, after several open/close sai,
569 * there will be no frame clock, and can't recover
570 * anymore. Add software reset to fix this issue.
571 * This is a hardware bug, and will be fix in the
574 if (!sai->is_slave_mode) {
575 /* Software Reset for both Tx and Rx */
576 regmap_write(sai->regmap,
577 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
578 regmap_write(sai->regmap,
579 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
580 /* Clear SR bit to finish the reset */
581 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
582 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
593 static int fsl_sai_startup(struct snd_pcm_substream *substream,
594 struct snd_soc_dai *cpu_dai)
596 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
597 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
598 struct device *dev = &sai->pdev->dev;
601 ret = clk_prepare_enable(sai->bus_clk);
603 dev_err(dev, "failed to enable bus clock: %d\n", ret);
607 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
610 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
611 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
616 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
617 struct snd_soc_dai *cpu_dai)
619 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
620 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
622 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
624 clk_disable_unprepare(sai->bus_clk);
627 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
628 .set_sysclk = fsl_sai_set_dai_sysclk,
629 .set_fmt = fsl_sai_set_dai_fmt,
630 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
631 .hw_params = fsl_sai_hw_params,
632 .hw_free = fsl_sai_hw_free,
633 .trigger = fsl_sai_trigger,
634 .startup = fsl_sai_startup,
635 .shutdown = fsl_sai_shutdown,
638 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
640 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
642 /* Software Reset for both Tx and Rx */
643 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
644 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
645 /* Clear SR bit to finish the reset */
646 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
647 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
649 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
650 FSL_SAI_MAXBURST_TX * 2);
651 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
652 FSL_SAI_MAXBURST_RX - 1);
654 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
655 &sai->dma_params_rx);
657 snd_soc_dai_set_drvdata(cpu_dai, sai);
662 static struct snd_soc_dai_driver fsl_sai_dai = {
663 .probe = fsl_sai_dai_probe,
665 .stream_name = "CPU-Playback",
670 .rates = SNDRV_PCM_RATE_KNOT,
671 .formats = FSL_SAI_FORMATS,
674 .stream_name = "CPU-Capture",
679 .rates = SNDRV_PCM_RATE_KNOT,
680 .formats = FSL_SAI_FORMATS,
682 .ops = &fsl_sai_pcm_dai_ops,
685 static const struct snd_soc_component_driver fsl_component = {
689 static struct reg_default fsl_sai_reg_defaults[] = {
705 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
731 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
745 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
769 static const struct regmap_config fsl_sai_regmap_config = {
774 .max_register = FSL_SAI_RMR,
775 .reg_defaults = fsl_sai_reg_defaults,
776 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
777 .readable_reg = fsl_sai_readable_reg,
778 .volatile_reg = fsl_sai_volatile_reg,
779 .writeable_reg = fsl_sai_writeable_reg,
780 .cache_type = REGCACHE_FLAT,
783 static int fsl_sai_probe(struct platform_device *pdev)
785 struct device_node *np = pdev->dev.of_node;
788 struct resource *res;
794 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
800 if (of_device_is_compatible(np, "fsl,imx6sx-sai") ||
801 of_device_is_compatible(np, "fsl,imx6ul-sai"))
802 sai->sai_on_imx = true;
804 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
806 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
807 base = devm_ioremap_resource(&pdev->dev, res);
809 return PTR_ERR(base);
811 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
812 "bus", base, &fsl_sai_regmap_config);
814 /* Compatible with old DTB cases */
815 if (IS_ERR(sai->regmap))
816 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
817 "sai", base, &fsl_sai_regmap_config);
818 if (IS_ERR(sai->regmap)) {
819 dev_err(&pdev->dev, "regmap init failed\n");
820 return PTR_ERR(sai->regmap);
823 /* No error out for old DTB cases but only mark the clock NULL */
824 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
825 if (IS_ERR(sai->bus_clk)) {
826 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
827 PTR_ERR(sai->bus_clk));
831 sai->mclk_clk[0] = sai->bus_clk;
832 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
833 sprintf(tmp, "mclk%d", i);
834 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
835 if (IS_ERR(sai->mclk_clk[i])) {
836 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
837 i + 1, PTR_ERR(sai->mclk_clk[i]));
838 sai->mclk_clk[i] = NULL;
842 irq = platform_get_irq(pdev, 0);
844 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
848 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
850 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
854 /* Sync Tx with Rx as default by following old DT binding */
855 sai->synchronous[RX] = true;
856 sai->synchronous[TX] = false;
857 fsl_sai_dai.symmetric_rates = 1;
858 fsl_sai_dai.symmetric_channels = 1;
859 fsl_sai_dai.symmetric_samplebits = 1;
861 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
862 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
863 /* error out if both synchronous and asynchronous are present */
864 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
868 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
869 /* Sync Rx with Tx */
870 sai->synchronous[RX] = false;
871 sai->synchronous[TX] = true;
872 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
873 /* Discard all settings for asynchronous mode */
874 sai->synchronous[RX] = false;
875 sai->synchronous[TX] = false;
876 fsl_sai_dai.symmetric_rates = 0;
877 fsl_sai_dai.symmetric_channels = 0;
878 fsl_sai_dai.symmetric_samplebits = 0;
881 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
882 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
883 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
885 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
889 index = of_alias_get_id(np, "sai");
893 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
897 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
898 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
899 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
900 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
902 platform_set_drvdata(pdev, sai);
904 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
910 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
912 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
915 static const struct of_device_id fsl_sai_ids[] = {
916 { .compatible = "fsl,vf610-sai", },
917 { .compatible = "fsl,imx6sx-sai", },
918 { .compatible = "fsl,imx6ul-sai", },
921 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
923 #ifdef CONFIG_PM_SLEEP
924 static int fsl_sai_suspend(struct device *dev)
926 struct fsl_sai *sai = dev_get_drvdata(dev);
928 regcache_cache_only(sai->regmap, true);
929 regcache_mark_dirty(sai->regmap);
934 static int fsl_sai_resume(struct device *dev)
936 struct fsl_sai *sai = dev_get_drvdata(dev);
938 regcache_cache_only(sai->regmap, false);
939 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
940 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
941 usleep_range(1000, 2000);
942 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
943 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
944 return regcache_sync(sai->regmap);
946 #endif /* CONFIG_PM_SLEEP */
948 static const struct dev_pm_ops fsl_sai_pm_ops = {
949 SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
952 static struct platform_driver fsl_sai_driver = {
953 .probe = fsl_sai_probe,
956 .pm = &fsl_sai_pm_ops,
957 .of_match_table = fsl_sai_ids,
960 module_platform_driver(fsl_sai_driver);
962 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
963 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
964 MODULE_ALIAS("platform:fsl-sai");
965 MODULE_LICENSE("GPL");