1 // SPDX-License-Identifier: GPL-2.0
3 // ALSA SoC IMX MQS driver
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
17 #include <linux/slab.h>
18 #include <sound/soc.h>
19 #include <sound/pcm.h>
20 #include <sound/initval.h>
22 #define REG_MQS_CTRL 0x00
24 #define MQS_EN_MASK (0x1 << 28)
25 #define MQS_EN_SHIFT (28)
26 #define MQS_SW_RST_MASK (0x1 << 24)
27 #define MQS_SW_RST_SHIFT (24)
28 #define MQS_OVERSAMPLE_MASK (0x1 << 20)
29 #define MQS_OVERSAMPLE_SHIFT (20)
30 #define MQS_CLK_DIV_MASK (0xFF << 0)
31 #define MQS_CLK_DIV_SHIFT (0)
34 * struct fsl_mqs_soc_data - soc specific data
36 * @use_gpr: control register is in General Purpose Register group
37 * @ctrl_off: control register offset
38 * @en_mask: enable bit mask
39 * @en_shift: enable bit shift
40 * @rst_mask: reset bit mask
41 * @rst_shift: reset bit shift
42 * @osr_mask: oversample bit mask
43 * @osr_shift: oversample bit shift
44 * @div_mask: clock divider mask
45 * @div_shift: clock divider bit shift
47 struct fsl_mqs_soc_data {
60 /* codec private data */
62 struct regmap *regmap;
65 const struct fsl_mqs_soc_data *soc;
67 unsigned int reg_mqs_ctrl;
70 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
71 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
73 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
74 struct snd_pcm_hw_params *params,
75 struct snd_soc_dai *dai)
77 struct snd_soc_component *component = dai->component;
78 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
79 unsigned long mclk_rate;
83 mclk_rate = clk_get_rate(mqs_priv->mclk);
84 lrclk = params_rate(params);
87 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
88 * if repeat_rate is 8, mqs can achieve better quality.
89 * oversample rate is fix to 32 currently.
91 div = mclk_rate / (32 * lrclk * 2 * 8);
92 res = mclk_rate % (32 * lrclk * 2 * 8);
94 if (res == 0 && div > 0 && div <= 256) {
95 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
96 mqs_priv->soc->div_mask,
97 (div - 1) << mqs_priv->soc->div_shift);
98 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
99 mqs_priv->soc->osr_mask, 0);
101 dev_err(component->dev, "can't get proper divider\n");
107 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
109 /* Only LEFT_J & SLAVE mode is supported. */
110 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
111 case SND_SOC_DAIFMT_LEFT_J:
117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_NB_NF:
124 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
125 case SND_SOC_DAIFMT_CBC_CFC:
134 static int fsl_mqs_startup(struct snd_pcm_substream *substream,
135 struct snd_soc_dai *dai)
137 struct snd_soc_component *component = dai->component;
138 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
140 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
141 mqs_priv->soc->en_mask,
142 1 << mqs_priv->soc->en_shift);
146 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
147 struct snd_soc_dai *dai)
149 struct snd_soc_component *component = dai->component;
150 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
152 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
153 mqs_priv->soc->en_mask, 0);
156 static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
160 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
161 .startup = fsl_mqs_startup,
162 .shutdown = fsl_mqs_shutdown,
163 .hw_params = fsl_mqs_hw_params,
164 .set_fmt = fsl_mqs_set_dai_fmt,
167 static struct snd_soc_dai_driver fsl_mqs_dai = {
168 .name = "fsl-mqs-dai",
170 .stream_name = "Playback",
173 .rates = FSL_MQS_RATES,
174 .formats = FSL_MQS_FORMATS,
176 .ops = &fsl_mqs_dai_ops,
179 static const struct regmap_config fsl_mqs_regmap_config = {
183 .max_register = REG_MQS_CTRL,
184 .cache_type = REGCACHE_NONE,
187 static int fsl_mqs_probe(struct platform_device *pdev)
189 struct device_node *np = pdev->dev.of_node;
190 struct device_node *gpr_np = NULL;
191 struct fsl_mqs *mqs_priv;
195 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
199 /* On i.MX6sx the MQS control register is in GPR domain
200 * But in i.MX8QM/i.MX8QXP the control register is moved
203 mqs_priv->soc = of_device_get_match_data(&pdev->dev);
205 if (mqs_priv->soc->use_gpr) {
206 gpr_np = of_parse_phandle(np, "gpr", 0);
208 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
212 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
214 if (IS_ERR(mqs_priv->regmap)) {
215 dev_err(&pdev->dev, "failed to get gpr regmap\n");
216 return PTR_ERR(mqs_priv->regmap);
219 regs = devm_platform_ioremap_resource(pdev, 0);
221 return PTR_ERR(regs);
223 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
226 &fsl_mqs_regmap_config);
227 if (IS_ERR(mqs_priv->regmap)) {
228 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
229 PTR_ERR(mqs_priv->regmap));
230 return PTR_ERR(mqs_priv->regmap);
233 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
234 if (IS_ERR(mqs_priv->ipg)) {
235 dev_err(&pdev->dev, "failed to get the clock: %ld\n",
236 PTR_ERR(mqs_priv->ipg));
237 return PTR_ERR(mqs_priv->ipg);
241 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
242 if (IS_ERR(mqs_priv->mclk)) {
243 dev_err(&pdev->dev, "failed to get the clock: %ld\n",
244 PTR_ERR(mqs_priv->mclk));
245 return PTR_ERR(mqs_priv->mclk);
248 dev_set_drvdata(&pdev->dev, mqs_priv);
249 pm_runtime_enable(&pdev->dev);
251 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,
259 static int fsl_mqs_remove(struct platform_device *pdev)
261 pm_runtime_disable(&pdev->dev);
266 static int fsl_mqs_runtime_resume(struct device *dev)
268 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
271 ret = clk_prepare_enable(mqs_priv->ipg);
273 dev_err(dev, "failed to enable ipg clock\n");
277 ret = clk_prepare_enable(mqs_priv->mclk);
279 dev_err(dev, "failed to enable mclk clock\n");
280 clk_disable_unprepare(mqs_priv->ipg);
284 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl);
288 static int fsl_mqs_runtime_suspend(struct device *dev)
290 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
292 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl);
294 clk_disable_unprepare(mqs_priv->mclk);
295 clk_disable_unprepare(mqs_priv->ipg);
301 static const struct dev_pm_ops fsl_mqs_pm_ops = {
302 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
303 fsl_mqs_runtime_resume,
305 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
306 pm_runtime_force_resume)
309 static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
311 .ctrl_off = REG_MQS_CTRL,
312 .en_mask = MQS_EN_MASK,
313 .en_shift = MQS_EN_SHIFT,
314 .rst_mask = MQS_SW_RST_MASK,
315 .rst_shift = MQS_SW_RST_SHIFT,
316 .osr_mask = MQS_OVERSAMPLE_MASK,
317 .osr_shift = MQS_OVERSAMPLE_SHIFT,
318 .div_mask = MQS_CLK_DIV_MASK,
319 .div_shift = MQS_CLK_DIV_SHIFT,
322 static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
324 .ctrl_off = IOMUXC_GPR2,
325 .en_mask = IMX6SX_GPR2_MQS_EN_MASK,
326 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
327 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
328 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
329 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
330 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
331 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
332 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
335 static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
344 .div_mask = GENMASK(15, 8),
348 static const struct of_device_id fsl_mqs_dt_ids[] = {
349 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
350 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
351 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
354 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
356 static struct platform_driver fsl_mqs_driver = {
357 .probe = fsl_mqs_probe,
358 .remove = fsl_mqs_remove,
361 .of_match_table = fsl_mqs_dt_ids,
362 .pm = &fsl_mqs_pm_ops,
366 module_platform_driver(fsl_mqs_driver);
368 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>");
369 MODULE_DESCRIPTION("MQS codec driver");
370 MODULE_LICENSE("GPL v2");
371 MODULE_ALIAS("platform:fsl-mqs");