1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
7 // Author: Nicolin Chen <nicoleotsuka@gmail.com>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_data/dma-imx.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
21 #define IDEAL_RATIO_DECIMAL_DEPTH 26
23 #define pair_err(fmt, ...) \
24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
26 #define pair_dbg(fmt, ...) \
27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 /* Sample rates are aligned with that defined in pcm.h file */
30 static const u8 process_option[][12][2] = {
31 /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
32 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
33 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
34 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
35 {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
36 {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
37 {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
38 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
39 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
40 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
41 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
42 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
43 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
44 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
47 /* Corresponding to process_option */
48 static int supported_input_rate[] = {
49 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
50 96000, 176400, 192000,
53 static int supported_asrc_rate[] = {
54 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
58 * The following tables map the relationship between asrc_inclk/asrc_outclk in
59 * fsl_asrc.h and the registers of ASRCSR
61 static unsigned char input_clk_map_imx35[] = {
62 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
65 static unsigned char output_clk_map_imx35[] = {
66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
69 /* i.MX53 uses the same map for input and output */
70 static unsigned char input_clk_map_imx53[] = {
71 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
72 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
75 static unsigned char output_clk_map_imx53[] = {
76 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
77 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
80 static unsigned char *clk_map[2];
85 * It assigns pair by the order of A->C->B because allocation of pair B,
86 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
87 * while pair A and pair C are comparatively independent.
89 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
91 enum asrc_pair_index index = ASRC_INVALID_PAIR;
92 struct fsl_asrc *asrc_priv = pair->asrc_priv;
93 struct device *dev = &asrc_priv->pdev->dev;
94 unsigned long lock_flags;
97 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
99 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
100 if (asrc_priv->pair[i] != NULL)
105 if (i != ASRC_PAIR_B)
109 if (index == ASRC_INVALID_PAIR) {
110 dev_err(dev, "all pairs are busy now\n");
112 } else if (asrc_priv->channel_avail < channels) {
113 dev_err(dev, "can't afford required channels: %d\n", channels);
116 asrc_priv->channel_avail -= channels;
117 asrc_priv->pair[index] = pair;
118 pair->channels = channels;
122 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
130 * It clears the resource from asrc_priv and releases the occupied channels.
132 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
134 struct fsl_asrc *asrc_priv = pair->asrc_priv;
135 enum asrc_pair_index index = pair->index;
136 unsigned long lock_flags;
138 /* Make sure the pair is disabled */
139 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
140 ASRCTR_ASRCEi_MASK(index), 0);
142 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
144 asrc_priv->channel_avail += pair->channels;
145 asrc_priv->pair[index] = NULL;
148 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
152 * Configure input and output thresholds
154 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
156 struct fsl_asrc *asrc_priv = pair->asrc_priv;
157 enum asrc_pair_index index = pair->index;
159 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
160 ASRMCRi_EXTTHRSHi_MASK |
161 ASRMCRi_INFIFO_THRESHOLD_MASK |
162 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
164 ASRMCRi_INFIFO_THRESHOLD(in) |
165 ASRMCRi_OUTFIFO_THRESHOLD(out));
169 * Calculate the total divisor between asrck clock rate and sample rate
171 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
173 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
177 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
178 for (ps = 0; div > 8; ps++)
181 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
185 * Calculate and set the ratio for Ideal Ratio mode only
187 * The ratio is a 32-bit fixed point value with 26 fractional bits.
189 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
190 int inrate, int outrate)
192 struct fsl_asrc *asrc_priv = pair->asrc_priv;
193 enum asrc_pair_index index = pair->index;
198 pair_err("output rate should not be zero\n");
202 /* Calculate the intergal part of the ratio */
203 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
205 /* ... and then the 26 depth decimal part */
208 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
211 if (inrate < outrate)
214 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
221 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
222 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
228 * Configure the assigned ASRC pair
230 * It configures those ASRC registers according to a configuration instance
231 * of struct asrc_config which includes in/output sample rate, width, channel
232 * and clock settings.
234 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
236 struct asrc_config *config = pair->config;
237 struct fsl_asrc *asrc_priv = pair->asrc_priv;
238 enum asrc_pair_index index = pair->index;
239 u32 inrate, outrate, indiv, outdiv;
240 u32 clk_index[2], div[2];
241 int in, out, channels;
246 pair_err("invalid pair config\n");
250 /* Validate channels */
251 if (config->channel_num < 1 || config->channel_num > 10) {
252 pair_err("does not support %d channels\n", config->channel_num);
256 /* Validate output width */
257 if (config->output_word_width == ASRC_WIDTH_8_BIT) {
258 pair_err("does not support 8bit width output\n");
262 inrate = config->input_sample_rate;
263 outrate = config->output_sample_rate;
264 ideal = config->inclk == INCLK_NONE;
266 /* Validate input and output sample rates */
267 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
268 if (inrate == supported_input_rate[in])
271 if (in == ARRAY_SIZE(supported_input_rate)) {
272 pair_err("unsupported input sample rate: %dHz\n", inrate);
276 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
277 if (outrate == supported_asrc_rate[out])
280 if (out == ARRAY_SIZE(supported_asrc_rate)) {
281 pair_err("unsupported output sample rate: %dHz\n", outrate);
285 if ((outrate >= 8000 && outrate <= 30000) &&
286 (outrate > 24 * inrate || inrate > 8 * outrate)) {
287 pair_err("exceed supported ratio range [1/24, 8] for \
288 inrate/outrate: %d/%d\n", inrate, outrate);
292 /* Validate input and output clock sources */
293 clk_index[IN] = clk_map[IN][config->inclk];
294 clk_index[OUT] = clk_map[OUT][config->outclk];
296 /* We only have output clock for ideal ratio mode */
297 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
299 div[IN] = clk_get_rate(clk) / inrate;
301 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
302 inrate, clk_index[ideal ? OUT : IN]);
306 clk = asrc_priv->asrck_clk[clk_index[OUT]];
308 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
310 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
312 div[OUT] = clk_get_rate(clk) / outrate;
315 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
316 outrate, clk_index[OUT]);
320 /* Set the channel number */
321 channels = config->channel_num;
323 if (asrc_priv->channel_bits < 4)
326 /* Update channels for current pair */
327 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
328 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
329 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
331 /* Default setting: Automatic selection for processing mode */
332 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
333 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
334 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
335 ASRCTR_USRi_MASK(index), 0);
337 /* Set the input and output clock sources */
338 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
339 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
340 ASRCSR_AICS(index, clk_index[IN]) |
341 ASRCSR_AOCS(index, clk_index[OUT]));
343 /* Calculate the input clock divisors */
344 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
345 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
347 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
348 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
349 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
350 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
351 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
353 /* Implement word_width configurations */
354 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
355 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
356 ASRMCR1i_OW16(config->output_word_width) |
357 ASRMCR1i_IWD(config->input_word_width));
359 /* Enable BUFFER STALL */
360 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
361 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
363 /* Set default thresholds for input and output FIFO */
364 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
365 ASRC_INPUTFIFO_THRESHOLD);
367 /* Configure the following only for Ideal Ratio mode */
371 /* Clear ASTSx bit to use Ideal Ratio mode */
372 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
373 ASRCTR_ATSi_MASK(index), 0);
375 /* Enable Ideal Ratio mode */
376 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
377 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
378 ASRCTR_IDR(index) | ASRCTR_USR(index));
380 /* Apply configurations for pre- and post-processing */
381 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
382 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
383 ASRCFG_PREMOD(index, process_option[in][out][0]) |
384 ASRCFG_POSTMOD(index, process_option[in][out][1]));
386 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
390 * Start the assigned ASRC pair
392 * It enables the assigned pair and makes it stopped at the stall level.
394 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
396 struct fsl_asrc *asrc_priv = pair->asrc_priv;
397 enum asrc_pair_index index = pair->index;
398 int reg, retry = 10, i;
400 /* Enable the current pair */
401 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
402 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
404 /* Wait for status of initialization */
407 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
408 reg &= ASRCFG_INIRQi_MASK(index);
409 } while (!reg && --retry);
411 /* Make the input fifo to ASRC STALL level */
412 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
413 for (i = 0; i < pair->channels * 4; i++)
414 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
416 /* Enable overload interrupt */
417 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
421 * Stop the assigned ASRC pair
423 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
425 struct fsl_asrc *asrc_priv = pair->asrc_priv;
426 enum asrc_pair_index index = pair->index;
428 /* Stop the current pair */
429 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
430 ASRCTR_ASRCEi_MASK(index), 0);
434 * Get DMA channel according to the pair and direction.
436 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
438 struct fsl_asrc *asrc_priv = pair->asrc_priv;
439 enum asrc_pair_index index = pair->index;
442 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
444 return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
446 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
448 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
449 struct snd_pcm_hw_params *params,
450 struct snd_soc_dai *dai)
452 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
453 int width = params_width(params);
454 struct snd_pcm_runtime *runtime = substream->runtime;
455 struct fsl_asrc_pair *pair = runtime->private_data;
456 unsigned int channels = params_channels(params);
457 unsigned int rate = params_rate(params);
458 struct asrc_config config;
461 ret = fsl_asrc_request_pair(channels, pair);
463 dev_err(dai->dev, "fail to request asrc pair\n");
467 pair->config = &config;
470 width = ASRC_WIDTH_16_BIT;
472 width = ASRC_WIDTH_24_BIT;
474 if (asrc_priv->asrc_width == 16)
475 word_width = ASRC_WIDTH_16_BIT;
477 word_width = ASRC_WIDTH_24_BIT;
479 config.pair = pair->index;
480 config.channel_num = channels;
481 config.inclk = INCLK_NONE;
482 config.outclk = OUTCLK_ASRCK1_CLK;
484 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
485 config.input_word_width = width;
486 config.output_word_width = word_width;
487 config.input_sample_rate = rate;
488 config.output_sample_rate = asrc_priv->asrc_rate;
490 config.input_word_width = word_width;
491 config.output_word_width = width;
492 config.input_sample_rate = asrc_priv->asrc_rate;
493 config.output_sample_rate = rate;
496 ret = fsl_asrc_config_pair(pair);
498 dev_err(dai->dev, "fail to config asrc pair\n");
505 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
506 struct snd_soc_dai *dai)
508 struct snd_pcm_runtime *runtime = substream->runtime;
509 struct fsl_asrc_pair *pair = runtime->private_data;
512 fsl_asrc_release_pair(pair);
517 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
518 struct snd_soc_dai *dai)
520 struct snd_pcm_runtime *runtime = substream->runtime;
521 struct fsl_asrc_pair *pair = runtime->private_data;
524 case SNDRV_PCM_TRIGGER_START:
525 case SNDRV_PCM_TRIGGER_RESUME:
526 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
527 fsl_asrc_start_pair(pair);
529 case SNDRV_PCM_TRIGGER_STOP:
530 case SNDRV_PCM_TRIGGER_SUSPEND:
531 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
532 fsl_asrc_stop_pair(pair);
541 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
542 .hw_params = fsl_asrc_dai_hw_params,
543 .hw_free = fsl_asrc_dai_hw_free,
544 .trigger = fsl_asrc_dai_trigger,
547 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
549 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
551 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
552 &asrc_priv->dma_params_rx);
557 #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
558 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
559 SNDRV_PCM_FMTBIT_S16_LE | \
560 SNDRV_PCM_FMTBIT_S20_3LE)
562 static struct snd_soc_dai_driver fsl_asrc_dai = {
563 .probe = fsl_asrc_dai_probe,
565 .stream_name = "ASRC-Playback",
568 .rates = FSL_ASRC_RATES,
569 .formats = FSL_ASRC_FORMATS,
572 .stream_name = "ASRC-Capture",
575 .rates = FSL_ASRC_RATES,
576 .formats = FSL_ASRC_FORMATS,
578 .ops = &fsl_asrc_dai_ops,
581 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
625 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
645 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
686 static struct reg_default fsl_asrc_reg[] = {
687 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
688 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
689 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
690 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
691 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
692 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
693 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
694 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
695 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
696 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
697 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
698 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
699 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
700 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
701 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
702 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
703 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
704 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
705 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
706 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
707 { REG_ASRMCR1C, 0x0000 },
710 static const struct regmap_config fsl_asrc_regmap_config = {
715 .max_register = REG_ASRMCR1C,
716 .reg_defaults = fsl_asrc_reg,
717 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
718 .readable_reg = fsl_asrc_readable_reg,
719 .volatile_reg = fsl_asrc_volatile_reg,
720 .writeable_reg = fsl_asrc_writeable_reg,
721 .cache_type = REGCACHE_FLAT,
725 * Initialize ASRC registers with a default configurations
727 static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
729 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
730 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
732 /* Disable interrupt by default */
733 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
735 /* Apply recommended settings for parameters from Reference Manual */
736 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
737 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
738 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
739 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
740 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
742 /* Base address for task queue FIFO. Set to 0x7C */
743 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
744 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
746 /* Set the processing clock for 76KHz to 133M */
747 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
749 /* Set the processing clock for 56KHz to 133M */
750 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
754 * Interrupt handler for ASRC
756 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
758 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
759 struct device *dev = &asrc_priv->pdev->dev;
760 enum asrc_pair_index index;
763 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
765 /* Clean overload error */
766 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
769 * We here use dev_dbg() for all exceptions because ASRC itself does
770 * not care if FIFO overflowed or underrun while a warning in the
771 * interrupt would result a ridged conversion.
773 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
774 if (!asrc_priv->pair[index])
777 if (status & ASRSTR_ATQOL) {
778 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
779 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
782 if (status & ASRSTR_AOOL(index)) {
783 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
784 pair_dbg("Output Task Overload\n");
787 if (status & ASRSTR_AIOL(index)) {
788 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
789 pair_dbg("Input Task Overload\n");
792 if (status & ASRSTR_AODO(index)) {
793 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
794 pair_dbg("Output Data Buffer has overflowed\n");
797 if (status & ASRSTR_AIDU(index)) {
798 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
799 pair_dbg("Input Data Buffer has underflowed\n");
806 static int fsl_asrc_probe(struct platform_device *pdev)
808 struct device_node *np = pdev->dev.of_node;
809 struct fsl_asrc *asrc_priv;
810 struct resource *res;
815 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
819 asrc_priv->pdev = pdev;
821 /* Get the addresses and IRQ */
822 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
823 regs = devm_ioremap_resource(&pdev->dev, res);
825 return PTR_ERR(regs);
827 asrc_priv->paddr = res->start;
829 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
830 &fsl_asrc_regmap_config);
831 if (IS_ERR(asrc_priv->regmap)) {
832 dev_err(&pdev->dev, "failed to init regmap\n");
833 return PTR_ERR(asrc_priv->regmap);
836 irq = platform_get_irq(pdev, 0);
838 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
842 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
843 dev_name(&pdev->dev), asrc_priv);
845 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
849 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
850 if (IS_ERR(asrc_priv->mem_clk)) {
851 dev_err(&pdev->dev, "failed to get mem clock\n");
852 return PTR_ERR(asrc_priv->mem_clk);
855 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
856 if (IS_ERR(asrc_priv->ipg_clk)) {
857 dev_err(&pdev->dev, "failed to get ipg clock\n");
858 return PTR_ERR(asrc_priv->ipg_clk);
861 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
862 if (IS_ERR(asrc_priv->spba_clk))
863 dev_warn(&pdev->dev, "failed to get spba clock\n");
865 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
866 sprintf(tmp, "asrck_%x", i);
867 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
868 if (IS_ERR(asrc_priv->asrck_clk[i])) {
869 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
870 return PTR_ERR(asrc_priv->asrck_clk[i]);
874 if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
875 asrc_priv->channel_bits = 3;
876 clk_map[IN] = input_clk_map_imx35;
877 clk_map[OUT] = output_clk_map_imx35;
879 asrc_priv->channel_bits = 4;
880 clk_map[IN] = input_clk_map_imx53;
881 clk_map[OUT] = output_clk_map_imx53;
884 ret = fsl_asrc_init(asrc_priv);
886 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
890 asrc_priv->channel_avail = 10;
892 ret = of_property_read_u32(np, "fsl,asrc-rate",
893 &asrc_priv->asrc_rate);
895 dev_err(&pdev->dev, "failed to get output rate\n");
899 ret = of_property_read_u32(np, "fsl,asrc-width",
900 &asrc_priv->asrc_width);
902 dev_err(&pdev->dev, "failed to get output width\n");
906 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
907 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
908 asrc_priv->asrc_width = 24;
911 platform_set_drvdata(pdev, asrc_priv);
912 pm_runtime_enable(&pdev->dev);
913 spin_lock_init(&asrc_priv->lock);
915 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
918 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
926 static int fsl_asrc_runtime_resume(struct device *dev)
928 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
931 ret = clk_prepare_enable(asrc_priv->mem_clk);
934 ret = clk_prepare_enable(asrc_priv->ipg_clk);
936 goto disable_mem_clk;
937 if (!IS_ERR(asrc_priv->spba_clk)) {
938 ret = clk_prepare_enable(asrc_priv->spba_clk);
940 goto disable_ipg_clk;
942 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
943 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
945 goto disable_asrck_clk;
951 for (i--; i >= 0; i--)
952 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
953 if (!IS_ERR(asrc_priv->spba_clk))
954 clk_disable_unprepare(asrc_priv->spba_clk);
956 clk_disable_unprepare(asrc_priv->ipg_clk);
958 clk_disable_unprepare(asrc_priv->mem_clk);
962 static int fsl_asrc_runtime_suspend(struct device *dev)
964 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
967 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
968 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
969 if (!IS_ERR(asrc_priv->spba_clk))
970 clk_disable_unprepare(asrc_priv->spba_clk);
971 clk_disable_unprepare(asrc_priv->ipg_clk);
972 clk_disable_unprepare(asrc_priv->mem_clk);
976 #endif /* CONFIG_PM */
978 #ifdef CONFIG_PM_SLEEP
979 static int fsl_asrc_suspend(struct device *dev)
981 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
983 regmap_read(asrc_priv->regmap, REG_ASRCFG,
984 &asrc_priv->regcache_cfg);
986 regcache_cache_only(asrc_priv->regmap, true);
987 regcache_mark_dirty(asrc_priv->regmap);
992 static int fsl_asrc_resume(struct device *dev)
994 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
997 /* Stop all pairs provisionally */
998 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
999 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1000 ASRCTR_ASRCEi_ALL_MASK, 0);
1002 /* Restore all registers */
1003 regcache_cache_only(asrc_priv->regmap, false);
1004 regcache_sync(asrc_priv->regmap);
1006 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1007 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1008 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1010 /* Restart enabled pairs */
1011 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1012 ASRCTR_ASRCEi_ALL_MASK, asrctr);
1016 #endif /* CONFIG_PM_SLEEP */
1018 static const struct dev_pm_ops fsl_asrc_pm = {
1019 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1020 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1023 static const struct of_device_id fsl_asrc_ids[] = {
1024 { .compatible = "fsl,imx35-asrc", },
1025 { .compatible = "fsl,imx53-asrc", },
1028 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1030 static struct platform_driver fsl_asrc_driver = {
1031 .probe = fsl_asrc_probe,
1034 .of_match_table = fsl_asrc_ids,
1038 module_platform_driver(fsl_asrc_driver);
1040 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1041 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1042 MODULE_ALIAS("platform:fsl-asrc");
1043 MODULE_LICENSE("GPL v2");