2 * FBTFT driver for the RA8875 LCD Controller
3 * Copyright by Pf@nne & NOTRO
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
21 #include <linux/gpio.h>
24 #define DRVNAME "fb_ra8875"
26 static int write_spi(struct fbtft_par *par, void *buf, size_t len)
28 struct spi_transfer t = {
35 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
36 "%s(len=%d): ", __func__, len);
39 dev_err(par->info->device,
40 "%s: par->spi is unexpectedly NULL\n", __func__);
45 spi_message_add_tail(&t, &m);
46 return spi_sync(par->spi, &m);
49 static int init_display(struct fbtft_par *par)
51 gpio_set_value(par->gpio.dc, 1);
53 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
55 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
56 "display size %dx%d\n",
60 par->fbtftops.reset(par);
62 if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
63 /* PLL clock frequency */
64 write_reg(par, 0x88, 0x0A);
65 write_reg(par, 0x89, 0x02);
67 /* color deep / MCU Interface */
68 write_reg(par, 0x10, 0x0C);
69 /* pixel clock period */
70 write_reg(par, 0x04, 0x03);
72 /* horizontal settings */
73 write_reg(par, 0x14, 0x27);
74 write_reg(par, 0x15, 0x00);
75 write_reg(par, 0x16, 0x05);
76 write_reg(par, 0x17, 0x04);
77 write_reg(par, 0x18, 0x03);
78 /* vertical settings */
79 write_reg(par, 0x19, 0xEF);
80 write_reg(par, 0x1A, 0x00);
81 write_reg(par, 0x1B, 0x05);
82 write_reg(par, 0x1C, 0x00);
83 write_reg(par, 0x1D, 0x0E);
84 write_reg(par, 0x1E, 0x00);
85 write_reg(par, 0x1F, 0x02);
86 } else if ((par->info->var.xres == 480) &&
87 (par->info->var.yres == 272)) {
88 /* PLL clock frequency */
89 write_reg(par, 0x88, 0x0A);
90 write_reg(par, 0x89, 0x02);
92 /* color deep / MCU Interface */
93 write_reg(par, 0x10, 0x0C);
94 /* pixel clock period */
95 write_reg(par, 0x04, 0x82);
97 /* horizontal settings */
98 write_reg(par, 0x14, 0x3B);
99 write_reg(par, 0x15, 0x00);
100 write_reg(par, 0x16, 0x01);
101 write_reg(par, 0x17, 0x00);
102 write_reg(par, 0x18, 0x05);
103 /* vertical settings */
104 write_reg(par, 0x19, 0x0F);
105 write_reg(par, 0x1A, 0x01);
106 write_reg(par, 0x1B, 0x02);
107 write_reg(par, 0x1C, 0x00);
108 write_reg(par, 0x1D, 0x07);
109 write_reg(par, 0x1E, 0x00);
110 write_reg(par, 0x1F, 0x09);
111 } else if ((par->info->var.xres == 640) &&
112 (par->info->var.yres == 480)) {
113 /* PLL clock frequency */
114 write_reg(par, 0x88, 0x0B);
115 write_reg(par, 0x89, 0x02);
117 /* color deep / MCU Interface */
118 write_reg(par, 0x10, 0x0C);
119 /* pixel clock period */
120 write_reg(par, 0x04, 0x01);
122 /* horizontal settings */
123 write_reg(par, 0x14, 0x4F);
124 write_reg(par, 0x15, 0x05);
125 write_reg(par, 0x16, 0x0F);
126 write_reg(par, 0x17, 0x01);
127 write_reg(par, 0x18, 0x00);
128 /* vertical settings */
129 write_reg(par, 0x19, 0xDF);
130 write_reg(par, 0x1A, 0x01);
131 write_reg(par, 0x1B, 0x0A);
132 write_reg(par, 0x1C, 0x00);
133 write_reg(par, 0x1D, 0x0E);
134 write_reg(par, 0x1E, 0x00);
135 write_reg(par, 0x1F, 0x01);
136 } else if ((par->info->var.xres == 800) &&
137 (par->info->var.yres == 480)) {
138 /* PLL clock frequency */
139 write_reg(par, 0x88, 0x0B);
140 write_reg(par, 0x89, 0x02);
142 /* color deep / MCU Interface */
143 write_reg(par, 0x10, 0x0C);
144 /* pixel clock period */
145 write_reg(par, 0x04, 0x81);
147 /* horizontal settings */
148 write_reg(par, 0x14, 0x63);
149 write_reg(par, 0x15, 0x03);
150 write_reg(par, 0x16, 0x03);
151 write_reg(par, 0x17, 0x02);
152 write_reg(par, 0x18, 0x00);
153 /* vertical settings */
154 write_reg(par, 0x19, 0xDF);
155 write_reg(par, 0x1A, 0x01);
156 write_reg(par, 0x1B, 0x14);
157 write_reg(par, 0x1C, 0x00);
158 write_reg(par, 0x1D, 0x06);
159 write_reg(par, 0x1E, 0x00);
160 write_reg(par, 0x1F, 0x01);
162 dev_err(par->info->device, "display size is not supported!!");
167 write_reg(par, 0x8a, 0x81);
168 write_reg(par, 0x8b, 0xFF);
172 write_reg(par, 0x01, 0x80);
178 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
180 /* Set_Active_Window */
181 write_reg(par, 0x30, xs & 0x00FF);
182 write_reg(par, 0x31, (xs & 0xFF00) >> 8);
183 write_reg(par, 0x32, ys & 0x00FF);
184 write_reg(par, 0x33, (ys & 0xFF00) >> 8);
185 write_reg(par, 0x34, (xs + xe) & 0x00FF);
186 write_reg(par, 0x35, ((xs + xe) & 0xFF00) >> 8);
187 write_reg(par, 0x36, (ys + ye) & 0x00FF);
188 write_reg(par, 0x37, ((ys + ye) & 0xFF00) >> 8);
190 /* Set_Memory_Write_Cursor */
191 write_reg(par, 0x46, xs & 0xff);
192 write_reg(par, 0x47, (xs >> 8) & 0x03);
193 write_reg(par, 0x48, ys & 0xff);
194 write_reg(par, 0x49, (ys >> 8) & 0x01);
196 write_reg(par, 0x02);
199 static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
205 /* slow down spi-speed for writing registers */
206 par->fbtftops.write = write_spi;
208 if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
210 for (i = 0; i < len; i++)
211 buf[i] = (u8)va_arg(args, unsigned int);
213 fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device,
214 u8, buf, len, "%s: ", __func__);
219 *buf = (u8)va_arg(args, unsigned int);
220 ret = par->fbtftops.write(par, par->buf, 2);
223 dev_err(par->info->device, "write() failed and returned %dn",
232 buf = (u8 *)par->buf;
236 *buf++ = (u8)va_arg(args, unsigned int);
238 ret = par->fbtftops.write(par, par->buf, len + 1);
241 dev_err(par->info->device,
242 "write() failed and returned %dn", ret);
248 /* restore user spi-speed */
249 par->fbtftops.write = fbtft_write_spi;
253 static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
256 __be16 *txbuf16 = par->txbuf.buf;
259 size_t tx_array_size;
262 size_t startbyte_size = 0;
264 fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
265 __func__, offset, len);
268 vmem16 = (u16 *)(par->info->screen_buffer + offset);
269 tx_array_size = par->txbuf.len / 2;
270 txbuf16 = par->txbuf.buf + 1;
272 *(u8 *)(par->txbuf.buf) = 0x00;
276 to_copy = min(tx_array_size, remain);
277 dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n",
278 to_copy, remain - to_copy);
280 for (i = 0; i < to_copy; i++)
281 txbuf16[i] = cpu_to_be16(vmem16[i]);
283 vmem16 = vmem16 + to_copy;
284 ret = par->fbtftops.write(par, par->txbuf.buf,
285 startbyte_size + to_copy * 2);
294 static struct fbtft_display display = {
297 .init_display = init_display,
298 .set_addr_win = set_addr_win,
299 .write_register = write_reg8_bus8,
300 .write_vmem = write_vmem16_bus8,
305 FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
307 MODULE_ALIAS("spi:" DRVNAME);
308 MODULE_ALIAS("platform:" DRVNAME);
309 MODULE_ALIAS("spi:ra8875");
310 MODULE_ALIAS("platform:ra8875");
312 MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
313 MODULE_AUTHOR("Pf@nne");
314 MODULE_LICENSE("GPL");