2 * Boot code and exception vectors for Book3E processors
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
27 #include <asm/hw_irq.h>
28 #include <asm/kvm_asm.h>
29 #include <asm/kvm_booke_hv_asm.h>
30 #include <asm/feature-fixups.h>
32 /* XXX This will ultimately add space for a special exception save
33 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
34 * when taking special interrupts. For now we don't support that,
35 * special interrupts from within a non-standard level will probably
38 #define SPECIAL_EXC_SRR0 0
39 #define SPECIAL_EXC_SRR1 1
40 #define SPECIAL_EXC_SPRG_GEN 2
41 #define SPECIAL_EXC_SPRG_TLB 3
42 #define SPECIAL_EXC_MAS0 4
43 #define SPECIAL_EXC_MAS1 5
44 #define SPECIAL_EXC_MAS2 6
45 #define SPECIAL_EXC_MAS3 7
46 #define SPECIAL_EXC_MAS6 8
47 #define SPECIAL_EXC_MAS7 9
48 #define SPECIAL_EXC_MAS5 10 /* E.HV only */
49 #define SPECIAL_EXC_MAS8 11 /* E.HV only */
50 #define SPECIAL_EXC_IRQHAPPENED 12
51 #define SPECIAL_EXC_DEAR 13
52 #define SPECIAL_EXC_ESR 14
53 #define SPECIAL_EXC_SOFTE 15
54 #define SPECIAL_EXC_CSRR0 16
55 #define SPECIAL_EXC_CSRR1 17
56 /* must be even to keep 16-byte stack alignment */
57 #define SPECIAL_EXC_END 18
59 #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
60 #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288)
62 #define SPECIAL_EXC_STORE(reg, name) \
63 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
65 #define SPECIAL_EXC_LOAD(reg, name) \
66 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
69 lbz r9,PACAIRQHAPPENED(r13)
70 RECONCILE_IRQ_STATE(r3,r4)
73 * We only need (or have stack space) to save this stuff if
74 * we interrupted the kernel.
80 /* Copy info into temporary exception thread info */
82 CURRENT_THREAD_INFO(r11, r11)
83 CURRENT_THREAD_INFO(r12, r1)
86 ld r10,TI_PREEMPT(r11)
87 std r10,TI_PREEMPT(r12)
92 * Advance to the next TLB exception frame for handler
93 * types that don't do it automatically.
95 LOAD_REG_ADDR(r11,extlb_level_exc)
97 mfspr r10,SPRN_SPRG_TLB_EXFRAME
99 mtspr SPRN_SPRG_TLB_EXFRAME,r10
102 * Save registers needed to allow nesting of certain exceptions
103 * (such as TLB misses) inside special exception levels
106 SPECIAL_EXC_STORE(r10,SRR0)
108 SPECIAL_EXC_STORE(r10,SRR1)
109 mfspr r10,SPRN_SPRG_GEN_SCRATCH
110 SPECIAL_EXC_STORE(r10,SPRG_GEN)
111 mfspr r10,SPRN_SPRG_TLB_SCRATCH
112 SPECIAL_EXC_STORE(r10,SPRG_TLB)
114 SPECIAL_EXC_STORE(r10,MAS0)
116 SPECIAL_EXC_STORE(r10,MAS1)
118 SPECIAL_EXC_STORE(r10,MAS2)
120 SPECIAL_EXC_STORE(r10,MAS3)
122 SPECIAL_EXC_STORE(r10,MAS6)
124 SPECIAL_EXC_STORE(r10,MAS7)
127 SPECIAL_EXC_STORE(r10,MAS5)
129 SPECIAL_EXC_STORE(r10,MAS8)
131 /* MAS5/8 could have inappropriate values if we interrupted KVM code */
135 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
136 SPECIAL_EXC_STORE(r9,IRQHAPPENED)
139 SPECIAL_EXC_STORE(r10,DEAR)
141 SPECIAL_EXC_STORE(r10,ESR)
143 lbz r10,PACAIRQSOFTMASK(r13)
144 SPECIAL_EXC_STORE(r10,SOFTE)
146 SPECIAL_EXC_STORE(r10,CSRR0)
148 SPECIAL_EXC_STORE(r10,CSRR1)
152 ret_from_level_except:
159 LOAD_REG_ADDR(r11,extlb_level_exc)
161 mfspr r10,SPRN_SPRG_TLB_EXFRAME
163 mtspr SPRN_SPRG_TLB_EXFRAME,r10
166 * It's possible that the special level exception interrupted a
167 * TLB miss handler, and inserted the same entry that the
168 * interrupted handler was about to insert. On CPUs without TLB
169 * write conditional, this can result in a duplicate TLB entry.
170 * Wipe all non-bolted entries to be safe.
172 * Note that this doesn't protect against any TLB misses
173 * we may take accessing the stack from here to the end of
174 * the special level exception. It's not clear how we can
175 * reasonably protect against that, but only CPUs with
176 * neither TLB write conditional nor bolted kernel memory
177 * are affected. Do any such CPUs even exist?
183 SPECIAL_EXC_LOAD(r10,SRR0)
185 SPECIAL_EXC_LOAD(r10,SRR1)
187 SPECIAL_EXC_LOAD(r10,SPRG_GEN)
188 mtspr SPRN_SPRG_GEN_SCRATCH,r10
189 SPECIAL_EXC_LOAD(r10,SPRG_TLB)
190 mtspr SPRN_SPRG_TLB_SCRATCH,r10
191 SPECIAL_EXC_LOAD(r10,MAS0)
193 SPECIAL_EXC_LOAD(r10,MAS1)
195 SPECIAL_EXC_LOAD(r10,MAS2)
197 SPECIAL_EXC_LOAD(r10,MAS3)
199 SPECIAL_EXC_LOAD(r10,MAS6)
201 SPECIAL_EXC_LOAD(r10,MAS7)
204 SPECIAL_EXC_LOAD(r10,MAS5)
206 SPECIAL_EXC_LOAD(r10,MAS8)
208 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
210 lbz r6,PACAIRQSOFTMASK(r13)
213 /* Interrupts had better not already be enabled... */
214 tweqi r6,IRQS_ENABLED
216 andi. r6,r5,IRQS_DISABLED
220 stb r5,PACAIRQSOFTMASK(r13)
223 * Restore PACAIRQHAPPENED rather than setting it based on
224 * the return MSR[EE], since we could have interrupted
225 * __check_irq_replay() or other inconsistent transitory
226 * states that must remain that way.
228 SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
229 stb r10,PACAIRQHAPPENED(r13)
231 SPECIAL_EXC_LOAD(r10,DEAR)
233 SPECIAL_EXC_LOAD(r10,ESR)
236 stdcx. r0,0,r1 /* to clear the reservation */
248 .macro ret_from_level srr0 srr1 paca_ex scratch
249 bl ret_from_level_except
262 std r10,\paca_ex+EX_R10(r13);
263 std r11,\paca_ex+EX_R11(r13);
270 ld r10,\paca_ex+EX_R10(r13)
271 ld r11,\paca_ex+EX_R11(r13)
275 ret_from_crit_except:
276 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
280 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
283 /* Exception prolog code for all exceptions */
284 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
285 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
286 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
287 std r10,PACA_EX##type+EX_R10(r13); \
288 std r11,PACA_EX##type+EX_R11(r13); \
289 mfcr r10; /* save CR */ \
290 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
291 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
292 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
293 addition; /* additional code for that exc. */ \
294 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
295 type##_SET_KSTACK; /* get special stack if necessary */\
296 andi. r10,r11,MSR_PR; /* save stack pointer */ \
297 beq 1f; /* branch around if supervisor */ \
298 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
299 1: type##_BTB_FLUSH \
300 cmpdi cr1,r1,0; /* check if SP makes sense */ \
301 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
302 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
304 /* Exception type-specific macros */
305 #define GEN_SET_KSTACK \
306 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
307 #define SPRN_GEN_SRR0 SPRN_SRR0
308 #define SPRN_GEN_SRR1 SPRN_SRR1
310 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
311 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
312 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
314 #define CRIT_SET_KSTACK \
315 ld r1,PACA_CRIT_STACK(r13); \
316 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
317 #define SPRN_CRIT_SRR0 SPRN_CSRR0
318 #define SPRN_CRIT_SRR1 SPRN_CSRR1
320 #define DBG_SET_KSTACK \
321 ld r1,PACA_DBG_STACK(r13); \
322 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
323 #define SPRN_DBG_SRR0 SPRN_DSRR0
324 #define SPRN_DBG_SRR1 SPRN_DSRR1
326 #define MC_SET_KSTACK \
327 ld r1,PACA_MC_STACK(r13); \
328 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
329 #define SPRN_MC_SRR0 SPRN_MCSRR0
330 #define SPRN_MC_SRR1 SPRN_MCSRR1
332 #ifdef CONFIG_PPC_FSL_BOOK3E
333 #define GEN_BTB_FLUSH \
334 START_BTB_FLUSH_SECTION \
338 END_BTB_FLUSH_SECTION
340 #define CRIT_BTB_FLUSH \
341 START_BTB_FLUSH_SECTION \
343 END_BTB_FLUSH_SECTION
345 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
346 #define MC_BTB_FLUSH CRIT_BTB_FLUSH
347 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
349 #define GEN_BTB_FLUSH
350 #define CRIT_BTB_FLUSH
351 #define DBG_BTB_FLUSH
353 #define GDBELL_BTB_FLUSH
356 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
357 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
359 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
360 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
362 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
363 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
365 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
366 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
368 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
369 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
371 /* Variants of the "addition" argument for the prolog
373 #define PROLOG_ADDITION_NONE_GEN(n)
374 #define PROLOG_ADDITION_NONE_GDBELL(n)
375 #define PROLOG_ADDITION_NONE_CRIT(n)
376 #define PROLOG_ADDITION_NONE_DBG(n)
377 #define PROLOG_ADDITION_NONE_MC(n)
379 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
380 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
381 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
382 bne masked_interrupt_book3e_##n
384 #define PROLOG_ADDITION_2REGS_GEN(n) \
385 std r14,PACA_EXGEN+EX_R14(r13); \
386 std r15,PACA_EXGEN+EX_R15(r13)
388 #define PROLOG_ADDITION_1REG_GEN(n) \
389 std r14,PACA_EXGEN+EX_R14(r13);
391 #define PROLOG_ADDITION_2REGS_CRIT(n) \
392 std r14,PACA_EXCRIT+EX_R14(r13); \
393 std r15,PACA_EXCRIT+EX_R15(r13)
395 #define PROLOG_ADDITION_2REGS_DBG(n) \
396 std r14,PACA_EXDBG+EX_R14(r13); \
397 std r15,PACA_EXDBG+EX_R15(r13)
399 #define PROLOG_ADDITION_2REGS_MC(n) \
400 std r14,PACA_EXMC+EX_R14(r13); \
401 std r15,PACA_EXMC+EX_R15(r13)
404 /* Core exception code for all exceptions except TLB misses. */
405 #define EXCEPTION_COMMON_LVL(n, scratch, excf) \
407 std r0,GPR0(r1); /* save r0 in stackframe */ \
408 std r2,GPR2(r1); /* save r2 in stackframe */ \
409 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
410 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
411 std r9,GPR9(r1); /* save r9 in stackframe */ \
412 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
413 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
414 beq 2f; /* if from kernel mode */ \
415 ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \
416 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
417 ld r4,excf+EX_R11(r13); /* get back r11 */ \
418 mfspr r5,scratch; /* get back r13 */ \
419 std r12,GPR12(r1); /* save r12 in stackframe */ \
420 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
421 mflr r6; /* save LR in stackframe */ \
422 mfctr r7; /* save CTR in stackframe */ \
423 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
424 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
425 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
426 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \
427 ld r12,exception_marker@toc(r2); \
429 std r3,GPR10(r1); /* save r10 to stackframe */ \
430 std r4,GPR11(r1); /* save r11 to stackframe */ \
431 std r5,GPR13(r1); /* save it to stackframe */ \
435 li r3,(n)+1; /* indicate partial regs in trap */ \
436 std r9,0(r1); /* store stack frame back link */ \
437 std r10,_CCR(r1); /* store orig CR in stackframe */ \
438 std r9,GPR1(r1); /* store stack frame back link */ \
439 std r11,SOFTE(r1); /* and save it to stackframe */ \
440 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
441 std r3,_TRAP(r1); /* set trap number */ \
442 std r0,RESULT(r1); /* clear regs->result */
444 #define EXCEPTION_COMMON(n) \
445 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
446 #define EXCEPTION_COMMON_CRIT(n) \
447 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
448 #define EXCEPTION_COMMON_MC(n) \
449 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
450 #define EXCEPTION_COMMON_DBG(n) \
451 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
454 * This is meant for exceptions that don't immediately hard-enable. We
455 * set a bit in paca->irq_happened to ensure that a subsequent call to
456 * arch_local_irq_restore() will properly hard-enable and avoid the
457 * fast-path, and then reconcile irq state.
459 #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4)
462 * This is called by exceptions that don't use INTS_DISABLE (that did not
463 * touch irq indicators in the PACA). This will restore MSR:EE to it's
466 * XXX In the long run, we may want to open-code it in order to separate the
467 * load from the wrtee, thus limiting the latency caused by the dependency
468 * but at this point, I'll favor code clarity until we have a near to final
471 #define INTS_RESTORE_HARD \
475 /* XXX FIXME: Restore r14/r15 when necessary */
476 #define BAD_STACK_TRAMPOLINE(n) \
477 exc_##n##_bad_stack: \
478 li r1,(n); /* get exception number */ \
479 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
480 b bad_stack_book3e; /* bad stack error */
482 /* WARNING: If you change the layout of this stub, make sure you check
483 * the debug exception handler which handles single stepping
484 * into exceptions from userspace, and the MM code in
485 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
486 * and would need to be updated if that branch is moved
488 #define EXCEPTION_STUB(loc, label) \
489 . = interrupt_base_book3e + loc; \
490 nop; /* To make debug interrupts happy */ \
491 b exc_##label##_book3e;
501 /* Used by asynchronous interrupt that may happen in the idle loop.
503 * This check if the thread was in the idle loop, and if yes, returns
504 * to the caller rather than the PC. This is to avoid a race if
505 * interrupts happen before the wait instruction.
507 #define CHECK_NAPPING() \
508 CURRENT_THREAD_INFO(r11, r1); \
509 ld r10,TI_LOCAL_FLAGS(r11); \
510 andi. r9,r10,_TLF_NAPPING; \
513 rlwinm r7,r10,0,~_TLF_NAPPING; \
515 std r7,TI_LOCAL_FLAGS(r11); \
519 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
520 START_EXCEPTION(label); \
521 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
522 EXCEPTION_COMMON(trapnum) \
526 addi r3,r1,STACK_FRAME_OVERHEAD; \
528 b ret_from_except_lite;
530 /* This value is used to mark exception frames on the stack. */
533 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
537 * And here we have the exception vectors !
542 .globl interrupt_base_book3e
543 interrupt_base_book3e: /* fake trap */
544 EXCEPTION_STUB(0x000, machine_check)
545 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
546 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
547 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
548 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
549 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
550 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
551 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
552 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
553 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
554 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
555 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
556 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
557 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
558 EXCEPTION_STUB(0x1c0, data_tlb_miss)
559 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
560 EXCEPTION_STUB(0x200, altivec_unavailable)
561 EXCEPTION_STUB(0x220, altivec_assist)
562 EXCEPTION_STUB(0x260, perfmon)
563 EXCEPTION_STUB(0x280, doorbell)
564 EXCEPTION_STUB(0x2a0, doorbell_crit)
565 EXCEPTION_STUB(0x2c0, guest_doorbell)
566 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
567 EXCEPTION_STUB(0x300, hypercall)
568 EXCEPTION_STUB(0x320, ehpriv)
569 EXCEPTION_STUB(0x340, lrat_error)
571 .globl __end_interrupts
574 /* Critical Input Interrupt */
575 START_EXCEPTION(critical_input);
576 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
577 PROLOG_ADDITION_NONE)
578 EXCEPTION_COMMON_CRIT(0x100)
582 addi r3,r1,STACK_FRAME_OVERHEAD
584 b ret_from_crit_except
586 /* Machine Check Interrupt */
587 START_EXCEPTION(machine_check);
588 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
589 PROLOG_ADDITION_NONE)
590 EXCEPTION_COMMON_MC(0x000)
594 addi r3,r1,STACK_FRAME_OVERHEAD
595 bl machine_check_exception
598 /* Data Storage Interrupt */
599 START_EXCEPTION(data_storage)
600 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
601 PROLOG_ADDITION_2REGS)
604 EXCEPTION_COMMON(0x300)
606 b storage_fault_common
608 /* Instruction Storage Interrupt */
609 START_EXCEPTION(instruction_storage);
610 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
611 PROLOG_ADDITION_2REGS)
614 EXCEPTION_COMMON(0x400)
616 b storage_fault_common
618 /* External Input Interrupt */
619 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
620 external_input, do_IRQ, ACK_NONE)
623 START_EXCEPTION(alignment);
624 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
625 PROLOG_ADDITION_2REGS)
628 EXCEPTION_COMMON(0x600)
629 b alignment_more /* no room, go out of line */
631 /* Program Interrupt */
632 START_EXCEPTION(program);
633 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
634 PROLOG_ADDITION_1REG)
636 EXCEPTION_COMMON(0x700)
639 addi r3,r1,STACK_FRAME_OVERHEAD
640 ld r14,PACA_EXGEN+EX_R14(r13)
642 bl program_check_exception
645 /* Floating Point Unavailable Interrupt */
646 START_EXCEPTION(fp_unavailable);
647 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
648 PROLOG_ADDITION_NONE)
649 /* we can probably do a shorter exception entry for that one... */
650 EXCEPTION_COMMON(0x800)
655 b fast_exception_return
658 addi r3,r1,STACK_FRAME_OVERHEAD
659 bl kernel_fp_unavailable_exception
662 /* Altivec Unavailable Interrupt */
663 START_EXCEPTION(altivec_unavailable);
664 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
665 PROLOG_ADDITION_NONE)
666 /* we can probably do a shorter exception entry for that one... */
667 EXCEPTION_COMMON(0x200)
668 #ifdef CONFIG_ALTIVEC
674 b fast_exception_return
676 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
680 addi r3,r1,STACK_FRAME_OVERHEAD
681 bl altivec_unavailable_exception
685 START_EXCEPTION(altivec_assist);
686 NORMAL_EXCEPTION_PROLOG(0x220,
687 BOOKE_INTERRUPT_ALTIVEC_ASSIST,
688 PROLOG_ADDITION_NONE)
689 EXCEPTION_COMMON(0x220)
692 addi r3,r1,STACK_FRAME_OVERHEAD
693 #ifdef CONFIG_ALTIVEC
695 bl altivec_assist_exception
696 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
703 /* Decrementer Interrupt */
704 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
705 decrementer, timer_interrupt, ACK_DEC)
707 /* Fixed Interval Timer Interrupt */
708 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
709 fixed_interval, unknown_exception, ACK_FIT)
711 /* Watchdog Timer Interrupt */
712 START_EXCEPTION(watchdog);
713 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
714 PROLOG_ADDITION_NONE)
715 EXCEPTION_COMMON_CRIT(0x9f0)
719 addi r3,r1,STACK_FRAME_OVERHEAD
720 #ifdef CONFIG_BOOKE_WDT
725 b ret_from_crit_except
727 /* System Call Interrupt */
728 START_EXCEPTION(system_call)
729 mr r9,r13 /* keep a copy of userland r13 */
730 mfspr r11,SPRN_SRR0 /* get return address */
731 mfspr r12,SPRN_SRR1 /* get previous MSR */
732 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
735 /* Auxiliary Processor Unavailable Interrupt */
736 START_EXCEPTION(ap_unavailable);
737 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
738 PROLOG_ADDITION_NONE)
739 EXCEPTION_COMMON(0xf20)
742 addi r3,r1,STACK_FRAME_OVERHEAD
746 /* Debug exception as a critical interrupt*/
747 START_EXCEPTION(debug_crit);
748 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
749 PROLOG_ADDITION_2REGS)
752 * If there is a single step or branch-taken exception in an
753 * exception entry sequence, it was probably meant to apply to
754 * the code where the exception occurred (since exception entry
755 * doesn't turn off DE automatically). We simulate the effect
756 * of turning off DE on entry to an exception handler by turning
757 * off DE in the CSRR1 value and clearing the debug status.
760 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
761 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
764 #ifdef CONFIG_RELOCATABLE
766 ld r14,interrupt_base_book3e@got(r15)
767 ld r15,__end_interrupts@got(r15)
769 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
770 LOAD_REG_IMMEDIATE(r15,__end_interrupts)
777 /* here it looks like we got an inappropriate debug exception. */
778 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
779 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
782 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
783 ld r1,PACA_EXCRIT+EX_R1(r13)
784 ld r14,PACA_EXCRIT+EX_R14(r13)
785 ld r15,PACA_EXCRIT+EX_R15(r13)
787 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
788 ld r11,PACA_EXCRIT+EX_R11(r13)
789 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
792 /* Normal debug exception */
793 /* XXX We only handle coming from userspace for now since we can't
794 * quite save properly an interrupted kernel state yet
796 1: andi. r14,r11,MSR_PR; /* check for userspace again */
797 beq kernel_dbg_exc; /* if from kernel mode */
799 /* Now we mash up things to make it look like we are coming on a
803 EXCEPTION_COMMON_CRIT(0xd00)
805 addi r3,r1,STACK_FRAME_OVERHEAD
807 ld r14,PACA_EXCRIT+EX_R14(r13)
808 ld r15,PACA_EXCRIT+EX_R15(r13)
816 /* Debug exception as a debug interrupt*/
817 START_EXCEPTION(debug_debug);
818 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
819 PROLOG_ADDITION_2REGS)
822 * If there is a single step or branch-taken exception in an
823 * exception entry sequence, it was probably meant to apply to
824 * the code where the exception occurred (since exception entry
825 * doesn't turn off DE automatically). We simulate the effect
826 * of turning off DE on entry to an exception handler by turning
827 * off DE in the DSRR1 value and clearing the debug status.
830 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
831 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
834 #ifdef CONFIG_RELOCATABLE
836 ld r14,interrupt_base_book3e@got(r15)
837 ld r15,__end_interrupts@got(r15)
839 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
840 LOAD_REG_IMMEDIATE(r15,__end_interrupts)
847 /* here it looks like we got an inappropriate debug exception. */
848 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
849 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
852 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
853 ld r1,PACA_EXDBG+EX_R1(r13)
854 ld r14,PACA_EXDBG+EX_R14(r13)
855 ld r15,PACA_EXDBG+EX_R15(r13)
857 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
858 ld r11,PACA_EXDBG+EX_R11(r13)
859 mfspr r13,SPRN_SPRG_DBG_SCRATCH
862 /* Normal debug exception */
863 /* XXX We only handle coming from userspace for now since we can't
864 * quite save properly an interrupted kernel state yet
866 1: andi. r14,r11,MSR_PR; /* check for userspace again */
867 beq kernel_dbg_exc; /* if from kernel mode */
869 /* Now we mash up things to make it look like we are coming on a
873 EXCEPTION_COMMON_DBG(0xd08)
876 addi r3,r1,STACK_FRAME_OVERHEAD
878 ld r14,PACA_EXDBG+EX_R14(r13)
879 ld r15,PACA_EXDBG+EX_R15(r13)
884 START_EXCEPTION(perfmon);
885 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
886 PROLOG_ADDITION_NONE)
887 EXCEPTION_COMMON(0x260)
890 addi r3,r1,STACK_FRAME_OVERHEAD
891 bl performance_monitor_exception
892 b ret_from_except_lite
894 /* Doorbell interrupt */
895 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
896 doorbell, doorbell_exception, ACK_NONE)
898 /* Doorbell critical Interrupt */
899 START_EXCEPTION(doorbell_crit);
900 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
901 PROLOG_ADDITION_NONE)
902 EXCEPTION_COMMON_CRIT(0x2a0)
906 addi r3,r1,STACK_FRAME_OVERHEAD
908 b ret_from_crit_except
911 * Guest doorbell interrupt
912 * This general exception use GSRRx save/restore registers
914 START_EXCEPTION(guest_doorbell);
915 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
916 PROLOG_ADDITION_NONE)
917 EXCEPTION_COMMON(0x2c0)
918 addi r3,r1,STACK_FRAME_OVERHEAD
924 /* Guest Doorbell critical Interrupt */
925 START_EXCEPTION(guest_doorbell_crit);
926 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
927 PROLOG_ADDITION_NONE)
928 EXCEPTION_COMMON_CRIT(0x2e0)
932 addi r3,r1,STACK_FRAME_OVERHEAD
934 b ret_from_crit_except
936 /* Hypervisor call */
937 START_EXCEPTION(hypercall);
938 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
939 PROLOG_ADDITION_NONE)
940 EXCEPTION_COMMON(0x310)
941 addi r3,r1,STACK_FRAME_OVERHEAD
947 /* Embedded Hypervisor priviledged */
948 START_EXCEPTION(ehpriv);
949 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
950 PROLOG_ADDITION_NONE)
951 EXCEPTION_COMMON(0x320)
952 addi r3,r1,STACK_FRAME_OVERHEAD
958 /* LRAT Error interrupt */
959 START_EXCEPTION(lrat_error);
960 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
961 PROLOG_ADDITION_NONE)
962 EXCEPTION_COMMON(0x340)
963 addi r3,r1,STACK_FRAME_OVERHEAD
970 * An interrupt came in while soft-disabled; We mark paca->irq_happened
971 * accordingly and if the interrupt is level sensitive, we hard disable
972 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
973 * keep these in synch.
976 .macro masked_interrupt_book3e paca_irq full_mask
977 lbz r10,PACAIRQHAPPENED(r13)
979 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
981 ori r10,r10,\paca_irq
983 stb r10,PACAIRQHAPPENED(r13)
986 rldicl r10,r11,48,1 /* clear MSR_EE */
991 lwz r11,PACA_EXGEN+EX_CR(r13)
993 ld r10,PACA_EXGEN+EX_R10(r13)
994 ld r11,PACA_EXGEN+EX_R11(r13)
995 mfspr r13,SPRN_SPRG_GEN_SCRATCH
1000 masked_interrupt_book3e_0x500:
1001 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
1002 masked_interrupt_book3e PACA_IRQ_EE 1
1004 masked_interrupt_book3e_0x900:
1006 masked_interrupt_book3e PACA_IRQ_DEC 0
1008 masked_interrupt_book3e_0x980:
1010 masked_interrupt_book3e PACA_IRQ_DEC 0
1012 masked_interrupt_book3e_0x280:
1013 masked_interrupt_book3e_0x2c0:
1014 masked_interrupt_book3e PACA_IRQ_DBELL 0
1017 * Called from arch_local_irq_enable when an interrupt needs
1018 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
1019 * to indicate the kind of interrupt. MSR:EE is already off.
1020 * We generate a stackframe like if a real interrupt had happened.
1022 * Note: While MSR:EE is off, we need to make sure that _MSR
1023 * in the generated frame has EE set to 1 or the exception
1024 * handler will not properly re-enable them.
1026 _GLOBAL(__replay_interrupt)
1027 /* We are going to jump to the exception common code which
1028 * will retrieve various register values from the PACA which
1029 * we don't give a damn about.
1034 mtspr SPRN_SPRG_GEN_SCRATCH,r13;
1035 std r1,PACA_EXGEN+EX_R1(r13);
1036 stw r4,PACA_EXGEN+EX_CR(r13);
1038 subi r1,r1,INT_FRAME_SIZE;
1040 beq exc_0x500_common
1042 beq exc_0x900_common
1044 beq exc_0x280_common
1049 * This is called from 0x300 and 0x400 handlers after the prologs with
1050 * r14 and r15 containing the fault address and error code, with the
1051 * original values stashed away in the PACA
1053 storage_fault_common:
1056 addi r3,r1,STACK_FRAME_OVERHEAD
1059 ld r14,PACA_EXGEN+EX_R14(r13)
1060 ld r15,PACA_EXGEN+EX_R15(r13)
1064 b ret_from_except_lite
1067 addi r3,r1,STACK_FRAME_OVERHEAD
1073 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1079 addi r3,r1,STACK_FRAME_OVERHEAD
1080 ld r14,PACA_EXGEN+EX_R14(r13)
1081 ld r15,PACA_EXGEN+EX_R15(r13)
1084 bl alignment_exception
1088 * We branch here from entry_64.S for the last stage of the exception
1089 * return code path. MSR:EE is expected to be off at that point
1091 _GLOBAL(exception_return_book3e)
1094 /* This is the return from load_up_fpu fast path which could do with
1095 * less GPR restores in fact, but for now we have a single return path
1097 .globl fast_exception_return
1098 fast_exception_return:
1106 ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
1109 1: stdcx. r0,0,r1 /* to clear the reservation */
1123 mtspr SPRN_SPRG_GEN_SCRATCH,r0
1125 std r10,PACA_EXGEN+EX_R10(r13);
1126 std r11,PACA_EXGEN+EX_R11(r13);
1133 ld r10,PACA_EXGEN+EX_R10(r13)
1134 ld r11,PACA_EXGEN+EX_R11(r13)
1135 mfspr r13,SPRN_SPRG_GEN_SCRATCH
1139 * Trampolines used when spotting a bad kernel stack pointer in
1140 * the exception entry code.
1142 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1143 * index around, etc... to handle crit & mcheck
1145 BAD_STACK_TRAMPOLINE(0x000)
1146 BAD_STACK_TRAMPOLINE(0x100)
1147 BAD_STACK_TRAMPOLINE(0x200)
1148 BAD_STACK_TRAMPOLINE(0x220)
1149 BAD_STACK_TRAMPOLINE(0x260)
1150 BAD_STACK_TRAMPOLINE(0x280)
1151 BAD_STACK_TRAMPOLINE(0x2a0)
1152 BAD_STACK_TRAMPOLINE(0x2c0)
1153 BAD_STACK_TRAMPOLINE(0x2e0)
1154 BAD_STACK_TRAMPOLINE(0x300)
1155 BAD_STACK_TRAMPOLINE(0x310)
1156 BAD_STACK_TRAMPOLINE(0x320)
1157 BAD_STACK_TRAMPOLINE(0x340)
1158 BAD_STACK_TRAMPOLINE(0x400)
1159 BAD_STACK_TRAMPOLINE(0x500)
1160 BAD_STACK_TRAMPOLINE(0x600)
1161 BAD_STACK_TRAMPOLINE(0x700)
1162 BAD_STACK_TRAMPOLINE(0x800)
1163 BAD_STACK_TRAMPOLINE(0x900)
1164 BAD_STACK_TRAMPOLINE(0x980)
1165 BAD_STACK_TRAMPOLINE(0x9f0)
1166 BAD_STACK_TRAMPOLINE(0xa00)
1167 BAD_STACK_TRAMPOLINE(0xb00)
1168 BAD_STACK_TRAMPOLINE(0xc00)
1169 BAD_STACK_TRAMPOLINE(0xd00)
1170 BAD_STACK_TRAMPOLINE(0xd08)
1171 BAD_STACK_TRAMPOLINE(0xe00)
1172 BAD_STACK_TRAMPOLINE(0xf00)
1173 BAD_STACK_TRAMPOLINE(0xf20)
1175 .globl bad_stack_book3e
1177 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1178 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
1179 ld r1,PACAEMERGSP(r13)
1180 subi r1,r1,64+INT_FRAME_SIZE
1183 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1184 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1191 std r0,GPR0(r1); /* save r0 in stackframe */ \
1192 std r2,GPR2(r1); /* save r2 in stackframe */ \
1193 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
1194 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
1195 std r9,GPR9(r1); /* save r9 in stackframe */ \
1196 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
1197 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
1198 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1199 std r3,GPR10(r1); /* save r10 to stackframe */ \
1200 std r4,GPR11(r1); /* save r11 to stackframe */ \
1201 std r12,GPR12(r1); /* save r12 in stackframe */ \
1202 std r5,GPR13(r1); /* save it to stackframe */ \
1211 lhz r12,PACA_TRAP_SAVE(r13)
1213 addi r11,r1,INT_FRAME_SIZE
1218 1: addi r3,r1,STACK_FRAME_OVERHEAD
1223 * Setup the initial TLB for a core. This current implementation
1224 * assume that whatever we are running off will not conflict with
1225 * the new mapping at PAGE_OFFSET.
1227 _GLOBAL(initial_tlb_book3e)
1229 /* Look for the first TLB with IPROT set */
1230 mfspr r4,SPRN_TLB0CFG
1231 andi. r3,r4,TLBnCFG_IPROT
1232 lis r3,MAS0_TLBSEL(0)@h
1235 mfspr r4,SPRN_TLB1CFG
1236 andi. r3,r4,TLBnCFG_IPROT
1237 lis r3,MAS0_TLBSEL(1)@h
1240 mfspr r4,SPRN_TLB2CFG
1241 andi. r3,r4,TLBnCFG_IPROT
1242 lis r3,MAS0_TLBSEL(2)@h
1245 lis r3,MAS0_TLBSEL(3)@h
1246 mfspr r4,SPRN_TLB3CFG
1250 andi. r5,r4,TLBnCFG_HES
1253 mflr r8 /* save LR */
1254 /* 1. Find the index of the entry we're executing in
1256 * r3 = MAS0_TLBSEL (for the iprot array)
1259 bl invstr /* Find our address */
1260 invstr: mflr r6 /* Make it accessible */
1262 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
1267 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
1270 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
1272 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
1273 oris r7,r7,MAS1_IPROT@h
1277 /* 2. Invalidate all entries except the entry we're executing in
1279 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1281 * r5 = ESEL of entry we are running in
1283 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
1284 li r6,0 /* Set Entry counter to 0 */
1285 1: mr r7,r3 /* Set MAS0(TLBSEL) */
1286 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1290 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
1292 beq skpinv /* Dont update the current execution TLB */
1296 skpinv: addi r6,r6,1 /* Increment */
1297 cmpw r6,r4 /* Are we done? */
1298 bne 1b /* If not, repeat */
1300 /* Invalidate all TLBs */
1301 PPC_TLBILX_ALL(0,R0)
1305 /* 3. Setup a temp mapping and jump to it
1307 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1308 * r5 = ESEL of entry we are running in
1310 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1312 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
1316 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
1320 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
1328 bl 1f /* Find our address */
1330 addi r6,r6,(2f - 1b)
1335 /* 4. Clear out PIDs & Search info
1337 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1338 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1345 /* 5. Invalidate mapping we started in
1347 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1348 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1354 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
1361 * The mapping only needs to be cache-coherent on SMP, except on
1362 * Freescale e500mc derivatives where it's also needed for coherent DMA.
1364 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
1365 #define M_IF_NEEDED MAS2_M
1367 #define M_IF_NEEDED 0
1370 /* 6. Setup KERNELBASE mapping in TLB[0]
1372 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1373 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1376 rlwinm r3,r3,0,16,3 /* clear ESEL */
1378 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1379 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1382 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED)
1386 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1393 /* 7. Jump to KERNELBASE mapping
1395 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1397 /* Now we branch the new virtual address mapped by this entry */
1398 bl 1f /* Find our address */
1400 addi r6,r6,(2f - 1b)
1403 ori r7,r7,MSR_KERNEL@l
1406 rfi /* start execution out of TLB1[0] entry */
1409 /* 8. Clear out the temp mapping
1411 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1416 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
1422 /* We translate LR and return */
1428 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1429 * kernel linear mapping. We also set MAS8 once for all here though
1430 * that will have to be made dependent on whether we are running under
1431 * a hypervisor I suppose.
1435 * This code is called as an ordinary function on the boot CPU. But to
1436 * avoid duplication, this code is also used in SCOM bringup of
1437 * secondary CPUs. We read the code between the initial_tlb_code_start
1438 * and initial_tlb_code_end labels one instruction at a time and RAM it
1439 * into the new core via SCOM. That doesn't process branches, so there
1440 * must be none between those two labels. It also means if this code
1441 * ever takes any parameters, the SCOM code must also be updated to
1444 .globl a2_tlbinit_code_start
1445 a2_tlbinit_code_start:
1447 ori r11,r3,MAS0_WQ_ALLWAYS
1448 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1450 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1451 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1453 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1455 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1456 mtspr SPRN_MAS7_MAS3,r3
1460 /* Write the TLB entry */
1463 .globl a2_tlbinit_after_linear_map
1464 a2_tlbinit_after_linear_map:
1466 /* Now we branch the new virtual address mapped by this entry */
1467 LOAD_REG_IMMEDIATE(r3,1f)
1471 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1472 * else (including IPROTed things left by firmware)
1474 * r3 = current address (more or less)
1481 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1482 rlwinm r10,r4,8,0xff
1483 addi r10,r10,-1 /* Get inner loop mask */
1488 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1491 rldicr r6,r6,0,51 /* Extract EPN */
1494 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1496 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1501 rlwimi r7,r4,16,MAS0_ESEL_MASK
1512 addis r6,r6,(1<<30)@h
1517 .globl a2_tlbinit_after_iprot_flush
1518 a2_tlbinit_after_iprot_flush:
1524 .globl a2_tlbinit_code_end
1525 a2_tlbinit_code_end:
1527 /* We translate LR and return */
1534 * Main entry (boot CPU, thread 0)
1536 * We enter here from head_64.S, possibly after the prom_init trampoline
1537 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1538 * mode. Anything else is as it was left by the bootloader
1540 * Initial requirements of this port:
1542 * - Kernel loaded at 0 physical
1543 * - A good lump of memory mapped 0:0 by UTLB entry 0
1544 * - MSR:IS & MSR:DS set to 0
1546 * Note that some of the above requirements will be relaxed in the future
1547 * as the kernel becomes smarter at dealing with different initial conditions
1548 * but for now you have to be careful
1550 _GLOBAL(start_initialization_book3e)
1553 /* First, we need to setup some initial TLBs to map the kernel
1554 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1555 * and always use AS 0, so we just set it up to match our link
1556 * address and never use 0 based addresses.
1558 bl initial_tlb_book3e
1560 /* Init global core bits */
1563 /* Init per-thread bits */
1564 bl init_thread_book3e
1566 /* Return to common init code */
1573 * Secondary core/processor entry
1575 * This is entered for thread 0 of a secondary core, all other threads
1576 * are expected to be stopped. It's similar to start_initialization_book3e
1577 * except that it's generally entered from the holding loop in head_64.S
1578 * after CPUs have been gathered by Open Firmware.
1580 * We assume we are in 32 bits mode running with whatever TLB entry was
1581 * set for us by the firmware or POR engine.
1583 _GLOBAL(book3e_secondary_core_init_tlb_set)
1585 b generic_secondary_smp_init
1587 _GLOBAL(book3e_secondary_core_init)
1590 /* Do we need to setup initial TLB entry ? */
1594 /* Setup TLB for this core */
1595 bl initial_tlb_book3e
1597 /* We can return from the above running at a different
1598 * address, so recalculate r2 (TOC)
1602 /* Init global core bits */
1603 2: bl init_core_book3e
1605 /* Init per-thread bits */
1606 3: bl init_thread_book3e
1608 /* Return to common init code at proper virtual address.
1610 * Due to various previous assumptions, we know we entered this
1611 * function at either the final PAGE_OFFSET mapping or using a
1612 * 1:1 mapping at 0, so we don't bother doing a complicated check
1613 * here, we just ensure the return address has the right top bits.
1615 * Note that if we ever want to be smarter about where we can be
1616 * started from, we have to be careful that by the time we reach
1617 * the code below we may already be running at a different location
1618 * than the one we were called from since initial_tlb_book3e can
1619 * have moved us already.
1623 lis r3,PAGE_OFFSET@highest
1629 _GLOBAL(book3e_secondary_thread_init)
1633 .globl init_core_book3e
1635 /* Establish the interrupt vector base */
1637 LOAD_REG_ADDR(r3, interrupt_base_book3e)
1643 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1646 /* Make sure interrupts are off */
1649 /* disable all timers and clear out status */
1657 _GLOBAL(__setup_base_ivors)
1658 SET_IVOR(0, 0x020) /* Critical Input */
1659 SET_IVOR(1, 0x000) /* Machine Check */
1660 SET_IVOR(2, 0x060) /* Data Storage */
1661 SET_IVOR(3, 0x080) /* Instruction Storage */
1662 SET_IVOR(4, 0x0a0) /* External Input */
1663 SET_IVOR(5, 0x0c0) /* Alignment */
1664 SET_IVOR(6, 0x0e0) /* Program */
1665 SET_IVOR(7, 0x100) /* FP Unavailable */
1666 SET_IVOR(8, 0x120) /* System Call */
1667 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1668 SET_IVOR(10, 0x160) /* Decrementer */
1669 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1670 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1671 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1672 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1673 SET_IVOR(15, 0x040) /* Debug */
1679 _GLOBAL(setup_altivec_ivors)
1680 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1681 SET_IVOR(33, 0x220) /* AltiVec Assist */
1684 _GLOBAL(setup_perfmon_ivor)
1685 SET_IVOR(35, 0x260) /* Performance Monitor */
1688 _GLOBAL(setup_doorbell_ivors)
1689 SET_IVOR(36, 0x280) /* Processor Doorbell */
1690 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1693 _GLOBAL(setup_ehv_ivors)
1694 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1695 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1696 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1697 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1700 _GLOBAL(setup_lrat_ivor)
1701 SET_IVOR(42, 0x340) /* LRAT Error */