1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/alternative-asm.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/ctl_reg.h>
18 #include <asm/dwarf.h>
19 #include <asm/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/unistd.h>
27 #include <asm/vx-insn.h>
28 #include <asm/setup.h>
30 #include <asm/export.h>
31 #include <asm/nospec-insn.h>
34 __PT_R1 = __PT_GPRS + 8
35 __PT_R2 = __PT_GPRS + 16
36 __PT_R3 = __PT_GPRS + 24
37 __PT_R4 = __PT_GPRS + 32
38 __PT_R5 = __PT_GPRS + 40
39 __PT_R6 = __PT_GPRS + 48
40 __PT_R7 = __PT_GPRS + 56
41 __PT_R8 = __PT_GPRS + 64
42 __PT_R9 = __PT_GPRS + 72
43 __PT_R10 = __PT_GPRS + 80
44 __PT_R11 = __PT_GPRS + 88
45 __PT_R12 = __PT_GPRS + 96
46 __PT_R13 = __PT_GPRS + 104
47 __PT_R14 = __PT_GPRS + 112
48 __PT_R15 = __PT_GPRS + 120
50 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
52 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
54 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
55 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
56 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
57 _TIF_SYSCALL_TRACEPOINT)
58 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
59 _CIF_ASCE_SECONDARY | _CIF_FPU)
60 _PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
62 _LPP_OFFSET = __LC_LPP
64 #define BASED(name) name-cleanup_critical(%r13)
67 #ifdef CONFIG_TRACE_IRQFLAGS
69 brasl %r14,trace_hardirqs_on_caller
74 #ifdef CONFIG_TRACE_IRQFLAGS
76 brasl %r14,trace_hardirqs_off_caller
80 .macro LOCKDEP_SYS_EXIT
82 tm __PT_PSW+1(%r11),0x01 # returning to user ?
84 brasl %r14,lockdep_sys_exit
88 .macro CHECK_STACK stacksize,savearea
89 #ifdef CONFIG_CHECK_STACK
90 tml %r15,\stacksize - CONFIG_STACK_GUARD
96 .macro SWITCH_ASYNC savearea,timer
97 tmhh %r8,0x0001 # interrupting from user ?
100 slg %r14,BASED(.Lcritical_start)
101 clg %r14,BASED(.Lcritical_length)
103 lghi %r11,\savearea # inside critical section, do cleanup
104 brasl %r14,cleanup_critical
105 tmhh %r8,0x0001 # retest problem state after cleanup
107 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
109 srag %r14,%r14,STACK_SHIFT
111 CHECK_STACK 1<<STACK_SHIFT,\savearea
112 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
114 1: UPDATE_VTIME %r14,%r15,\timer
115 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
116 2: lg %r15,__LC_ASYNC_STACK # load async stack
117 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
120 .macro UPDATE_VTIME w1,w2,enter_timer
121 lg \w1,__LC_EXIT_TIMER
122 lg \w2,__LC_LAST_UPDATE_TIMER
124 slg \w2,__LC_EXIT_TIMER
125 alg \w1,__LC_USER_TIMER
126 alg \w2,__LC_SYSTEM_TIMER
127 stg \w1,__LC_USER_TIMER
128 stg \w2,__LC_SYSTEM_TIMER
129 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
133 stg %r8,__LC_RETURN_PSW
134 ni __LC_RETURN_PSW,0xbf
139 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
140 .insn s,0xb27c0000,\savearea # store clock fast
142 .insn s,0xb2050000,\savearea # store clock
147 * The TSTMSK macro generates a test-under-mask instruction by
148 * calculating the memory offset for the specified mask value.
149 * Mask value can be any constant. The macro shifts the mask
150 * value to calculate the memory offset for the test-under-mask
153 .macro TSTMSK addr, mask, size=8, bytepos=0
154 .if (\bytepos < \size) && (\mask >> 8)
156 .error "Mask exceeds byte boundary"
158 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
162 .error "Mask must not be zero"
164 off = \size - \bytepos - 1
169 ALTERNATIVE "", ".long 0xb2e8c000", 82
173 ALTERNATIVE "", ".long 0xb2e8d000", 82
176 .macro BPENTER tif_ptr,tif_mask
177 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
181 .macro BPEXIT tif_ptr,tif_mask
182 TSTMSK \tif_ptr,\tif_mask
183 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
184 "jnz .+8; .long 0xb2e8d000", 82
189 GEN_BR_THUNK %r14,%r11
191 .section .kprobes.text, "ax"
194 * This nop exists only in order to avoid that __switch_to starts at
195 * the beginning of the kprobes text section. In that case we would
196 * have several symbols at the same address. E.g. objdump would take
197 * an arbitrary symbol name when disassembling this code.
198 * With the added nop in between the __switch_to symbol is unique
209 * Scheduler resume function, called by switch_to
210 * gpr2 = (task_struct *) prev
211 * gpr3 = (task_struct *) next
216 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
217 lghi %r4,__TASK_stack
218 lghi %r1,__TASK_thread
219 lg %r5,0(%r4,%r3) # start of kernel stack of next
220 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
222 aghi %r15,STACK_INIT # end of kernel stack of next
223 stg %r3,__LC_CURRENT # store task struct of next
224 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
225 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
227 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
228 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
229 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
234 #if IS_ENABLED(CONFIG_KVM)
236 * sie64a calling convention:
237 * %r2 pointer to sie control block
238 * %r3 guest register save area
241 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
243 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
244 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
245 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
246 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
247 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
248 jno .Lsie_load_guest_gprs
249 brasl %r14,load_fpu_regs # load guest fp/vx regs
250 .Lsie_load_guest_gprs:
251 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
252 lg %r14,__LC_GMAP # get gmap pointer
255 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
257 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
258 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
259 tm __SIE_PROG20+3(%r14),3 # last exit...
261 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
262 jo .Lsie_skip # exit if fp/vx regs changed
263 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
268 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
270 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
271 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
273 # some program checks are suppressing. C code (e.g. do_protection_exception)
274 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
275 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
276 # Other instructions between sie64a and .Lsie_done should not cause program
277 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
278 # See also .Lcleanup_sie
287 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
288 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
289 xgr %r0,%r0 # clear guest registers to
290 xgr %r1,%r1 # prevent speculative use
295 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
296 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
300 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
303 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
304 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
305 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
306 EX_TABLE(sie_exit,.Lsie_fault)
307 EXPORT_SYMBOL(sie64a)
308 EXPORT_SYMBOL(sie_exit)
312 * SVC interrupt handler routine. System calls are synchronous events and
313 * are executed with interrupts enabled.
317 stpt __LC_SYNC_ENTER_TIMER
319 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
322 lghi %r13,__TASK_thread
323 lghi %r14,_PIF_SYSCALL
325 lg %r15,__LC_KERNEL_STACK
326 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
328 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
329 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
330 stmg %r0,%r7,__PT_R0(%r11)
331 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
332 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
333 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
334 stg %r14,__PT_FLAGS(%r11)
336 # clear user controlled register to prevent speculative use
338 # load address of system call table
339 lg %r10,__THREAD_sysc_table(%r13,%r12)
340 llgh %r8,__PT_INT_CODE+2(%r11)
341 slag %r8,%r8,2 # shift and test for svc 0
343 # svc 0: system call number in %r1
344 llgfr %r1,%r1 # clear high word in r1
347 sth %r1,__PT_INT_CODE+2(%r11)
350 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
351 stg %r2,__PT_ORIG_GPR2(%r11)
352 stg %r7,STACK_FRAME_OVERHEAD(%r15)
353 lgf %r9,0(%r8,%r10) # get system call add.
354 TSTMSK __TI_flags(%r12),_TIF_TRACE
356 BASR_EX %r14,%r9 # call sys_xxxx
357 stg %r2,__PT_R2(%r11) # store return value
360 #ifdef CONFIG_DEBUG_RSEQ
362 brasl %r14,rseq_syscall
366 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
368 TSTMSK __TI_flags(%r12),_TIF_WORK
369 jnz .Lsysc_work # check for work
370 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
372 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
374 lg %r14,__LC_VDSO_PER_CPU
375 lmg %r0,%r10,__PT_R0(%r11)
376 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
379 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
380 lmg %r11,%r15,__PT_R11(%r11)
381 lpswe __LC_RETURN_PSW
385 # One of the work bits is on. Find out which one.
388 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
389 jo .Lsysc_mcck_pending
390 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
392 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
393 jo .Lsysc_syscall_restart
394 #ifdef CONFIG_UPROBES
395 TSTMSK __TI_flags(%r12),_TIF_UPROBE
396 jo .Lsysc_uprobe_notify
398 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
399 jo .Lsysc_guarded_storage
400 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
402 #ifdef CONFIG_LIVEPATCH
403 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
404 jo .Lsysc_patch_pending # handle live patching just before
405 # signals and possible syscall restart
407 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
408 jo .Lsysc_syscall_restart
409 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
411 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
412 jo .Lsysc_notify_resume
413 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
415 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
417 j .Lsysc_return # beware of critical section cleanup
420 # _TIF_NEED_RESCHED is set, call schedule
423 larl %r14,.Lsysc_return
427 # _CIF_MCCK_PENDING is set, call handler
430 larl %r14,.Lsysc_return
431 jg s390_handle_mcck # TIF bit will be cleared by handler
434 # _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
437 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
438 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
439 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
441 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
442 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
443 jnz .Lsysc_set_fs_fixup
444 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
445 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
449 larl %r14,.Lsysc_return
453 # CIF_FPU is set, restore floating-point controls and floating-point registers.
456 larl %r14,.Lsysc_return
460 # _TIF_SIGPENDING is set, call do_signal
463 lgr %r2,%r11 # pass pointer to pt_regs
465 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
468 lghi %r13,__TASK_thread
469 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
470 lghi %r1,0 # svc 0 returns -ENOSYS
474 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
476 .Lsysc_notify_resume:
477 lgr %r2,%r11 # pass pointer to pt_regs
478 larl %r14,.Lsysc_return
482 # _TIF_UPROBE is set, call uprobe_notify_resume
484 #ifdef CONFIG_UPROBES
485 .Lsysc_uprobe_notify:
486 lgr %r2,%r11 # pass pointer to pt_regs
487 larl %r14,.Lsysc_return
488 jg uprobe_notify_resume
492 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
494 .Lsysc_guarded_storage:
495 lgr %r2,%r11 # pass pointer to pt_regs
496 larl %r14,.Lsysc_return
499 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
501 #ifdef CONFIG_LIVEPATCH
502 .Lsysc_patch_pending:
503 lg %r2,__LC_CURRENT # pass pointer to task struct
504 larl %r14,.Lsysc_return
505 jg klp_update_patch_state
509 # _PIF_PER_TRAP is set, call do_per_trap
512 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
513 lgr %r2,%r11 # pass pointer to pt_regs
514 larl %r14,.Lsysc_return
518 # _PIF_SYSCALL_RESTART is set, repeat the current system call
520 .Lsysc_syscall_restart:
521 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
522 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
523 lg %r2,__PT_ORIG_GPR2(%r11)
527 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
528 # and after the system call
531 lgr %r2,%r11 # pass pointer to pt_regs
533 llgh %r0,__PT_INT_CODE+2(%r11)
534 stg %r0,__PT_R2(%r11)
535 brasl %r14,do_syscall_trace_enter
542 lmg %r3,%r7,__PT_R3(%r11)
543 stg %r7,STACK_FRAME_OVERHEAD(%r15)
544 lg %r2,__PT_ORIG_GPR2(%r11)
545 BASR_EX %r14,%r9 # call sys_xxx
546 stg %r2,__PT_R2(%r11) # store return value
548 TSTMSK __TI_flags(%r12),_TIF_TRACE
550 lgr %r2,%r11 # pass pointer to pt_regs
551 larl %r14,.Lsysc_return
552 jg do_syscall_trace_exit
555 # a new process exits the kernel with ret_from_fork
558 la %r11,STACK_FRAME_OVERHEAD(%r15)
560 brasl %r14,schedule_tail
562 ssm __LC_SVC_NEW_PSW # reenable interrupts
563 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
565 # it's a kernel thread
566 lmg %r9,%r10,__PT_R9(%r11) # load gprs
567 ENTRY(kernel_thread_starter)
573 * Program check handler routine
576 ENTRY(pgm_check_handler)
577 stpt __LC_SYNC_ENTER_TIMER
579 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
580 lg %r10,__LC_LAST_BREAK
583 larl %r13,cleanup_critical
584 lmg %r8,%r9,__LC_PGM_OLD_PSW
585 tmhh %r8,0x0001 # test problem state bit
586 jnz 2f # -> fault in user space
587 #if IS_ENABLED(CONFIG_KVM)
588 # cleanup critical section for program checks in sie64a
590 slg %r14,BASED(.Lsie_critical_start)
591 clg %r14,BASED(.Lsie_critical_length)
593 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
594 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
595 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
596 larl %r9,sie_exit # skip forward to sie_exit
597 lghi %r11,_PIF_GUEST_FAULT
599 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
600 jnz 1f # -> enabled, can't be a double fault
601 tm __LC_PGM_ILC+3,0x80 # check for per exception
602 jnz .Lpgm_svcper # -> single stepped svc
603 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
604 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
606 2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
607 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
608 lg %r15,__LC_KERNEL_STACK
610 aghi %r14,__TASK_thread # pointer to thread_struct
611 lghi %r13,__LC_PGM_TDB
612 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
614 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
615 3: stg %r10,__THREAD_last_break(%r14)
617 la %r11,STACK_FRAME_OVERHEAD(%r15)
618 stmg %r0,%r7,__PT_R0(%r11)
619 # clear user controlled registers to prevent speculative use
628 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
629 stmg %r8,%r9,__PT_PSW(%r11)
630 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
631 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
632 stg %r13,__PT_FLAGS(%r11)
633 stg %r10,__PT_ARGS(%r11)
634 tm __LC_PGM_ILC+3,0x80 # check for per exception
636 tmhh %r8,0x0001 # kernel per event ?
638 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
639 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
640 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
641 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
643 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
644 larl %r1,pgm_check_table
645 llgh %r10,__PT_INT_CODE+2(%r11)
649 lgf %r9,0(%r10,%r1) # load address of handler routine
650 lgr %r2,%r11 # pass pointer to pt_regs
651 BASR_EX %r14,%r9 # branch to interrupt-handler
654 tm __PT_PSW+1(%r11),0x01 # returning to user ?
656 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
661 # PER event in supervisor state, must be kprobes
665 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
666 lgr %r2,%r11 # pass pointer to pt_regs
667 brasl %r14,do_per_trap
671 # single stepped system call
674 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
675 lghi %r13,__TASK_thread
677 stg %r14,__LC_RETURN_PSW+8
678 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
679 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
682 * IO interrupt handler routine
684 ENTRY(io_int_handler)
686 stpt __LC_ASYNC_ENTER_TIMER
688 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
690 larl %r13,cleanup_critical
691 lmg %r8,%r9,__LC_IO_OLD_PSW
692 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
693 stmg %r0,%r7,__PT_R0(%r11)
694 # clear user controlled registers to prevent speculative use
704 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
705 stmg %r8,%r9,__PT_PSW(%r11)
706 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
707 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
708 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
711 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
713 lgr %r2,%r11 # pass pointer to pt_regs
714 lghi %r3,IO_INTERRUPT
715 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
717 lghi %r3,THIN_INTERRUPT
720 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
724 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
730 TSTMSK __TI_flags(%r12),_TIF_WORK
731 jnz .Lio_work # there is work to do (signals etc.)
732 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
735 lg %r14,__LC_VDSO_PER_CPU
736 lmg %r0,%r10,__PT_R0(%r11)
737 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
738 tm __PT_PSW+1(%r11),0x01 # returning to user ?
740 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
743 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
745 lmg %r11,%r15,__PT_R11(%r11)
746 lpswe __LC_RETURN_PSW
750 # There is work todo, find out in which context we have been interrupted:
751 # 1) if we return to user space we can do all _TIF_WORK work
752 # 2) if we return to kernel code and kvm is enabled check if we need to
753 # modify the psw to leave SIE
754 # 3) if we return to kernel code and preemptive scheduling is enabled check
755 # the preemption counter and if it is zero call preempt_schedule_irq
756 # Before any work can be done, a switch to the kernel stack is required.
759 tm __PT_PSW+1(%r11),0x01 # returning to user ?
760 jo .Lio_work_user # yes -> do resched & signal
761 #ifdef CONFIG_PREEMPT
762 # check for preemptive scheduling
763 icm %r0,15,__LC_PREEMPT_COUNT
764 jnz .Lio_restore # preemption is disabled
765 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
767 # switch to kernel stack
768 lg %r1,__PT_R15(%r11)
769 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
770 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
771 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
772 la %r11,STACK_FRAME_OVERHEAD(%r1)
774 # TRACE_IRQS_ON already done at .Lio_return, call
775 # TRACE_IRQS_OFF to keep things symmetrical
777 brasl %r14,preempt_schedule_irq
784 # Need to do work before returning to userspace, switch to kernel stack
787 lg %r1,__LC_KERNEL_STACK
788 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
789 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
790 la %r11,STACK_FRAME_OVERHEAD(%r1)
794 # One of the work bits is on. Find out which one.
797 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
799 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
801 #ifdef CONFIG_LIVEPATCH
802 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
803 jo .Lio_patch_pending
805 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
807 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
808 jo .Lio_notify_resume
809 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
810 jo .Lio_guarded_storage
811 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
813 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
815 j .Lio_return # beware of critical section cleanup
818 # _CIF_MCCK_PENDING is set, call handler
821 # TRACE_IRQS_ON already done at .Lio_return
822 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
827 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
830 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
831 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
832 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
834 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
835 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
836 jnz .Lio_set_fs_fixup
837 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
838 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
842 larl %r14,.Lio_return
846 # CIF_FPU is set, restore floating-point controls and floating-point registers.
849 larl %r14,.Lio_return
853 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
855 .Lio_guarded_storage:
856 # TRACE_IRQS_ON already done at .Lio_return
857 ssm __LC_SVC_NEW_PSW # reenable interrupts
858 lgr %r2,%r11 # pass pointer to pt_regs
859 brasl %r14,gs_load_bc_cb
860 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
865 # _TIF_NEED_RESCHED is set, call schedule
868 # TRACE_IRQS_ON already done at .Lio_return
869 ssm __LC_SVC_NEW_PSW # reenable interrupts
870 brasl %r14,schedule # call scheduler
871 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
876 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
878 #ifdef CONFIG_LIVEPATCH
880 lg %r2,__LC_CURRENT # pass pointer to task struct
881 larl %r14,.Lio_return
882 jg klp_update_patch_state
886 # _TIF_SIGPENDING or is set, call do_signal
889 # TRACE_IRQS_ON already done at .Lio_return
890 ssm __LC_SVC_NEW_PSW # reenable interrupts
891 lgr %r2,%r11 # pass pointer to pt_regs
893 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
898 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
901 # TRACE_IRQS_ON already done at .Lio_return
902 ssm __LC_SVC_NEW_PSW # reenable interrupts
903 lgr %r2,%r11 # pass pointer to pt_regs
904 brasl %r14,do_notify_resume
905 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
910 * External interrupt handler routine
912 ENTRY(ext_int_handler)
914 stpt __LC_ASYNC_ENTER_TIMER
916 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
918 larl %r13,cleanup_critical
919 lmg %r8,%r9,__LC_EXT_OLD_PSW
920 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
921 stmg %r0,%r7,__PT_R0(%r11)
922 # clear user controlled registers to prevent speculative use
932 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
933 stmg %r8,%r9,__PT_PSW(%r11)
934 lghi %r1,__LC_EXT_PARAMS2
935 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
936 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
937 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
938 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
939 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
942 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
943 lgr %r2,%r11 # pass pointer to pt_regs
944 lghi %r3,EXT_INTERRUPT
949 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
952 stg %r14,(__SF_GPRS+8*8)(%r15)
953 stg %r3,__SF_EMPTY(%r15)
954 larl %r1,.Lpsw_idle_lpsw+4
955 stg %r1,__SF_EMPTY+8(%r15)
957 larl %r1,smp_cpu_mtid
961 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
964 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
966 STCK __CLOCK_IDLE_ENTER(%r2)
967 stpt __TIMER_IDLE_ENTER(%r2)
969 lpswe __SF_EMPTY(%r15)
974 * Store floating-point controls and floating-point or vector register
975 * depending whether the vector facility is available. A critical section
976 * cleanup assures that the registers are stored even if interrupted for
977 * some other work. The CIF_FPU flag is set to trigger a lazy restore
978 * of the register contents at return from io or a system call.
982 aghi %r2,__TASK_thread
983 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
984 jo .Lsave_fpu_regs_exit
985 stfpc __THREAD_FPU_fpc(%r2)
986 lg %r3,__THREAD_FPU_regs(%r2)
987 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
988 jz .Lsave_fpu_regs_fp # no -> store FP regs
989 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
990 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
991 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
1009 .Lsave_fpu_regs_done:
1010 oi __LC_CPU_FLAGS+7,_CIF_FPU
1011 .Lsave_fpu_regs_exit:
1013 .Lsave_fpu_regs_end:
1014 EXPORT_SYMBOL(save_fpu_regs)
1017 * Load floating-point controls and floating-point or vector registers.
1018 * A critical section cleanup assures that the register contents are
1019 * loaded even if interrupted for some other work.
1021 * There are special calling conventions to fit into sysc and io return work:
1022 * %r15: <kernel stack>
1023 * The function requires:
1028 aghi %r4,__TASK_thread
1029 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1030 jno .Lload_fpu_regs_exit
1031 lfpc __THREAD_FPU_fpc(%r4)
1032 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1033 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
1034 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
1036 VLM %v16,%v31,256,%r4
1037 j .Lload_fpu_regs_done
1055 .Lload_fpu_regs_done:
1056 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1057 .Lload_fpu_regs_exit:
1059 .Lload_fpu_regs_end:
1064 * Machine check handler routines
1066 ENTRY(mcck_int_handler)
1067 STCK __LC_MCCK_CLOCK
1069 la %r1,4095 # validate r1
1070 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
1071 sckc __LC_CLOCK_COMPARATOR # validate comparator
1072 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1073 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1074 lg %r12,__LC_CURRENT
1075 larl %r13,cleanup_critical
1076 lmg %r8,%r9,__LC_MCK_OLD_PSW
1077 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1078 jo .Lmcck_panic # yes -> rest of mcck code invalid
1079 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
1080 jno .Lmcck_panic # control registers invalid -> panic
1082 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1084 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1085 nill %r11,0xfc00 # MCESA_ORIGIN_MASK
1086 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1088 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID
1090 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
1091 0: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1092 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID
1096 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1098 lghi %r14,__LC_FPREGS_SAVE_AREA
1116 0: VLM %v0,%v15,0,%r11
1117 VLM %v16,%v31,256,%r11
1118 1: lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1119 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1120 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1122 la %r14,__LC_SYNC_ENTER_TIMER
1123 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1125 la %r14,__LC_ASYNC_ENTER_TIMER
1126 0: clc 0(8,%r14),__LC_EXIT_TIMER
1128 la %r14,__LC_EXIT_TIMER
1129 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1131 la %r14,__LC_LAST_UPDATE_TIMER
1133 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1134 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1136 tmhh %r8,0x0001 # interrupting from user ?
1138 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1140 4: SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1142 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1143 stmg %r0,%r7,__PT_R0(%r11)
1144 # clear user controlled registers to prevent speculative use
1154 mvc __PT_R8(64,%r11),0(%r14)
1155 stmg %r8,%r9,__PT_PSW(%r11)
1156 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1157 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1158 lgr %r2,%r11 # pass pointer to pt_regs
1159 brasl %r14,s390_do_machine_check
1160 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1162 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1163 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1164 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1165 la %r11,STACK_FRAME_OVERHEAD(%r1)
1167 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1168 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1171 brasl %r14,s390_handle_mcck
1174 lg %r14,__LC_VDSO_PER_CPU
1175 lmg %r0,%r10,__PT_R0(%r11)
1176 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1177 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1179 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1180 stpt __LC_EXIT_TIMER
1181 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
1182 0: lmg %r11,%r15,__PT_R11(%r11)
1183 lpswe __LC_RETURN_MCCK_PSW
1186 lg %r15,__LC_PANIC_STACK
1187 la %r11,STACK_FRAME_OVERHEAD(%r15)
1191 # PSW restart interrupt handler
1193 ENTRY(restart_int_handler)
1194 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
1195 stg %r15,__LC_SAVE_AREA_RESTART
1196 lg %r15,__LC_RESTART_STACK
1197 aghi %r15,-__PT_SIZE # create pt_regs on stack
1198 xc 0(__PT_SIZE,%r15),0(%r15)
1199 stmg %r0,%r14,__PT_R0(%r15)
1200 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1201 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1202 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
1203 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1204 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1205 lg %r2,__LC_RESTART_DATA
1206 lg %r3,__LC_RESTART_SOURCE
1207 ltgr %r3,%r3 # test source cpu address
1208 jm 1f # negative -> skip source stop
1209 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1210 brc 10,0b # wait for status stored
1211 1: basr %r14,%r1 # call function
1212 stap __SF_EMPTY(%r15) # store cpu address
1213 llgh %r3,__SF_EMPTY(%r15)
1214 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1218 .section .kprobes.text, "ax"
1220 #ifdef CONFIG_CHECK_STACK
1222 * The synchronous or the asynchronous stack overflowed. We are dead.
1223 * No need to properly save the registers, we are going to panic anyway.
1224 * Setup a pt_regs so that show_trace can provide a good call trace.
1227 lg %r15,__LC_PANIC_STACK # change to panic stack
1228 la %r11,STACK_FRAME_OVERHEAD(%r15)
1229 stmg %r0,%r7,__PT_R0(%r11)
1230 stmg %r8,%r9,__PT_PSW(%r11)
1231 mvc __PT_R8(64,%r11),0(%r14)
1232 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1233 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1234 lgr %r2,%r11 # pass pointer to pt_regs
1235 jg kernel_stack_overflow
1239 #if IS_ENABLED(CONFIG_KVM)
1240 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1242 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1245 clg %r9,BASED(.Lcleanup_table) # system_call
1247 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1248 jl .Lcleanup_system_call
1249 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1251 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1252 jl .Lcleanup_sysc_tif
1253 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1254 jl .Lcleanup_sysc_restore
1255 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1257 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1259 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1260 jl .Lcleanup_io_restore
1261 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1263 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1265 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1267 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1268 jl .Lcleanup_save_fpu_regs
1269 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1271 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1272 jl .Lcleanup_load_fpu_regs
1280 .quad .Lsysc_restore
1286 .quad .Lpsw_idle_end
1288 .quad .Lsave_fpu_regs_end
1290 .quad .Lload_fpu_regs_end
1292 #if IS_ENABLED(CONFIG_KVM)
1293 .Lcleanup_table_sie:
1298 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
1300 slg %r9,BASED(.Lsie_crit_mcck_start)
1301 clg %r9,BASED(.Lsie_crit_mcck_length)
1303 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
1304 1: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1305 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
1306 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1307 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1308 larl %r9,sie_exit # skip forward to sie_exit
1312 .Lcleanup_system_call:
1313 # check if stpt has been executed
1314 clg %r9,BASED(.Lcleanup_system_call_insn)
1316 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1317 cghi %r11,__LC_SAVE_AREA_ASYNC
1319 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1320 0: # check if stmg has been executed
1321 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1323 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1324 0: # check if base register setup + TIF bit load has been done
1325 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1327 # set up saved register r12 task struct pointer
1329 # set up saved register r13 __TASK_thread offset
1330 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
1331 0: # check if the user time update has been done
1332 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1334 lg %r15,__LC_EXIT_TIMER
1335 slg %r15,__LC_SYNC_ENTER_TIMER
1336 alg %r15,__LC_USER_TIMER
1337 stg %r15,__LC_USER_TIMER
1338 0: # check if the system time update has been done
1339 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1341 lg %r15,__LC_LAST_UPDATE_TIMER
1342 slg %r15,__LC_EXIT_TIMER
1343 alg %r15,__LC_SYSTEM_TIMER
1344 stg %r15,__LC_SYSTEM_TIMER
1345 0: # update accounting time stamp
1346 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1347 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1348 # set up saved register r11
1349 lg %r15,__LC_KERNEL_STACK
1350 la %r9,STACK_FRAME_OVERHEAD(%r15)
1351 stg %r9,24(%r11) # r11 pt_regs pointer
1353 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1354 stmg %r0,%r7,__PT_R0(%r9)
1355 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1356 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1357 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1358 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1359 # setup saved register r15
1360 stg %r15,56(%r11) # r15 stack pointer
1361 # set new psw address and exit
1362 larl %r9,.Lsysc_do_svc
1364 .Lcleanup_system_call_insn:
1368 .quad .Lsysc_vtime+36
1369 .quad .Lsysc_vtime+42
1370 .Lcleanup_system_call_const:
1377 .Lcleanup_sysc_restore:
1378 # check if stpt has been executed
1379 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1381 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1382 cghi %r11,__LC_SAVE_AREA_ASYNC
1384 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1385 0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1387 lg %r9,24(%r11) # get saved pointer to pt_regs
1388 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1389 mvc 0(64,%r11),__PT_R8(%r9)
1390 lmg %r0,%r7,__PT_R0(%r9)
1391 1: lmg %r8,%r9,__LC_RETURN_PSW
1393 .Lcleanup_sysc_restore_insn:
1394 .quad .Lsysc_exit_timer
1395 .quad .Lsysc_done - 4
1401 .Lcleanup_io_restore:
1402 # check if stpt has been executed
1403 clg %r9,BASED(.Lcleanup_io_restore_insn)
1405 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1406 0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1408 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1409 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1410 mvc 0(64,%r11),__PT_R8(%r9)
1411 lmg %r0,%r7,__PT_R0(%r9)
1412 1: lmg %r8,%r9,__LC_RETURN_PSW
1414 .Lcleanup_io_restore_insn:
1415 .quad .Lio_exit_timer
1419 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1420 # copy interrupt clock & cpu timer
1421 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1422 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1423 cghi %r11,__LC_SAVE_AREA_ASYNC
1425 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1426 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1427 0: # check if stck & stpt have been executed
1428 clg %r9,BASED(.Lcleanup_idle_insn)
1430 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1431 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1432 1: # calculate idle cycles
1434 clg %r9,BASED(.Lcleanup_idle_insn)
1436 larl %r1,smp_cpu_mtid
1440 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1442 ag %r3,__LC_PERCPU_OFFSET
1443 la %r4,__SF_EMPTY+16(%r15)
1452 3: # account system time going idle
1453 lg %r9,__LC_STEAL_TIMER
1454 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1455 slg %r9,__LC_LAST_UPDATE_CLOCK
1456 stg %r9,__LC_STEAL_TIMER
1457 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1458 lg %r9,__LC_SYSTEM_TIMER
1459 alg %r9,__LC_LAST_UPDATE_TIMER
1460 slg %r9,__TIMER_IDLE_ENTER(%r2)
1461 stg %r9,__LC_SYSTEM_TIMER
1462 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1463 # prepare return psw
1464 nihh %r8,0xfcfd # clear irq & wait state bits
1465 lg %r9,48(%r11) # return from psw_idle
1467 .Lcleanup_idle_insn:
1468 .quad .Lpsw_idle_lpsw
1470 .Lcleanup_save_fpu_regs:
1471 larl %r9,save_fpu_regs
1474 .Lcleanup_load_fpu_regs:
1475 larl %r9,load_fpu_regs
1483 .quad .L__critical_start
1485 .quad .L__critical_end - .L__critical_start
1486 #if IS_ENABLED(CONFIG_KVM)
1487 .Lsie_critical_start:
1489 .Lsie_critical_length:
1490 .quad .Lsie_done - .Lsie_gmap
1491 .Lsie_crit_mcck_start:
1493 .Lsie_crit_mcck_length:
1494 .quad .Lsie_skip - .Lsie_entry
1496 .section .rodata, "a"
1497 #define SYSCALL(esame,emu) .long esame
1498 .globl sys_call_table
1500 #include "asm/syscall_table.h"
1503 #ifdef CONFIG_COMPAT
1505 #define SYSCALL(esame,emu) .long emu
1506 .globl sys_call_table_emu
1508 #include "asm/syscall_table.h"