1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
9 * The Core code provides basic services for accessing and managing the
10 * DWC_otg hardware. These services are used by both the Host Controller
11 * Driver and the Peripheral Controller Driver.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/usb.h>
24 #include <linux/usb/hcd.h>
25 #include <linux/usb/ch11.h>
31 * dwc2_backup_global_registers() - Backup global controller registers.
32 * When suspending usb bus, registers needs to be backuped
33 * if controller power is disabled once suspended.
35 * @hsotg: Programming view of the DWC_otg controller
37 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
39 struct dwc2_gregs_backup *gr;
41 dev_dbg(hsotg->dev, "%s\n", __func__);
43 /* Backup global regs */
44 gr = &hsotg->gr_backup;
46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
49 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
50 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
51 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
52 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
53 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
54 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
55 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
56 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
63 * dwc2_restore_global_registers() - Restore controller global registers.
64 * When resuming usb bus, device registers needs to be restored
65 * if controller power were disabled.
67 * @hsotg: Programming view of the DWC_otg controller
69 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
71 struct dwc2_gregs_backup *gr;
73 dev_dbg(hsotg->dev, "%s\n", __func__);
75 /* Restore global regs */
76 gr = &hsotg->gr_backup;
78 dev_err(hsotg->dev, "%s: no global registers to restore\n",
84 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
85 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
86 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
87 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
88 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
89 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
90 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
91 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
92 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
93 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
94 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
95 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
101 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
103 * @hsotg: Programming view of the DWC_otg controller
104 * @rem_wakeup: indicates whether resume is initiated by Reset.
105 * @restore: Controller registers need to be restored
107 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
110 struct dwc2_gregs_backup *gr;
112 gr = &hsotg->gr_backup;
115 * Restore host or device regisers with the same mode core enterted
116 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
117 * value of the "gotgctl" register.
119 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
120 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
123 return dwc2_gadget_exit_partial_power_down(hsotg, restore);
127 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
129 * @hsotg: Programming view of the DWC_otg controller
131 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
133 if (dwc2_is_host_mode(hsotg))
134 return dwc2_host_enter_partial_power_down(hsotg);
136 return dwc2_gadget_enter_partial_power_down(hsotg);
140 * dwc2_restore_essential_regs() - Restore essiential regs of core.
142 * @hsotg: Programming view of the DWC_otg controller
143 * @rmode: Restore mode, enabled in case of remote-wakeup.
144 * @is_host: Host or device mode.
146 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
150 struct dwc2_gregs_backup *gr;
151 struct dwc2_dregs_backup *dr;
152 struct dwc2_hregs_backup *hr;
154 gr = &hsotg->gr_backup;
155 dr = &hsotg->dr_backup;
156 hr = &hsotg->hr_backup;
158 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
160 /* Load restore values for [31:14] bits */
161 pcgcctl = (gr->pcgcctl & 0xffffc000);
164 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
167 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
170 dwc2_writel(hsotg, pcgcctl, PCGCTL);
172 /* Umnask global Interrupt in GAHBCFG and restore it */
173 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
175 /* Clear all pending interupts */
176 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
178 /* Unmask restore done interrupt */
179 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
181 /* Restore GUSBCFG and HCFG/DCFG */
182 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
185 dwc2_writel(hsotg, hr->hcfg, HCFG);
187 pcgcctl |= PCGCTL_RESTOREMODE;
188 dwc2_writel(hsotg, pcgcctl, PCGCTL);
191 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
192 dwc2_writel(hsotg, pcgcctl, PCGCTL);
195 dwc2_writel(hsotg, dr->dcfg, DCFG);
197 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
198 dwc2_writel(hsotg, pcgcctl, PCGCTL);
201 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
202 dwc2_writel(hsotg, pcgcctl, PCGCTL);
208 * dwc2_hib_restore_common() - Common part of restore routine.
210 * @hsotg: Programming view of the DWC_otg controller
211 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
212 * @is_host: Host or device mode.
214 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
219 /* Switch-on voltage to the core */
220 gpwrdn = dwc2_readl(hsotg, GPWRDN);
221 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
222 dwc2_writel(hsotg, gpwrdn, GPWRDN);
226 gpwrdn = dwc2_readl(hsotg, GPWRDN);
227 gpwrdn &= ~GPWRDN_PWRDNRSTN;
228 dwc2_writel(hsotg, gpwrdn, GPWRDN);
231 /* Enable restore from PMU */
232 gpwrdn = dwc2_readl(hsotg, GPWRDN);
233 gpwrdn |= GPWRDN_RESTORE;
234 dwc2_writel(hsotg, gpwrdn, GPWRDN);
237 /* Disable Power Down Clamp */
238 gpwrdn = dwc2_readl(hsotg, GPWRDN);
239 gpwrdn &= ~GPWRDN_PWRDNCLMP;
240 dwc2_writel(hsotg, gpwrdn, GPWRDN);
243 if (!is_host && rem_wakeup)
246 /* Deassert reset core */
247 gpwrdn = dwc2_readl(hsotg, GPWRDN);
248 gpwrdn |= GPWRDN_PWRDNRSTN;
249 dwc2_writel(hsotg, gpwrdn, GPWRDN);
252 /* Disable PMU interrupt */
253 gpwrdn = dwc2_readl(hsotg, GPWRDN);
254 gpwrdn &= ~GPWRDN_PMUINTSEL;
255 dwc2_writel(hsotg, gpwrdn, GPWRDN);
258 /* Set Restore Essential Regs bit in PCGCCTL register */
259 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
262 * Wait For Restore_done Interrupt. This mechanism of polling the
263 * interrupt is introduced to avoid any possible race conditions
265 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
268 "%s: Restore Done wasn't generated here\n",
271 dev_dbg(hsotg->dev, "restore done generated here\n");
274 * To avoid restore done interrupt storm after restore is
275 * generated clear GINTSTS_RESTOREDONE bit.
277 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
282 * dwc2_wait_for_mode() - Waits for the controller mode.
283 * @hsotg: Programming view of the DWC_otg controller.
284 * @host_mode: If true, waits for host mode, otherwise device mode.
286 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
291 unsigned int timeout = 110;
293 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
294 host_mode ? "host" : "device");
301 if (dwc2_is_host_mode(hsotg) == host_mode) {
302 dev_vdbg(hsotg->dev, "%s mode set\n",
303 host_mode ? "Host" : "Device");
308 ms = ktime_to_ms(ktime_sub(end, start));
310 if (ms >= (s64)timeout) {
311 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
312 __func__, host_mode ? "host" : "device");
316 usleep_range(1000, 2000);
321 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
324 * @hsotg: Programming view of DWC_otg controller
326 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
331 if (!dwc2_hw_is_otg(hsotg))
334 /* Check if core configuration includes the IDDIG filter. */
335 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
336 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
340 * Check if the IDDIG debounce filter is bypassed. Available
341 * in core version >= 3.10a.
343 gsnpsid = dwc2_readl(hsotg, GSNPSID);
344 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
345 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
347 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
355 * dwc2_enter_hibernation() - Common function to enter hibernation.
357 * @hsotg: Programming view of the DWC_otg controller
358 * @is_host: True if core is in host mode.
360 * Return: 0 if successful, negative error code otherwise
362 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
365 return dwc2_host_enter_hibernation(hsotg);
367 return dwc2_gadget_enter_hibernation(hsotg);
371 * dwc2_exit_hibernation() - Common function to exit from hibernation.
373 * @hsotg: Programming view of the DWC_otg controller
374 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
375 * @reset: Enabled in case of restore with reset.
376 * @is_host: True if core is in host mode.
378 * Return: 0 if successful, negative error code otherwise
380 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
381 int reset, int is_host)
384 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
386 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
390 * Do core a soft reset of the core. Be careful with this because it
391 * resets all the internal state machines of the core.
393 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
396 bool wait_for_host_mode = false;
398 dev_vdbg(hsotg->dev, "%s()\n", __func__);
401 * If the current mode is host, either due to the force mode
402 * bit being set (which persists after core reset) or the
403 * connector id pin, a core soft reset will temporarily reset
404 * the mode to device. A delay from the IDDIG debounce filter
405 * will occur before going back to host mode.
407 * Determine whether we will go back into host mode after a
408 * reset and account for this delay after the reset.
410 if (dwc2_iddig_filter_enabled(hsotg)) {
411 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
412 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
414 if (!(gotgctl & GOTGCTL_CONID_B) ||
415 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
416 wait_for_host_mode = true;
420 /* Core Soft Reset */
421 greset = dwc2_readl(hsotg, GRSTCTL);
422 greset |= GRSTCTL_CSFTRST;
423 dwc2_writel(hsotg, greset, GRSTCTL);
425 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
426 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
427 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
428 GRSTCTL_CSFTRST, 10000)) {
429 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
434 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
435 GRSTCTL_CSFTRST_DONE, 10000)) {
436 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
440 greset = dwc2_readl(hsotg, GRSTCTL);
441 greset &= ~GRSTCTL_CSFTRST;
442 greset |= GRSTCTL_CSFTRST_DONE;
443 dwc2_writel(hsotg, greset, GRSTCTL);
447 * Switching from device mode to host mode by disconnecting
448 * device cable core enters and exits form hibernation.
449 * However, the fifo map remains not cleared. It results
450 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
451 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
452 * if in host mode we disconnect the micro a to b host
453 * cable. Because core reset occurs.
454 * To avoid the WARNING, fifo_map should be cleared
455 * in dwc2_core_reset() function by taking into account configs.
456 * fifo_map must be cleared only if driver is configured in
457 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
460 dwc2_clear_fifo_map(hsotg);
462 /* Wait for AHB master IDLE state */
463 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
464 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
469 if (wait_for_host_mode && !skip_wait)
470 dwc2_wait_for_mode(hsotg, true);
476 * dwc2_force_mode() - Force the mode of the controller.
478 * Forcing the mode is needed for two cases:
480 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
481 * controller to stay in a particular mode regardless of ID pin
482 * changes. We do this once during probe.
484 * 2) During probe we want to read reset values of the hw
485 * configuration registers that are only available in either host or
486 * device mode. We may need to force the mode if the current mode does
487 * not allow us to access the register in the mode that we want.
489 * In either case it only makes sense to force the mode if the
490 * controller hardware is OTG capable.
492 * Checks are done in this function to determine whether doing a force
493 * would be valid or not.
495 * If a force is done, it requires a IDDIG debounce filter delay if
496 * the filter is configured and enabled. We poll the current mode of
497 * the controller to account for this delay.
499 * @hsotg: Programming view of DWC_otg controller
500 * @host: Host mode flag
502 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
508 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
511 * Force mode has no effect if the hardware is not OTG.
513 if (!dwc2_hw_is_otg(hsotg))
517 * If dr_mode is either peripheral or host only, there is no
518 * need to ever force the mode to the opposite mode.
520 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
523 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
526 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
528 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
529 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
533 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
535 dwc2_wait_for_mode(hsotg, host);
540 * dwc2_clear_force_mode() - Clears the force mode bits.
542 * After clearing the bits, wait up to 100 ms to account for any
543 * potential IDDIG filter delay. We can't know if we expect this delay
544 * or not because the value of the connector ID status is affected by
545 * the force mode. We only need to call this once during probe if
548 * @hsotg: Programming view of DWC_otg controller
550 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
554 if (!dwc2_hw_is_otg(hsotg))
557 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
559 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
560 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
561 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
562 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
564 if (dwc2_iddig_filter_enabled(hsotg))
569 * Sets or clears force mode based on the dr_mode parameter.
571 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
573 switch (hsotg->dr_mode) {
574 case USB_DR_MODE_HOST:
576 * NOTE: This is required for some rockchip soc based
577 * platforms on their host-only dwc2.
579 if (!dwc2_hw_is_otg(hsotg))
583 case USB_DR_MODE_PERIPHERAL:
584 dwc2_force_mode(hsotg, false);
586 case USB_DR_MODE_OTG:
587 dwc2_clear_force_mode(hsotg);
590 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
591 __func__, hsotg->dr_mode);
597 * dwc2_enable_acg - enable active clock gating feature
599 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
601 if (hsotg->params.acg_enable) {
602 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
604 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
605 pcgcctl1 |= PCGCCTL1_GATEEN;
606 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
611 * dwc2_dump_host_registers() - Prints the host registers
613 * @hsotg: Programming view of DWC_otg controller
615 * NOTE: This function will be removed once the peripheral controller code
616 * is integrated and the driver is stable
618 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
624 dev_dbg(hsotg->dev, "Host Global Registers\n");
625 addr = hsotg->regs + HCFG;
626 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
627 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
628 addr = hsotg->regs + HFIR;
629 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
630 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
631 addr = hsotg->regs + HFNUM;
632 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
633 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
634 addr = hsotg->regs + HPTXSTS;
635 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
636 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
637 addr = hsotg->regs + HAINT;
638 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
639 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
640 addr = hsotg->regs + HAINTMSK;
641 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
642 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
643 if (hsotg->params.dma_desc_enable) {
644 addr = hsotg->regs + HFLBADDR;
645 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
646 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
649 addr = hsotg->regs + HPRT0;
650 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
651 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
653 for (i = 0; i < hsotg->params.host_channels; i++) {
654 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
655 addr = hsotg->regs + HCCHAR(i);
656 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
657 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
658 addr = hsotg->regs + HCSPLT(i);
659 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
660 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
661 addr = hsotg->regs + HCINT(i);
662 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
663 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
664 addr = hsotg->regs + HCINTMSK(i);
665 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
666 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
667 addr = hsotg->regs + HCTSIZ(i);
668 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
669 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
670 addr = hsotg->regs + HCDMA(i);
671 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
672 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
673 if (hsotg->params.dma_desc_enable) {
674 addr = hsotg->regs + HCDMAB(i);
675 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
676 (unsigned long)addr, dwc2_readl(hsotg,
684 * dwc2_dump_global_registers() - Prints the core global registers
686 * @hsotg: Programming view of DWC_otg controller
688 * NOTE: This function will be removed once the peripheral controller code
689 * is integrated and the driver is stable
691 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
696 dev_dbg(hsotg->dev, "Core Global Registers\n");
697 addr = hsotg->regs + GOTGCTL;
698 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
699 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
700 addr = hsotg->regs + GOTGINT;
701 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
702 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
703 addr = hsotg->regs + GAHBCFG;
704 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
705 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
706 addr = hsotg->regs + GUSBCFG;
707 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
708 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
709 addr = hsotg->regs + GRSTCTL;
710 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
711 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
712 addr = hsotg->regs + GINTSTS;
713 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
714 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
715 addr = hsotg->regs + GINTMSK;
716 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
717 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
718 addr = hsotg->regs + GRXSTSR;
719 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
720 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
721 addr = hsotg->regs + GRXFSIZ;
722 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
723 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
724 addr = hsotg->regs + GNPTXFSIZ;
725 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
726 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
727 addr = hsotg->regs + GNPTXSTS;
728 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
729 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
730 addr = hsotg->regs + GI2CCTL;
731 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
733 addr = hsotg->regs + GPVNDCTL;
734 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
735 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
736 addr = hsotg->regs + GGPIO;
737 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
738 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
739 addr = hsotg->regs + GUID;
740 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
741 (unsigned long)addr, dwc2_readl(hsotg, GUID));
742 addr = hsotg->regs + GSNPSID;
743 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
744 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
745 addr = hsotg->regs + GHWCFG1;
746 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
748 addr = hsotg->regs + GHWCFG2;
749 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
750 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
751 addr = hsotg->regs + GHWCFG3;
752 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
753 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
754 addr = hsotg->regs + GHWCFG4;
755 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
756 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
757 addr = hsotg->regs + GLPMCFG;
758 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
759 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
760 addr = hsotg->regs + GPWRDN;
761 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
763 addr = hsotg->regs + GDFIFOCFG;
764 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
765 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
766 addr = hsotg->regs + HPTXFSIZ;
767 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
768 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
770 addr = hsotg->regs + PCGCTL;
771 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
772 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
777 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
779 * @hsotg: Programming view of DWC_otg controller
780 * @num: Tx FIFO to flush
782 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
786 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
788 /* Wait for AHB master IDLE state */
789 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
790 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
793 greset = GRSTCTL_TXFFLSH;
794 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
795 dwc2_writel(hsotg, greset, GRSTCTL);
797 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
798 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
801 /* Wait for at least 3 PHY Clocks */
806 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
808 * @hsotg: Programming view of DWC_otg controller
810 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
814 dev_vdbg(hsotg->dev, "%s()\n", __func__);
816 /* Wait for AHB master IDLE state */
817 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
818 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
821 greset = GRSTCTL_RXFFLSH;
822 dwc2_writel(hsotg, greset, GRSTCTL);
824 /* Wait for RxFIFO flush done */
825 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
826 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
829 /* Wait for at least 3 PHY Clocks */
833 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
835 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
842 * dwc2_enable_global_interrupts() - Enables the controller's Global
843 * Interrupt in the AHB Config register
845 * @hsotg: Programming view of DWC_otg controller
847 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
849 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
851 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
852 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
856 * dwc2_disable_global_interrupts() - Disables the controller's Global
857 * Interrupt in the AHB Config register
859 * @hsotg: Programming view of DWC_otg controller
861 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
863 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
865 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
866 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
869 /* Returns the controller's GHWCFG2.OTG_MODE. */
870 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
872 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
874 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
875 GHWCFG2_OP_MODE_SHIFT;
878 /* Returns true if the controller is capable of DRD. */
879 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
881 unsigned int op_mode = dwc2_op_mode(hsotg);
883 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
884 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
885 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
888 /* Returns true if the controller is host-only. */
889 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
891 unsigned int op_mode = dwc2_op_mode(hsotg);
893 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
894 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
897 /* Returns true if the controller is device-only. */
898 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
900 unsigned int op_mode = dwc2_op_mode(hsotg);
902 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
903 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
907 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
908 * @hsotg: Programming view of DWC_otg controller.
909 * @offset: Register's offset where bit/bits must be set.
910 * @mask: Mask of the bit/bits which must be set.
911 * @timeout: Timeout to wait.
913 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
915 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
920 for (i = 0; i < timeout; i++) {
921 if (dwc2_readl(hsotg, offset) & mask)
930 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
931 * @hsotg: Programming view of DWC_otg controller.
932 * @offset: Register's offset where bit/bits must be set.
933 * @mask: Mask of the bit/bits which must be set.
934 * @timeout: Timeout to wait.
936 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
938 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
943 for (i = 0; i < timeout; i++) {
944 if (!(dwc2_readl(hsotg, offset) & mask))
953 * Initializes the FSLSPClkSel field of the HCFG register depending on the
956 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
960 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
961 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
962 hsotg->params.ulpi_fs_ls) ||
963 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
965 val = HCFG_FSLSPCLKSEL_48_MHZ;
967 /* High speed PHY running at full speed or high speed */
968 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
971 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
972 hcfg = dwc2_readl(hsotg, HCFG);
973 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
974 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
975 dwc2_writel(hsotg, hcfg, HCFG);
978 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
980 u32 usbcfg, ggpio, i2cctl;
984 * core_init() is now called on every switch so only call the
985 * following for the first time through
988 dev_dbg(hsotg->dev, "FS PHY selected\n");
990 usbcfg = dwc2_readl(hsotg, GUSBCFG);
991 if (!(usbcfg & GUSBCFG_PHYSEL)) {
992 usbcfg |= GUSBCFG_PHYSEL;
993 dwc2_writel(hsotg, usbcfg, GUSBCFG);
995 /* Reset after a PHY select */
996 retval = dwc2_core_reset(hsotg, false);
1000 "%s: Reset failed, aborting", __func__);
1005 if (hsotg->params.activate_stm_fs_transceiver) {
1006 ggpio = dwc2_readl(hsotg, GGPIO);
1007 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1008 dev_dbg(hsotg->dev, "Activating transceiver\n");
1010 * STM32F4x9 uses the GGPIO register as general
1011 * core configuration register.
1013 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1014 dwc2_writel(hsotg, ggpio, GGPIO);
1020 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1021 * do this on HNP Dev/Host mode switches (done in dev_init and
1024 if (dwc2_is_host_mode(hsotg))
1025 dwc2_init_fs_ls_pclk_sel(hsotg);
1027 if (hsotg->params.i2c_enable) {
1028 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1030 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1031 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1032 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1033 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1035 /* Program GI2CCTL.I2CEn */
1036 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1037 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1038 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1039 i2cctl &= ~GI2CCTL_I2CEN;
1040 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1041 i2cctl |= GI2CCTL_I2CEN;
1042 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1048 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1050 u32 usbcfg, usbcfg_old;
1056 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1057 usbcfg_old = usbcfg;
1060 * HS PHY parameters. These parameters are preserved during soft reset
1061 * so only program the first time. Do a soft reset immediately after
1064 switch (hsotg->params.phy_type) {
1065 case DWC2_PHY_TYPE_PARAM_ULPI:
1066 /* ULPI interface */
1067 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1068 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1069 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1070 if (hsotg->params.phy_ulpi_ddr)
1071 usbcfg |= GUSBCFG_DDRSEL;
1073 /* Set external VBUS indicator as needed. */
1074 if (hsotg->params.oc_disable)
1075 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1076 GUSBCFG_INDICATORPASSTHROUGH);
1078 case DWC2_PHY_TYPE_PARAM_UTMI:
1079 /* UTMI+ interface */
1080 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1081 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1082 if (hsotg->params.phy_utmi_width == 16)
1083 usbcfg |= GUSBCFG_PHYIF16;
1086 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1090 if (usbcfg != usbcfg_old) {
1091 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1093 /* Reset after setting the PHY parameters */
1094 retval = dwc2_core_reset(hsotg, false);
1097 "%s: Reset failed, aborting", __func__);
1105 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1109 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1112 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1114 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1115 if (hsotg->params.phy_utmi_width == 16)
1116 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1118 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1120 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1123 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1129 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1130 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1131 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1132 /* If FS/LS mode with FS/LS PHY */
1133 retval = dwc2_fs_phy_init(hsotg, select_phy);
1137 /* High speed PHY */
1138 retval = dwc2_hs_phy_init(hsotg, select_phy);
1142 if (dwc2_is_device_mode(hsotg))
1143 dwc2_set_turnaround_time(hsotg);
1146 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1147 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1148 hsotg->params.ulpi_fs_ls) {
1149 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1150 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1151 usbcfg |= GUSBCFG_ULPI_FS_LS;
1152 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1153 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1155 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1156 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1157 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1158 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1161 if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1162 if (dwc2_is_host_mode(hsotg)) {
1163 otgctl = readl(hsotg->regs + GOTGCTL);
1164 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1165 writel(otgctl, hsotg->regs + GOTGCTL);
1172 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1173 MODULE_AUTHOR("Synopsys, Inc.");
1174 MODULE_LICENSE("Dual BSD/GPL");