2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
29 #include <linux/dvb/frontend.h>
30 #include "dvb_frontend.h"
32 #include "stv6110x.h" /* for demodulator internal modes */
34 #include "stv090x_reg.h"
36 #include "stv090x_priv.h"
38 /* Max transfer size done by I2C transfer functions */
39 #define MAX_XFER_SIZE 64
41 static unsigned int verbose;
42 module_param(verbose, int, 0644);
44 /* internal params node */
46 /* pointer for internal params, one for each pair of demods */
47 struct stv090x_internal *internal;
48 struct stv090x_dev *next_dev;
51 /* first internal params */
52 static struct stv090x_dev *stv090x_first_dev;
54 /* find chip by i2c adapter and i2c address */
55 static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
58 struct stv090x_dev *temp_dev = stv090x_first_dev;
61 Search of the last stv0900 chip or
62 find it by i2c adapter and i2c address */
63 while ((temp_dev != NULL) &&
64 ((temp_dev->internal->i2c_adap != i2c_adap) ||
65 (temp_dev->internal->i2c_addr != i2c_addr))) {
67 temp_dev = temp_dev->next_dev;
73 /* deallocating chip */
74 static void remove_dev(struct stv090x_internal *internal)
76 struct stv090x_dev *prev_dev = stv090x_first_dev;
77 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
80 if (del_dev != NULL) {
81 if (del_dev == stv090x_first_dev) {
82 stv090x_first_dev = del_dev->next_dev;
84 while (prev_dev->next_dev != del_dev)
85 prev_dev = prev_dev->next_dev;
87 prev_dev->next_dev = del_dev->next_dev;
94 /* allocating new chip */
95 static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
97 struct stv090x_dev *new_dev;
98 struct stv090x_dev *temp_dev;
100 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
101 if (new_dev != NULL) {
102 new_dev->internal = internal;
103 new_dev->next_dev = NULL;
106 if (stv090x_first_dev == NULL) {
107 stv090x_first_dev = new_dev;
109 temp_dev = stv090x_first_dev;
110 while (temp_dev->next_dev != NULL)
111 temp_dev = temp_dev->next_dev;
113 temp_dev->next_dev = new_dev;
121 /* DVBS1 and DSS C/N Lookup table */
122 static const struct stv090x_tab stv090x_s1cn_tab[] = {
123 { 0, 8917 }, /* 0.0dB */
124 { 5, 8801 }, /* 0.5dB */
125 { 10, 8667 }, /* 1.0dB */
126 { 15, 8522 }, /* 1.5dB */
127 { 20, 8355 }, /* 2.0dB */
128 { 25, 8175 }, /* 2.5dB */
129 { 30, 7979 }, /* 3.0dB */
130 { 35, 7763 }, /* 3.5dB */
131 { 40, 7530 }, /* 4.0dB */
132 { 45, 7282 }, /* 4.5dB */
133 { 50, 7026 }, /* 5.0dB */
134 { 55, 6781 }, /* 5.5dB */
135 { 60, 6514 }, /* 6.0dB */
136 { 65, 6241 }, /* 6.5dB */
137 { 70, 5965 }, /* 7.0dB */
138 { 75, 5690 }, /* 7.5dB */
139 { 80, 5424 }, /* 8.0dB */
140 { 85, 5161 }, /* 8.5dB */
141 { 90, 4902 }, /* 9.0dB */
142 { 95, 4654 }, /* 9.5dB */
143 { 100, 4417 }, /* 10.0dB */
144 { 105, 4186 }, /* 10.5dB */
145 { 110, 3968 }, /* 11.0dB */
146 { 115, 3757 }, /* 11.5dB */
147 { 120, 3558 }, /* 12.0dB */
148 { 125, 3366 }, /* 12.5dB */
149 { 130, 3185 }, /* 13.0dB */
150 { 135, 3012 }, /* 13.5dB */
151 { 140, 2850 }, /* 14.0dB */
152 { 145, 2698 }, /* 14.5dB */
153 { 150, 2550 }, /* 15.0dB */
154 { 160, 2283 }, /* 16.0dB */
155 { 170, 2042 }, /* 17.0dB */
156 { 180, 1827 }, /* 18.0dB */
157 { 190, 1636 }, /* 19.0dB */
158 { 200, 1466 }, /* 20.0dB */
159 { 210, 1315 }, /* 21.0dB */
160 { 220, 1181 }, /* 22.0dB */
161 { 230, 1064 }, /* 23.0dB */
162 { 240, 960 }, /* 24.0dB */
163 { 250, 869 }, /* 25.0dB */
164 { 260, 792 }, /* 26.0dB */
165 { 270, 724 }, /* 27.0dB */
166 { 280, 665 }, /* 28.0dB */
167 { 290, 616 }, /* 29.0dB */
168 { 300, 573 }, /* 30.0dB */
169 { 310, 537 }, /* 31.0dB */
170 { 320, 507 }, /* 32.0dB */
171 { 330, 483 }, /* 33.0dB */
172 { 400, 398 }, /* 40.0dB */
173 { 450, 381 }, /* 45.0dB */
174 { 500, 377 } /* 50.0dB */
177 /* DVBS2 C/N Lookup table */
178 static const struct stv090x_tab stv090x_s2cn_tab[] = {
179 { -30, 13348 }, /* -3.0dB */
180 { -20, 12640 }, /* -2d.0B */
181 { -10, 11883 }, /* -1.0dB */
182 { 0, 11101 }, /* -0.0dB */
183 { 5, 10718 }, /* 0.5dB */
184 { 10, 10339 }, /* 1.0dB */
185 { 15, 9947 }, /* 1.5dB */
186 { 20, 9552 }, /* 2.0dB */
187 { 25, 9183 }, /* 2.5dB */
188 { 30, 8799 }, /* 3.0dB */
189 { 35, 8422 }, /* 3.5dB */
190 { 40, 8062 }, /* 4.0dB */
191 { 45, 7707 }, /* 4.5dB */
192 { 50, 7353 }, /* 5.0dB */
193 { 55, 7025 }, /* 5.5dB */
194 { 60, 6684 }, /* 6.0dB */
195 { 65, 6331 }, /* 6.5dB */
196 { 70, 6036 }, /* 7.0dB */
197 { 75, 5727 }, /* 7.5dB */
198 { 80, 5437 }, /* 8.0dB */
199 { 85, 5164 }, /* 8.5dB */
200 { 90, 4902 }, /* 9.0dB */
201 { 95, 4653 }, /* 9.5dB */
202 { 100, 4408 }, /* 10.0dB */
203 { 105, 4187 }, /* 10.5dB */
204 { 110, 3961 }, /* 11.0dB */
205 { 115, 3751 }, /* 11.5dB */
206 { 120, 3558 }, /* 12.0dB */
207 { 125, 3368 }, /* 12.5dB */
208 { 130, 3191 }, /* 13.0dB */
209 { 135, 3017 }, /* 13.5dB */
210 { 140, 2862 }, /* 14.0dB */
211 { 145, 2710 }, /* 14.5dB */
212 { 150, 2565 }, /* 15.0dB */
213 { 160, 2300 }, /* 16.0dB */
214 { 170, 2058 }, /* 17.0dB */
215 { 180, 1849 }, /* 18.0dB */
216 { 190, 1663 }, /* 19.0dB */
217 { 200, 1495 }, /* 20.0dB */
218 { 210, 1349 }, /* 21.0dB */
219 { 220, 1222 }, /* 22.0dB */
220 { 230, 1110 }, /* 23.0dB */
221 { 240, 1011 }, /* 24.0dB */
222 { 250, 925 }, /* 25.0dB */
223 { 260, 853 }, /* 26.0dB */
224 { 270, 789 }, /* 27.0dB */
225 { 280, 734 }, /* 28.0dB */
226 { 290, 690 }, /* 29.0dB */
227 { 300, 650 }, /* 30.0dB */
228 { 310, 619 }, /* 31.0dB */
229 { 320, 593 }, /* 32.0dB */
230 { 330, 571 }, /* 33.0dB */
231 { 400, 498 }, /* 40.0dB */
232 { 450, 484 }, /* 45.0dB */
233 { 500, 481 } /* 50.0dB */
236 /* RF level C/N lookup table */
237 static const struct stv090x_tab stv090x_rf_tab[] = {
238 { -5, 0xcaa1 }, /* -5dBm */
239 { -10, 0xc229 }, /* -10dBm */
240 { -15, 0xbb08 }, /* -15dBm */
241 { -20, 0xb4bc }, /* -20dBm */
242 { -25, 0xad5a }, /* -25dBm */
243 { -30, 0xa298 }, /* -30dBm */
244 { -35, 0x98a8 }, /* -35dBm */
245 { -40, 0x8389 }, /* -40dBm */
246 { -45, 0x59be }, /* -45dBm */
247 { -50, 0x3a14 }, /* -50dBm */
248 { -55, 0x2d11 }, /* -55dBm */
249 { -60, 0x210d }, /* -60dBm */
250 { -65, 0xa14f }, /* -65dBm */
251 { -70, 0x07aa } /* -70dBm */
255 static struct stv090x_reg stv0900_initval[] = {
257 { STV090x_OUTCFG, 0x00 },
258 { STV090x_MODECFG, 0xff },
259 { STV090x_AGCRF1CFG, 0x11 },
260 { STV090x_AGCRF2CFG, 0x13 },
261 { STV090x_TSGENERAL1X, 0x14 },
262 { STV090x_TSTTNR2, 0x21 },
263 { STV090x_TSTTNR4, 0x21 },
264 { STV090x_P2_DISTXCTL, 0x22 },
265 { STV090x_P2_F22TX, 0xc0 },
266 { STV090x_P2_F22RX, 0xc0 },
267 { STV090x_P2_DISRXCTL, 0x00 },
268 { STV090x_P2_DMDCFGMD, 0xF9 },
269 { STV090x_P2_DEMOD, 0x08 },
270 { STV090x_P2_DMDCFG3, 0xc4 },
271 { STV090x_P2_CARFREQ, 0xed },
272 { STV090x_P2_LDT, 0xd0 },
273 { STV090x_P2_LDT2, 0xb8 },
274 { STV090x_P2_TMGCFG, 0xd2 },
275 { STV090x_P2_TMGTHRISE, 0x20 },
276 { STV090x_P1_TMGCFG, 0xd2 },
278 { STV090x_P2_TMGTHFALL, 0x00 },
279 { STV090x_P2_FECSPY, 0x88 },
280 { STV090x_P2_FSPYDATA, 0x3a },
281 { STV090x_P2_FBERCPT4, 0x00 },
282 { STV090x_P2_FSPYBER, 0x10 },
283 { STV090x_P2_ERRCTRL1, 0x35 },
284 { STV090x_P2_ERRCTRL2, 0xc1 },
285 { STV090x_P2_CFRICFG, 0xf8 },
286 { STV090x_P2_NOSCFG, 0x1c },
287 { STV090x_P2_DMDTOM, 0x20 },
288 { STV090x_P2_CORRELMANT, 0x70 },
289 { STV090x_P2_CORRELABS, 0x88 },
290 { STV090x_P2_AGC2O, 0x5b },
291 { STV090x_P2_AGC2REF, 0x38 },
292 { STV090x_P2_CARCFG, 0xe4 },
293 { STV090x_P2_ACLC, 0x1A },
294 { STV090x_P2_BCLC, 0x09 },
295 { STV090x_P2_CARHDR, 0x08 },
296 { STV090x_P2_KREFTMG, 0xc1 },
297 { STV090x_P2_SFRUPRATIO, 0xf0 },
298 { STV090x_P2_SFRLOWRATIO, 0x70 },
299 { STV090x_P2_SFRSTEP, 0x58 },
300 { STV090x_P2_TMGCFG2, 0x01 },
301 { STV090x_P2_CAR2CFG, 0x26 },
302 { STV090x_P2_BCLC2S2Q, 0x86 },
303 { STV090x_P2_BCLC2S28, 0x86 },
304 { STV090x_P2_SMAPCOEF7, 0x77 },
305 { STV090x_P2_SMAPCOEF6, 0x85 },
306 { STV090x_P2_SMAPCOEF5, 0x77 },
307 { STV090x_P2_TSCFGL, 0x20 },
308 { STV090x_P2_DMDCFG2, 0x3b },
309 { STV090x_P2_MODCODLST0, 0xff },
310 { STV090x_P2_MODCODLST1, 0xff },
311 { STV090x_P2_MODCODLST2, 0xff },
312 { STV090x_P2_MODCODLST3, 0xff },
313 { STV090x_P2_MODCODLST4, 0xff },
314 { STV090x_P2_MODCODLST5, 0xff },
315 { STV090x_P2_MODCODLST6, 0xff },
316 { STV090x_P2_MODCODLST7, 0xcc },
317 { STV090x_P2_MODCODLST8, 0xcc },
318 { STV090x_P2_MODCODLST9, 0xcc },
319 { STV090x_P2_MODCODLSTA, 0xcc },
320 { STV090x_P2_MODCODLSTB, 0xcc },
321 { STV090x_P2_MODCODLSTC, 0xcc },
322 { STV090x_P2_MODCODLSTD, 0xcc },
323 { STV090x_P2_MODCODLSTE, 0xcc },
324 { STV090x_P2_MODCODLSTF, 0xcf },
325 { STV090x_P1_DISTXCTL, 0x22 },
326 { STV090x_P1_F22TX, 0xc0 },
327 { STV090x_P1_F22RX, 0xc0 },
328 { STV090x_P1_DISRXCTL, 0x00 },
329 { STV090x_P1_DMDCFGMD, 0xf9 },
330 { STV090x_P1_DEMOD, 0x08 },
331 { STV090x_P1_DMDCFG3, 0xc4 },
332 { STV090x_P1_DMDTOM, 0x20 },
333 { STV090x_P1_CARFREQ, 0xed },
334 { STV090x_P1_LDT, 0xd0 },
335 { STV090x_P1_LDT2, 0xb8 },
336 { STV090x_P1_TMGCFG, 0xd2 },
337 { STV090x_P1_TMGTHRISE, 0x20 },
338 { STV090x_P1_TMGTHFALL, 0x00 },
339 { STV090x_P1_SFRUPRATIO, 0xf0 },
340 { STV090x_P1_SFRLOWRATIO, 0x70 },
341 { STV090x_P1_TSCFGL, 0x20 },
342 { STV090x_P1_FECSPY, 0x88 },
343 { STV090x_P1_FSPYDATA, 0x3a },
344 { STV090x_P1_FBERCPT4, 0x00 },
345 { STV090x_P1_FSPYBER, 0x10 },
346 { STV090x_P1_ERRCTRL1, 0x35 },
347 { STV090x_P1_ERRCTRL2, 0xc1 },
348 { STV090x_P1_CFRICFG, 0xf8 },
349 { STV090x_P1_NOSCFG, 0x1c },
350 { STV090x_P1_CORRELMANT, 0x70 },
351 { STV090x_P1_CORRELABS, 0x88 },
352 { STV090x_P1_AGC2O, 0x5b },
353 { STV090x_P1_AGC2REF, 0x38 },
354 { STV090x_P1_CARCFG, 0xe4 },
355 { STV090x_P1_ACLC, 0x1A },
356 { STV090x_P1_BCLC, 0x09 },
357 { STV090x_P1_CARHDR, 0x08 },
358 { STV090x_P1_KREFTMG, 0xc1 },
359 { STV090x_P1_SFRSTEP, 0x58 },
360 { STV090x_P1_TMGCFG2, 0x01 },
361 { STV090x_P1_CAR2CFG, 0x26 },
362 { STV090x_P1_BCLC2S2Q, 0x86 },
363 { STV090x_P1_BCLC2S28, 0x86 },
364 { STV090x_P1_SMAPCOEF7, 0x77 },
365 { STV090x_P1_SMAPCOEF6, 0x85 },
366 { STV090x_P1_SMAPCOEF5, 0x77 },
367 { STV090x_P1_DMDCFG2, 0x3b },
368 { STV090x_P1_MODCODLST0, 0xff },
369 { STV090x_P1_MODCODLST1, 0xff },
370 { STV090x_P1_MODCODLST2, 0xff },
371 { STV090x_P1_MODCODLST3, 0xff },
372 { STV090x_P1_MODCODLST4, 0xff },
373 { STV090x_P1_MODCODLST5, 0xff },
374 { STV090x_P1_MODCODLST6, 0xff },
375 { STV090x_P1_MODCODLST7, 0xcc },
376 { STV090x_P1_MODCODLST8, 0xcc },
377 { STV090x_P1_MODCODLST9, 0xcc },
378 { STV090x_P1_MODCODLSTA, 0xcc },
379 { STV090x_P1_MODCODLSTB, 0xcc },
380 { STV090x_P1_MODCODLSTC, 0xcc },
381 { STV090x_P1_MODCODLSTD, 0xcc },
382 { STV090x_P1_MODCODLSTE, 0xcc },
383 { STV090x_P1_MODCODLSTF, 0xcf },
384 { STV090x_GENCFG, 0x1d },
385 { STV090x_NBITER_NF4, 0x37 },
386 { STV090x_NBITER_NF5, 0x29 },
387 { STV090x_NBITER_NF6, 0x37 },
388 { STV090x_NBITER_NF7, 0x33 },
389 { STV090x_NBITER_NF8, 0x31 },
390 { STV090x_NBITER_NF9, 0x2f },
391 { STV090x_NBITER_NF10, 0x39 },
392 { STV090x_NBITER_NF11, 0x3a },
393 { STV090x_NBITER_NF12, 0x29 },
394 { STV090x_NBITER_NF13, 0x37 },
395 { STV090x_NBITER_NF14, 0x33 },
396 { STV090x_NBITER_NF15, 0x2f },
397 { STV090x_NBITER_NF16, 0x39 },
398 { STV090x_NBITER_NF17, 0x3a },
399 { STV090x_NBITERNOERR, 0x04 },
400 { STV090x_GAINLLR_NF4, 0x0C },
401 { STV090x_GAINLLR_NF5, 0x0F },
402 { STV090x_GAINLLR_NF6, 0x11 },
403 { STV090x_GAINLLR_NF7, 0x14 },
404 { STV090x_GAINLLR_NF8, 0x17 },
405 { STV090x_GAINLLR_NF9, 0x19 },
406 { STV090x_GAINLLR_NF10, 0x20 },
407 { STV090x_GAINLLR_NF11, 0x21 },
408 { STV090x_GAINLLR_NF12, 0x0D },
409 { STV090x_GAINLLR_NF13, 0x0F },
410 { STV090x_GAINLLR_NF14, 0x13 },
411 { STV090x_GAINLLR_NF15, 0x1A },
412 { STV090x_GAINLLR_NF16, 0x1F },
413 { STV090x_GAINLLR_NF17, 0x21 },
414 { STV090x_RCCFGH, 0x20 },
415 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
416 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
417 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
418 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
421 static struct stv090x_reg stv0903_initval[] = {
422 { STV090x_OUTCFG, 0x00 },
423 { STV090x_AGCRF1CFG, 0x11 },
424 { STV090x_STOPCLK1, 0x48 },
425 { STV090x_STOPCLK2, 0x14 },
426 { STV090x_TSTTNR1, 0x27 },
427 { STV090x_TSTTNR2, 0x21 },
428 { STV090x_P1_DISTXCTL, 0x22 },
429 { STV090x_P1_F22TX, 0xc0 },
430 { STV090x_P1_F22RX, 0xc0 },
431 { STV090x_P1_DISRXCTL, 0x00 },
432 { STV090x_P1_DMDCFGMD, 0xF9 },
433 { STV090x_P1_DEMOD, 0x08 },
434 { STV090x_P1_DMDCFG3, 0xc4 },
435 { STV090x_P1_CARFREQ, 0xed },
436 { STV090x_P1_TNRCFG2, 0x82 },
437 { STV090x_P1_LDT, 0xd0 },
438 { STV090x_P1_LDT2, 0xb8 },
439 { STV090x_P1_TMGCFG, 0xd2 },
440 { STV090x_P1_TMGTHRISE, 0x20 },
441 { STV090x_P1_TMGTHFALL, 0x00 },
442 { STV090x_P1_SFRUPRATIO, 0xf0 },
443 { STV090x_P1_SFRLOWRATIO, 0x70 },
444 { STV090x_P1_TSCFGL, 0x20 },
445 { STV090x_P1_FECSPY, 0x88 },
446 { STV090x_P1_FSPYDATA, 0x3a },
447 { STV090x_P1_FBERCPT4, 0x00 },
448 { STV090x_P1_FSPYBER, 0x10 },
449 { STV090x_P1_ERRCTRL1, 0x35 },
450 { STV090x_P1_ERRCTRL2, 0xc1 },
451 { STV090x_P1_CFRICFG, 0xf8 },
452 { STV090x_P1_NOSCFG, 0x1c },
453 { STV090x_P1_DMDTOM, 0x20 },
454 { STV090x_P1_CORRELMANT, 0x70 },
455 { STV090x_P1_CORRELABS, 0x88 },
456 { STV090x_P1_AGC2O, 0x5b },
457 { STV090x_P1_AGC2REF, 0x38 },
458 { STV090x_P1_CARCFG, 0xe4 },
459 { STV090x_P1_ACLC, 0x1A },
460 { STV090x_P1_BCLC, 0x09 },
461 { STV090x_P1_CARHDR, 0x08 },
462 { STV090x_P1_KREFTMG, 0xc1 },
463 { STV090x_P1_SFRSTEP, 0x58 },
464 { STV090x_P1_TMGCFG2, 0x01 },
465 { STV090x_P1_CAR2CFG, 0x26 },
466 { STV090x_P1_BCLC2S2Q, 0x86 },
467 { STV090x_P1_BCLC2S28, 0x86 },
468 { STV090x_P1_SMAPCOEF7, 0x77 },
469 { STV090x_P1_SMAPCOEF6, 0x85 },
470 { STV090x_P1_SMAPCOEF5, 0x77 },
471 { STV090x_P1_DMDCFG2, 0x3b },
472 { STV090x_P1_MODCODLST0, 0xff },
473 { STV090x_P1_MODCODLST1, 0xff },
474 { STV090x_P1_MODCODLST2, 0xff },
475 { STV090x_P1_MODCODLST3, 0xff },
476 { STV090x_P1_MODCODLST4, 0xff },
477 { STV090x_P1_MODCODLST5, 0xff },
478 { STV090x_P1_MODCODLST6, 0xff },
479 { STV090x_P1_MODCODLST7, 0xcc },
480 { STV090x_P1_MODCODLST8, 0xcc },
481 { STV090x_P1_MODCODLST9, 0xcc },
482 { STV090x_P1_MODCODLSTA, 0xcc },
483 { STV090x_P1_MODCODLSTB, 0xcc },
484 { STV090x_P1_MODCODLSTC, 0xcc },
485 { STV090x_P1_MODCODLSTD, 0xcc },
486 { STV090x_P1_MODCODLSTE, 0xcc },
487 { STV090x_P1_MODCODLSTF, 0xcf },
488 { STV090x_GENCFG, 0x1c },
489 { STV090x_NBITER_NF4, 0x37 },
490 { STV090x_NBITER_NF5, 0x29 },
491 { STV090x_NBITER_NF6, 0x37 },
492 { STV090x_NBITER_NF7, 0x33 },
493 { STV090x_NBITER_NF8, 0x31 },
494 { STV090x_NBITER_NF9, 0x2f },
495 { STV090x_NBITER_NF10, 0x39 },
496 { STV090x_NBITER_NF11, 0x3a },
497 { STV090x_NBITER_NF12, 0x29 },
498 { STV090x_NBITER_NF13, 0x37 },
499 { STV090x_NBITER_NF14, 0x33 },
500 { STV090x_NBITER_NF15, 0x2f },
501 { STV090x_NBITER_NF16, 0x39 },
502 { STV090x_NBITER_NF17, 0x3a },
503 { STV090x_NBITERNOERR, 0x04 },
504 { STV090x_GAINLLR_NF4, 0x0C },
505 { STV090x_GAINLLR_NF5, 0x0F },
506 { STV090x_GAINLLR_NF6, 0x11 },
507 { STV090x_GAINLLR_NF7, 0x14 },
508 { STV090x_GAINLLR_NF8, 0x17 },
509 { STV090x_GAINLLR_NF9, 0x19 },
510 { STV090x_GAINLLR_NF10, 0x20 },
511 { STV090x_GAINLLR_NF11, 0x21 },
512 { STV090x_GAINLLR_NF12, 0x0D },
513 { STV090x_GAINLLR_NF13, 0x0F },
514 { STV090x_GAINLLR_NF14, 0x13 },
515 { STV090x_GAINLLR_NF15, 0x1A },
516 { STV090x_GAINLLR_NF16, 0x1F },
517 { STV090x_GAINLLR_NF17, 0x21 },
518 { STV090x_RCCFGH, 0x20 },
519 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
520 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
523 static struct stv090x_reg stv0900_cut20_val[] = {
525 { STV090x_P2_DMDCFG3, 0xe8 },
526 { STV090x_P2_DMDCFG4, 0x10 },
527 { STV090x_P2_CARFREQ, 0x38 },
528 { STV090x_P2_CARHDR, 0x20 },
529 { STV090x_P2_KREFTMG, 0x5a },
530 { STV090x_P2_SMAPCOEF7, 0x06 },
531 { STV090x_P2_SMAPCOEF6, 0x00 },
532 { STV090x_P2_SMAPCOEF5, 0x04 },
533 { STV090x_P2_NOSCFG, 0x0c },
534 { STV090x_P1_DMDCFG3, 0xe8 },
535 { STV090x_P1_DMDCFG4, 0x10 },
536 { STV090x_P1_CARFREQ, 0x38 },
537 { STV090x_P1_CARHDR, 0x20 },
538 { STV090x_P1_KREFTMG, 0x5a },
539 { STV090x_P1_SMAPCOEF7, 0x06 },
540 { STV090x_P1_SMAPCOEF6, 0x00 },
541 { STV090x_P1_SMAPCOEF5, 0x04 },
542 { STV090x_P1_NOSCFG, 0x0c },
543 { STV090x_GAINLLR_NF4, 0x21 },
544 { STV090x_GAINLLR_NF5, 0x21 },
545 { STV090x_GAINLLR_NF6, 0x20 },
546 { STV090x_GAINLLR_NF7, 0x1F },
547 { STV090x_GAINLLR_NF8, 0x1E },
548 { STV090x_GAINLLR_NF9, 0x1E },
549 { STV090x_GAINLLR_NF10, 0x1D },
550 { STV090x_GAINLLR_NF11, 0x1B },
551 { STV090x_GAINLLR_NF12, 0x20 },
552 { STV090x_GAINLLR_NF13, 0x20 },
553 { STV090x_GAINLLR_NF14, 0x20 },
554 { STV090x_GAINLLR_NF15, 0x20 },
555 { STV090x_GAINLLR_NF16, 0x20 },
556 { STV090x_GAINLLR_NF17, 0x21 },
559 static struct stv090x_reg stv0903_cut20_val[] = {
560 { STV090x_P1_DMDCFG3, 0xe8 },
561 { STV090x_P1_DMDCFG4, 0x10 },
562 { STV090x_P1_CARFREQ, 0x38 },
563 { STV090x_P1_CARHDR, 0x20 },
564 { STV090x_P1_KREFTMG, 0x5a },
565 { STV090x_P1_SMAPCOEF7, 0x06 },
566 { STV090x_P1_SMAPCOEF6, 0x00 },
567 { STV090x_P1_SMAPCOEF5, 0x04 },
568 { STV090x_P1_NOSCFG, 0x0c },
569 { STV090x_GAINLLR_NF4, 0x21 },
570 { STV090x_GAINLLR_NF5, 0x21 },
571 { STV090x_GAINLLR_NF6, 0x20 },
572 { STV090x_GAINLLR_NF7, 0x1F },
573 { STV090x_GAINLLR_NF8, 0x1E },
574 { STV090x_GAINLLR_NF9, 0x1E },
575 { STV090x_GAINLLR_NF10, 0x1D },
576 { STV090x_GAINLLR_NF11, 0x1B },
577 { STV090x_GAINLLR_NF12, 0x20 },
578 { STV090x_GAINLLR_NF13, 0x20 },
579 { STV090x_GAINLLR_NF14, 0x20 },
580 { STV090x_GAINLLR_NF15, 0x20 },
581 { STV090x_GAINLLR_NF16, 0x20 },
582 { STV090x_GAINLLR_NF17, 0x21 }
585 /* Cut 2.0 Long Frame Tracking CR loop */
586 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
587 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
588 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
589 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
590 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
593 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
594 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
595 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
596 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
597 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
598 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
599 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
600 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
601 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
604 /* Cut 3.0 Long Frame Tracking CR loop */
605 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
606 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
607 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
608 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
609 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
610 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
611 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
612 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
613 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
614 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
615 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
616 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
617 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
618 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
619 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
620 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
623 /* Cut 2.0 Long Frame Tracking CR Loop */
624 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
625 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
626 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
627 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
628 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
629 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
630 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
631 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
632 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
633 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
634 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
635 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
636 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
639 /* Cut 3.0 Long Frame Tracking CR Loop */
640 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
641 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
642 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
643 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
644 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
645 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
646 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
647 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
648 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
649 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
650 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
651 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
652 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
655 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
656 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
657 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
658 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
659 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
662 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
663 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
664 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
665 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
666 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
669 /* Cut 2.0 Short Frame Tracking CR Loop */
670 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
671 /* MODCOD 2M 5M 10M 20M 30M */
672 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
673 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
674 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
675 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
678 /* Cut 3.0 Short Frame Tracking CR Loop */
679 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
680 /* MODCOD 2M 5M 10M 20M 30M */
681 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
682 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
683 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
684 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
687 static inline s32 comp2(s32 __x, s32 __width)
692 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
695 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
697 const struct stv090x_config *config = state->config;
700 u8 b0[] = { reg >> 8, reg & 0xff };
703 struct i2c_msg msg[] = {
704 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
705 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
708 ret = i2c_transfer(state->i2c, msg, 2);
710 if (ret != -ERESTARTSYS)
712 "Read error, Reg=[0x%02x], Status=%d",
715 return ret < 0 ? ret : -EREMOTEIO;
717 if (unlikely(*state->verbose >= FE_DEBUGREG))
718 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
721 return (unsigned int) buf;
724 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
726 const struct stv090x_config *config = state->config;
728 u8 buf[MAX_XFER_SIZE];
729 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
731 if (2 + count > sizeof(buf)) {
733 "%s: i2c wr reg=%04x: len=%d is too big!\n",
734 KBUILD_MODNAME, reg, count);
740 memcpy(&buf[2], data, count);
742 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
745 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
746 for (i = 0; i < count; i++)
747 printk(" %02x", data[i]);
751 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
753 if (ret != -ERESTARTSYS)
754 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
755 reg, data[0], count, ret);
756 return ret < 0 ? ret : -EREMOTEIO;
762 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
764 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
766 return stv090x_write_regs(state, reg, &tmp, 1);
769 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
774 * NOTE! A lock is used as a FSM to control the state in which
775 * access is serialized between two tuners on the same demod.
776 * This has nothing to do with a lock to protect a critical section
777 * which may in some other cases be confused with protecting I/O
778 * access to the demodulator gate.
779 * In case of any error, the lock is unlocked and exit within the
780 * relevant operations themselves.
783 if (state->config->tuner_i2c_lock)
784 state->config->tuner_i2c_lock(&state->frontend, 1);
786 mutex_lock(&state->internal->tuner_lock);
789 reg = STV090x_READ_DEMOD(state, I2CRPT);
791 dprintk(FE_DEBUG, 1, "Enable Gate");
792 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
793 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
797 dprintk(FE_DEBUG, 1, "Disable Gate");
798 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
799 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
804 if (state->config->tuner_i2c_lock)
805 state->config->tuner_i2c_lock(&state->frontend, 0);
807 mutex_unlock(&state->internal->tuner_lock);
812 dprintk(FE_ERROR, 1, "I/O error");
813 if (state->config->tuner_i2c_lock)
814 state->config->tuner_i2c_lock(&state->frontend, 0);
816 mutex_unlock(&state->internal->tuner_lock);
820 static void stv090x_get_lock_tmg(struct stv090x_state *state)
822 switch (state->algo) {
823 case STV090x_BLIND_SEARCH:
824 dprintk(FE_DEBUG, 1, "Blind Search");
825 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
826 state->DemodTimeout = 1500;
827 state->FecTimeout = 400;
828 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
829 state->DemodTimeout = 1000;
830 state->FecTimeout = 300;
831 } else { /*SR >20Msps*/
832 state->DemodTimeout = 700;
833 state->FecTimeout = 100;
837 case STV090x_COLD_SEARCH:
838 case STV090x_WARM_SEARCH:
840 dprintk(FE_DEBUG, 1, "Normal Search");
841 if (state->srate <= 1000000) { /*SR <=1Msps*/
842 state->DemodTimeout = 4500;
843 state->FecTimeout = 1700;
844 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
845 state->DemodTimeout = 2500;
846 state->FecTimeout = 1100;
847 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
848 state->DemodTimeout = 1000;
849 state->FecTimeout = 550;
850 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
851 state->DemodTimeout = 700;
852 state->FecTimeout = 250;
853 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
854 state->DemodTimeout = 400;
855 state->FecTimeout = 130;
856 } else { /*SR >20Msps*/
857 state->DemodTimeout = 300;
858 state->FecTimeout = 100;
863 if (state->algo == STV090x_WARM_SEARCH)
864 state->DemodTimeout /= 2;
867 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
871 if (srate > 60000000) {
872 sym = (srate << 4); /* SR * 2^16 / master_clk */
873 sym /= (state->internal->mclk >> 12);
874 } else if (srate > 6000000) {
876 sym /= (state->internal->mclk >> 10);
879 sym /= (state->internal->mclk >> 7);
882 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
884 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
889 dprintk(FE_ERROR, 1, "I/O error");
893 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
897 srate = 105 * (srate / 100);
898 if (srate > 60000000) {
899 sym = (srate << 4); /* SR * 2^16 / master_clk */
900 sym /= (state->internal->mclk >> 12);
901 } else if (srate > 6000000) {
903 sym /= (state->internal->mclk >> 10);
906 sym /= (state->internal->mclk >> 7);
910 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
912 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
915 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
917 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
923 dprintk(FE_ERROR, 1, "I/O error");
927 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
931 srate = 95 * (srate / 100);
932 if (srate > 60000000) {
933 sym = (srate << 4); /* SR * 2^16 / master_clk */
934 sym /= (state->internal->mclk >> 12);
935 } else if (srate > 6000000) {
937 sym /= (state->internal->mclk >> 10);
940 sym /= (state->internal->mclk >> 7);
943 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
945 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
949 dprintk(FE_ERROR, 1, "I/O error");
953 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
970 return srate + (srate * ro) / 100;
973 static int stv090x_set_vit_thacq(struct stv090x_state *state)
975 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
977 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
979 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
981 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
983 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
985 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
989 dprintk(FE_ERROR, 1, "I/O error");
993 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
995 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
997 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
999 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
1001 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
1003 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
1005 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
1009 dprintk(FE_ERROR, 1, "I/O error");
1013 static int stv090x_set_viterbi(struct stv090x_state *state)
1015 switch (state->search_mode) {
1016 case STV090x_SEARCH_AUTO:
1017 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
1019 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
1022 case STV090x_SEARCH_DVBS1:
1023 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
1025 switch (state->fec) {
1027 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1032 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1037 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1042 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1047 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1052 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1057 case STV090x_SEARCH_DSS:
1058 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1060 switch (state->fec) {
1062 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1067 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1072 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1077 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1087 dprintk(FE_ERROR, 1, "I/O error");
1091 static int stv090x_stop_modcod(struct stv090x_state *state)
1093 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1095 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1097 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1099 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1101 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1111 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1117 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1119 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1123 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1127 dprintk(FE_ERROR, 1, "I/O error");
1131 static int stv090x_activate_modcod(struct stv090x_state *state)
1133 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1135 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1137 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1139 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1141 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1151 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1157 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1159 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1161 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1163 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1168 dprintk(FE_ERROR, 1, "I/O error");
1172 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1175 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1177 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1179 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1181 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1183 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1185 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1187 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1189 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1191 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1193 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1199 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1201 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1203 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1205 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1211 dprintk(FE_ERROR, 1, "I/O error");
1215 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1219 switch (state->demod) {
1220 case STV090x_DEMODULATOR_0:
1221 mutex_lock(&state->internal->demod_lock);
1222 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1223 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1224 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1226 mutex_unlock(&state->internal->demod_lock);
1229 case STV090x_DEMODULATOR_1:
1230 mutex_lock(&state->internal->demod_lock);
1231 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1232 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1233 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1235 mutex_unlock(&state->internal->demod_lock);
1239 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1244 mutex_unlock(&state->internal->demod_lock);
1245 dprintk(FE_ERROR, 1, "I/O error");
1249 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1251 if (state->internal->dev_ver >= 0x30) {
1252 /* Set ACLC BCLC optimised value vs SR */
1253 if (state->srate >= 15000000) {
1254 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1256 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1258 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1259 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1261 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1263 } else if (state->srate < 7000000) {
1264 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1266 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1272 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1274 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1279 dprintk(FE_ERROR, 1, "I/O error");
1283 static int stv090x_delivery_search(struct stv090x_state *state)
1287 switch (state->search_mode) {
1288 case STV090x_SEARCH_DVBS1:
1289 case STV090x_SEARCH_DSS:
1290 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1291 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1292 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1293 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1296 /* Activate Viterbi decoder in legacy search,
1297 * do not use FRESVIT1, might impact VITERBI2
1299 if (stv090x_vitclk_ctl(state, 0) < 0)
1302 if (stv090x_dvbs_track_crl(state) < 0)
1305 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1308 if (stv090x_set_vit_thacq(state) < 0)
1310 if (stv090x_set_viterbi(state) < 0)
1314 case STV090x_SEARCH_DVBS2:
1315 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1316 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1317 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1318 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1320 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1321 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1322 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1325 if (stv090x_vitclk_ctl(state, 1) < 0)
1328 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1330 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1333 if (state->internal->dev_ver <= 0x20) {
1334 /* enable S2 carrier loop */
1335 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1338 /* > Cut 3: Stop carrier 3 */
1339 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1343 if (state->demod_mode != STV090x_SINGLE) {
1344 /* Cut 2: enable link during search */
1345 if (stv090x_activate_modcod(state) < 0)
1348 /* Single demodulator
1349 * Authorize SHORT and LONG frames,
1350 * QPSK, 8PSK, 16APSK and 32APSK
1352 if (stv090x_activate_modcod_single(state) < 0)
1356 if (stv090x_set_vit_thtracq(state) < 0)
1360 case STV090x_SEARCH_AUTO:
1362 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1363 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1364 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1365 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1366 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1368 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1369 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1370 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1373 if (stv090x_vitclk_ctl(state, 0) < 0)
1376 if (stv090x_dvbs_track_crl(state) < 0)
1379 if (state->internal->dev_ver <= 0x20) {
1380 /* enable S2 carrier loop */
1381 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1384 /* > Cut 3: Stop carrier 3 */
1385 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1389 if (state->demod_mode != STV090x_SINGLE) {
1390 /* Cut 2: enable link during search */
1391 if (stv090x_activate_modcod(state) < 0)
1394 /* Single demodulator
1395 * Authorize SHORT and LONG frames,
1396 * QPSK, 8PSK, 16APSK and 32APSK
1398 if (stv090x_activate_modcod_single(state) < 0)
1402 if (stv090x_set_vit_thacq(state) < 0)
1405 if (stv090x_set_viterbi(state) < 0)
1411 dprintk(FE_ERROR, 1, "I/O error");
1415 static int stv090x_start_search(struct stv090x_state *state)
1420 /* Reset demodulator */
1421 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1422 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1423 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1426 if (state->internal->dev_ver <= 0x20) {
1427 if (state->srate <= 5000000) {
1428 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1430 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1432 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1434 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1436 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1439 /*enlarge the timing bandwidth for Low SR*/
1440 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1443 /* If the symbol rate is >5 Msps
1444 Set The carrier search up and low to auto mode */
1445 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1447 /*reduce the timing bandwidth for high SR*/
1448 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1453 if (state->srate <= 5000000) {
1454 /* enlarge the timing bandwidth for Low SR */
1455 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1457 /* reduce timing bandwidth for high SR */
1458 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1461 /* Set CFR min and max to manual mode */
1462 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1464 if (state->algo == STV090x_WARM_SEARCH) {
1469 freq_abs = 1000 << 16;
1470 freq_abs /= (state->internal->mclk / 1000);
1471 freq = (s16) freq_abs;
1474 * CFR min =- (SearchRange / 2 + 600KHz)
1475 * CFR max = +(SearchRange / 2 + 600KHz)
1476 * (600KHz for the tuner step size)
1478 freq_abs = (state->search_range / 2000) + 600;
1479 freq_abs = freq_abs << 16;
1480 freq_abs /= (state->internal->mclk / 1000);
1481 freq = (s16) freq_abs;
1484 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1486 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1491 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1493 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1498 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1500 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1503 if (state->internal->dev_ver >= 0x20) {
1504 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1506 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1509 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
1510 (state->search_mode == STV090x_SEARCH_DSS) ||
1511 (state->search_mode == STV090x_SEARCH_AUTO)) {
1513 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1515 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1520 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1522 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1524 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1527 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1528 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1529 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1530 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1532 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1533 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1534 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1537 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1540 if (state->internal->dev_ver >= 0x20) {
1541 /*Frequency offset detector setting*/
1542 if (state->srate < 2000000) {
1543 if (state->internal->dev_ver <= 0x20) {
1545 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1549 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1552 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1554 } else if (state->srate < 10000000) {
1555 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1557 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1560 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1562 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1566 if (state->srate < 10000000) {
1567 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1570 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1575 switch (state->algo) {
1576 case STV090x_WARM_SEARCH:
1577 /* The symbol rate and the exact
1578 * carrier Frequency are known
1580 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1582 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1586 case STV090x_COLD_SEARCH:
1587 /* The symbol rate is known */
1588 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1590 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1599 dprintk(FE_ERROR, 1, "I/O error");
1603 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1605 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1606 s32 i, j, steps, dir;
1608 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1610 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1611 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1612 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1613 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1616 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1618 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1620 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1622 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1624 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1626 if (stv090x_set_srate(state, 1000000) < 0)
1629 steps = state->search_range / 1000000;
1634 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1637 for (i = 0; i < steps; i++) {
1639 freq_init = freq_init + (freq_step * i);
1641 freq_init = freq_init - (freq_step * i);
1645 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1647 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1649 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1651 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1656 for (j = 0; j < 10; j++) {
1657 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1658 STV090x_READ_DEMOD(state, AGC2I0);
1661 if (agc2 < agc2_min)
1667 dprintk(FE_ERROR, 1, "I/O error");
1671 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1674 s32 srate, int_1, int_2, tmp_1, tmp_2;
1676 r3 = STV090x_READ_DEMOD(state, SFR3);
1677 r2 = STV090x_READ_DEMOD(state, SFR2);
1678 r1 = STV090x_READ_DEMOD(state, SFR1);
1679 r0 = STV090x_READ_DEMOD(state, SFR0);
1681 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1684 int_2 = srate >> 16;
1686 tmp_1 = clk % 0x10000;
1687 tmp_2 = srate % 0x10000;
1689 srate = (int_1 * int_2) +
1690 ((int_1 * tmp_2) >> 16) +
1691 ((int_2 * tmp_1) >> 16);
1696 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1698 struct dvb_frontend *fe = &state->frontend;
1700 int tmg_lock = 0, i;
1701 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1702 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1705 if (state->internal->dev_ver >= 0x30)
1710 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1711 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1712 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1714 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1716 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1718 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1720 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1722 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1723 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1724 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1725 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1728 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1730 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1732 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1734 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1736 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1738 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1741 if (state->internal->dev_ver >= 0x30) {
1742 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1744 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1747 } else if (state->internal->dev_ver >= 0x20) {
1748 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1750 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1754 if (state->srate <= 2000000)
1756 else if (state->srate <= 5000000)
1758 else if (state->srate <= 12000000)
1763 steps = -1 + ((state->search_range / 1000) / car_step);
1765 steps = (2 * steps) + 1;
1768 else if (steps > 10) {
1770 car_step = (state->search_range / 1000) / 10;
1774 freq = state->frequency;
1776 while ((!tmg_lock) && (cur_step < steps)) {
1777 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1779 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1781 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1783 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1785 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1787 /* trigger acquisition */
1788 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1791 for (i = 0; i < 10; i++) {
1792 reg = STV090x_READ_DEMOD(state, DSTATUS);
1793 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1795 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1796 STV090x_READ_DEMOD(state, AGC2I0);
1799 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1802 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1803 (srate_coarse < 50000000) && (srate_coarse > 850000))
1805 else if (cur_step < steps) {
1807 freq += cur_step * car_step;
1809 freq -= cur_step * car_step;
1812 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1815 if (state->config->tuner_set_frequency) {
1816 if (state->config->tuner_set_frequency(fe, freq) < 0)
1820 if (state->config->tuner_set_bandwidth) {
1821 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1825 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1830 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1833 if (state->config->tuner_get_status) {
1834 if (state->config->tuner_get_status(fe, ®) < 0)
1839 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1841 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1843 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1851 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1853 return srate_coarse;
1856 stv090x_i2c_gate_ctrl(state, 0);
1858 dprintk(FE_ERROR, 1, "I/O error");
1862 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1864 u32 srate_coarse, freq_coarse, sym, reg;
1866 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1867 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1868 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1869 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1871 if (sym < state->srate)
1874 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1876 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1878 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1880 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1882 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1884 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1885 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1886 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1889 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1892 if (state->internal->dev_ver >= 0x30) {
1893 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1895 } else if (state->internal->dev_ver >= 0x20) {
1896 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1900 if (srate_coarse > 3000000) {
1901 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1902 sym = (sym / 1000) * 65536;
1903 sym /= (state->internal->mclk / 1000);
1904 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1906 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1908 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1909 sym = (sym / 1000) * 65536;
1910 sym /= (state->internal->mclk / 1000);
1911 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1913 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1915 sym = (srate_coarse / 1000) * 65536;
1916 sym /= (state->internal->mclk / 1000);
1917 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1919 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1922 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1923 sym = (sym / 100) * 65536;
1924 sym /= (state->internal->mclk / 100);
1925 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1927 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1929 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1930 sym = (sym / 100) * 65536;
1931 sym /= (state->internal->mclk / 100);
1932 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1934 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1936 sym = (srate_coarse / 100) * 65536;
1937 sym /= (state->internal->mclk / 100);
1938 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1940 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1943 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1945 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1947 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1949 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1953 return srate_coarse;
1956 dprintk(FE_ERROR, 1, "I/O error");
1960 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1962 s32 timer = 0, lock = 0;
1966 while ((timer < timeout) && (!lock)) {
1967 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1968 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1971 case 0: /* searching */
1972 case 1: /* first PLH detected */
1974 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1977 case 2: /* DVB-S2 mode */
1978 case 3: /* DVB-S1/legacy mode */
1979 reg = STV090x_READ_DEMOD(state, DSTATUS);
1980 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1987 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1994 static int stv090x_blind_search(struct stv090x_state *state)
1996 u32 agc2, reg, srate_coarse;
1997 s32 cpt_fail, agc2_ovflw, i;
1998 u8 k_ref, k_max, k_min;
1999 int coarse_fail = 0;
2005 agc2 = stv090x_get_agc2_min_level(state);
2007 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
2011 if (state->internal->dev_ver <= 0x20) {
2012 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
2016 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
2020 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
2023 if (state->internal->dev_ver >= 0x20) {
2024 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
2026 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
2028 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
2030 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2036 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2038 if (stv090x_srate_srch_coarse(state) != 0) {
2039 srate_coarse = stv090x_srate_srch_fine(state);
2040 if (srate_coarse != 0) {
2041 stv090x_get_lock_tmg(state);
2042 lock = stv090x_get_dmdlock(state,
2043 state->DemodTimeout);
2050 for (i = 0; i < 10; i++) {
2051 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2052 STV090x_READ_DEMOD(state, AGC2I0);
2055 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2056 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2057 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2061 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2067 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2073 dprintk(FE_ERROR, 1, "I/O error");
2077 static int stv090x_chk_tmg(struct stv090x_state *state)
2081 u8 freq, tmg_thh, tmg_thl;
2084 freq = STV090x_READ_DEMOD(state, CARFREQ);
2085 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2086 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2087 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2089 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2092 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2093 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2094 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2096 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2099 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2101 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2104 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2106 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2108 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2111 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2115 for (i = 0; i < 10; i++) {
2116 reg = STV090x_READ_DEMOD(state, DSTATUS);
2117 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2124 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2126 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2128 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2131 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2133 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2135 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2141 dprintk(FE_ERROR, 1, "I/O error");
2145 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2147 struct dvb_frontend *fe = &state->frontend;
2150 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2153 if (state->srate >= 10000000)
2154 timeout_lock = timeout_dmd / 3;
2156 timeout_lock = timeout_dmd / 2;
2158 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2162 if (state->srate >= 10000000) {
2163 if (stv090x_chk_tmg(state)) {
2164 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2166 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2168 return stv090x_get_dmdlock(state, timeout_dmd);
2173 if (state->srate <= 4000000)
2175 else if (state->srate <= 7000000)
2177 else if (state->srate <= 10000000)
2182 steps = (state->search_range / 1000) / car_step;
2184 steps = 2 * (steps + 1);
2187 else if (steps > 12)
2193 freq = state->frequency;
2194 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2195 while ((cur_step <= steps) && (!lock)) {
2197 freq += cur_step * car_step;
2199 freq -= cur_step * car_step;
2202 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2205 if (state->config->tuner_set_frequency) {
2206 if (state->config->tuner_set_frequency(fe, freq) < 0)
2210 if (state->config->tuner_set_bandwidth) {
2211 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2215 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2220 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2223 if (state->config->tuner_get_status) {
2224 if (state->config->tuner_get_status(fe, ®) < 0)
2229 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2231 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2233 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2236 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2237 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2239 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2241 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2243 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2245 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2254 stv090x_i2c_gate_ctrl(state, 0);
2256 dprintk(FE_ERROR, 1, "I/O error");
2260 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2262 s32 timeout, inc, steps_max, srate, car_max;
2264 srate = state->srate;
2265 car_max = state->search_range / 1000;
2266 car_max += car_max / 10;
2267 car_max = 65536 * (car_max / 2);
2268 car_max /= (state->internal->mclk / 1000);
2270 if (car_max > 0x4000)
2271 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2274 inc /= state->internal->mclk / 1000;
2279 switch (state->search_mode) {
2280 case STV090x_SEARCH_DVBS1:
2281 case STV090x_SEARCH_DSS:
2282 inc *= 3; /* freq step = 3% of srate */
2286 case STV090x_SEARCH_DVBS2:
2291 case STV090x_SEARCH_AUTO:
2298 if ((inc > car_max) || (inc < 0))
2299 inc = car_max / 2; /* increment <= 1/8 Mclk */
2301 timeout *= 27500; /* 27.5 Msps reference */
2303 timeout /= (srate / 1000);
2305 if ((timeout > 100) || (timeout < 0))
2308 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2309 if ((steps_max > 100) || (steps_max < 0)) {
2310 steps_max = 100; /* max steps <= 100 */
2311 inc = car_max / steps_max;
2314 *timeout_sw = timeout;
2320 static int stv090x_chk_signal(struct stv090x_state *state)
2322 s32 offst_car, agc2, car_max;
2325 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2326 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2327 offst_car = comp2(offst_car, 16);
2329 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2330 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2331 car_max = state->search_range / 1000;
2333 car_max += (car_max / 10); /* 10% margin */
2334 car_max = (65536 * car_max / 2);
2335 car_max /= state->internal->mclk / 1000;
2337 if (car_max > 0x4000)
2340 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2342 dprintk(FE_DEBUG, 1, "No Signal");
2345 dprintk(FE_DEBUG, 1, "Found Signal");
2351 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2353 int no_signal, lock = 0;
2354 s32 cpt_step = 0, offst_freq, car_max;
2357 car_max = state->search_range / 1000;
2358 car_max += (car_max / 10);
2359 car_max = (65536 * car_max / 2);
2360 car_max /= (state->internal->mclk / 1000);
2361 if (car_max > 0x4000)
2367 offst_freq = -car_max + inc;
2370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2372 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2374 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2376 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2379 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2380 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2381 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2385 if (offst_freq >= 0)
2386 offst_freq = -offst_freq - 2 * inc;
2388 offst_freq = -offst_freq;
2390 offst_freq += 2 * inc;
2395 lock = stv090x_get_dmdlock(state, timeout);
2396 no_signal = stv090x_chk_signal(state);
2400 ((offst_freq - inc) < car_max) &&
2401 ((offst_freq + inc) > -car_max) &&
2402 (cpt_step < steps_max));
2404 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2405 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2406 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2411 dprintk(FE_ERROR, 1, "I/O error");
2415 static int stv090x_sw_algo(struct stv090x_state *state)
2417 int no_signal, zigzag, lock = 0;
2420 s32 dvbs2_fly_wheel;
2421 s32 inc, timeout_step, trials, steps_max;
2424 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2426 switch (state->search_mode) {
2427 case STV090x_SEARCH_DVBS1:
2428 case STV090x_SEARCH_DSS:
2429 /* accelerate the frequency detector */
2430 if (state->internal->dev_ver >= 0x20) {
2431 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2435 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2440 case STV090x_SEARCH_DVBS2:
2441 if (state->internal->dev_ver >= 0x20) {
2442 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2446 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2451 case STV090x_SEARCH_AUTO:
2453 /* accelerate the frequency detector */
2454 if (state->internal->dev_ver >= 0x20) {
2455 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2457 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2461 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2469 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2470 no_signal = stv090x_chk_signal(state);
2473 /*run the SW search 2 times maximum*/
2474 if (lock || no_signal || (trials == 2)) {
2475 /*Check if the demod is not losing lock in DVBS2*/
2476 if (state->internal->dev_ver >= 0x20) {
2477 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2479 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2483 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2484 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2485 /*Check if the demod is not losing lock in DVBS2*/
2486 msleep(timeout_step);
2487 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2488 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2489 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2490 msleep(timeout_step);
2491 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2492 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2494 if (dvbs2_fly_wheel < 0xd) {
2495 /*FALSE lock, The demod is losing lock */
2498 if (state->internal->dev_ver >= 0x20) {
2499 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2503 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2509 } while ((!lock) && (trials < 2) && (!no_signal));
2513 dprintk(FE_ERROR, 1, "I/O error");
2517 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2520 enum stv090x_delsys delsys;
2522 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2523 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2524 delsys = STV090x_DVBS2;
2525 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2526 reg = STV090x_READ_DEMOD(state, FECM);
2527 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2528 delsys = STV090x_DSS;
2530 delsys = STV090x_DVBS1;
2532 delsys = STV090x_ERROR;
2539 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2541 s32 derot, int_1, int_2, tmp_1, tmp_2;
2543 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2544 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2545 derot |= STV090x_READ_DEMOD(state, CFR0);
2547 derot = comp2(derot, 24);
2549 int_2 = derot >> 12;
2551 /* carrier_frequency = MasterClock * Reg / 2^24 */
2552 tmp_1 = mclk % 0x1000;
2553 tmp_2 = derot % 0x1000;
2555 derot = (int_1 * int_2) +
2556 ((int_1 * tmp_2) >> 12) +
2557 ((int_2 * tmp_1) >> 12);
2562 static int stv090x_get_viterbi(struct stv090x_state *state)
2566 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2567 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2571 state->fec = STV090x_PR12;
2575 state->fec = STV090x_PR23;
2579 state->fec = STV090x_PR34;
2583 state->fec = STV090x_PR56;
2587 state->fec = STV090x_PR67;
2591 state->fec = STV090x_PR78;
2595 state->fec = STV090x_PRERR;
2602 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2604 struct dvb_frontend *fe = &state->frontend;
2608 s32 i = 0, offst_freq;
2612 if (state->algo == STV090x_BLIND_SEARCH) {
2613 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2614 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2615 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2616 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2621 state->delsys = stv090x_get_std(state);
2623 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2626 if (state->config->tuner_get_frequency) {
2627 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2631 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2634 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2635 state->frequency += offst_freq;
2637 if (stv090x_get_viterbi(state) < 0)
2640 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2641 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2642 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2643 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2644 reg = STV090x_READ_DEMOD(state, TMGOBS);
2645 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2646 reg = STV090x_READ_DEMOD(state, FECM);
2647 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2649 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2651 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2654 if (state->config->tuner_get_frequency) {
2655 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2659 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2662 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2663 return STV090x_RANGEOK;
2664 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2665 return STV090x_RANGEOK;
2667 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2668 return STV090x_RANGEOK;
2671 return STV090x_OUTOFRANGE;
2674 stv090x_i2c_gate_ctrl(state, 0);
2676 dprintk(FE_ERROR, 1, "I/O error");
2680 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2684 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2685 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2686 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2688 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2692 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2698 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2702 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2704 if (state->internal->dev_ver == 0x20) {
2705 car_loop = stv090x_s2_crl_cut20;
2706 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2707 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2710 car_loop = stv090x_s2_crl_cut30;
2711 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2712 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2715 if (modcod < STV090x_QPSK_12) {
2717 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2725 while ((i < 14) && (modcod != car_loop[i].modcod))
2730 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2738 if (modcod <= STV090x_QPSK_25) {
2740 if (state->srate <= 3000000)
2741 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2742 else if (state->srate <= 7000000)
2743 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2744 else if (state->srate <= 15000000)
2745 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2746 else if (state->srate <= 25000000)
2747 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2749 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2751 if (state->srate <= 3000000)
2752 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2753 else if (state->srate <= 7000000)
2754 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2755 else if (state->srate <= 15000000)
2756 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2757 else if (state->srate <= 25000000)
2758 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2760 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2763 } else if (modcod <= STV090x_8PSK_910) {
2765 if (state->srate <= 3000000)
2766 aclc = car_loop[i].crl_pilots_on_2;
2767 else if (state->srate <= 7000000)
2768 aclc = car_loop[i].crl_pilots_on_5;
2769 else if (state->srate <= 15000000)
2770 aclc = car_loop[i].crl_pilots_on_10;
2771 else if (state->srate <= 25000000)
2772 aclc = car_loop[i].crl_pilots_on_20;
2774 aclc = car_loop[i].crl_pilots_on_30;
2776 if (state->srate <= 3000000)
2777 aclc = car_loop[i].crl_pilots_off_2;
2778 else if (state->srate <= 7000000)
2779 aclc = car_loop[i].crl_pilots_off_5;
2780 else if (state->srate <= 15000000)
2781 aclc = car_loop[i].crl_pilots_off_10;
2782 else if (state->srate <= 25000000)
2783 aclc = car_loop[i].crl_pilots_off_20;
2785 aclc = car_loop[i].crl_pilots_off_30;
2787 } else { /* 16APSK and 32APSK */
2789 * This should never happen in practice, except if
2790 * something is really wrong at the car_loop table.
2794 if (state->srate <= 3000000)
2795 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2796 else if (state->srate <= 7000000)
2797 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2798 else if (state->srate <= 15000000)
2799 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2800 else if (state->srate <= 25000000)
2801 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2803 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2809 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2811 struct stv090x_short_frame_crloop *short_crl = NULL;
2815 switch (state->modulation) {
2823 case STV090x_16APSK:
2826 case STV090x_32APSK:
2831 if (state->internal->dev_ver >= 0x30) {
2832 /* Cut 3.0 and up */
2833 short_crl = stv090x_s2_short_crl_cut30;
2835 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2836 short_crl = stv090x_s2_short_crl_cut20;
2839 if (state->srate <= 3000000)
2840 aclc = short_crl[index].crl_2;
2841 else if (state->srate <= 7000000)
2842 aclc = short_crl[index].crl_5;
2843 else if (state->srate <= 15000000)
2844 aclc = short_crl[index].crl_10;
2845 else if (state->srate <= 25000000)
2846 aclc = short_crl[index].crl_20;
2848 aclc = short_crl[index].crl_30;
2853 static int stv090x_optimize_track(struct stv090x_state *state)
2855 struct dvb_frontend *fe = &state->frontend;
2857 enum stv090x_modcod modcod;
2859 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2862 srate = stv090x_get_srate(state, state->internal->mclk);
2863 srate += stv090x_get_tmgoffst(state, srate);
2865 switch (state->delsys) {
2868 if (state->search_mode == STV090x_SEARCH_AUTO) {
2869 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2870 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2871 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2872 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2875 reg = STV090x_READ_DEMOD(state, DEMOD);
2876 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2877 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2878 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2881 if (state->internal->dev_ver >= 0x30) {
2882 if (stv090x_get_viterbi(state) < 0)
2885 if (state->fec == STV090x_PR12) {
2886 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2888 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2891 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2893 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2898 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2903 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2904 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2905 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2906 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2908 if (state->internal->dev_ver >= 0x30) {
2909 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2911 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2914 if (state->frame_len == STV090x_LONG_FRAME) {
2915 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2916 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2917 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2918 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2919 if (modcod <= STV090x_QPSK_910) {
2920 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2921 } else if (modcod <= STV090x_8PSK_910) {
2922 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2924 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2927 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2928 if (modcod <= STV090x_16APSK_910) {
2929 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2931 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2934 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2936 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2941 /*Carrier loop setting for short frame*/
2942 aclc = stv090x_optimize_carloop_short(state);
2943 if (state->modulation == STV090x_QPSK) {
2944 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2946 } else if (state->modulation == STV090x_8PSK) {
2947 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2949 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2951 } else if (state->modulation == STV090x_16APSK) {
2952 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2954 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2956 } else if (state->modulation == STV090x_32APSK) {
2957 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2959 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2964 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2969 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2970 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2971 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2972 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2977 f_1 = STV090x_READ_DEMOD(state, CFR2);
2978 f_0 = STV090x_READ_DEMOD(state, CFR1);
2979 reg = STV090x_READ_DEMOD(state, TMGOBS);
2981 if (state->algo == STV090x_BLIND_SEARCH) {
2982 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2983 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2984 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2985 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2986 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2988 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2991 if (stv090x_set_srate(state, srate) < 0)
2995 if (stv090x_dvbs_track_crl(state) < 0)
2999 if (state->internal->dev_ver >= 0x20) {
3000 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
3001 (state->search_mode == STV090x_SEARCH_DSS) ||
3002 (state->search_mode == STV090x_SEARCH_AUTO)) {
3004 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
3006 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
3011 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3014 /* AUTO tracking MODE */
3015 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
3017 /* AUTO tracking MODE */
3018 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
3021 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
3022 (state->srate < 10000000)) {
3023 /* update initial carrier freq with the found freq offset */
3024 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3026 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3028 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
3030 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3032 if (state->algo != STV090x_WARM_SEARCH) {
3034 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3037 if (state->config->tuner_set_bandwidth) {
3038 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3042 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3047 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3048 msleep(50); /* blind search: wait 50ms for SR stabilization */
3052 stv090x_get_lock_tmg(state);
3054 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3055 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3057 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3059 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3061 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3066 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3068 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3070 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3072 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3074 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3082 if (state->internal->dev_ver >= 0x20) {
3083 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3087 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3088 stv090x_set_vit_thtracq(state);
3093 stv090x_i2c_gate_ctrl(state, 0);
3095 dprintk(FE_ERROR, 1, "I/O error");
3099 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3101 s32 timer = 0, lock = 0, stat;
3104 while ((timer < timeout) && (!lock)) {
3105 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3106 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3109 case 0: /* searching */
3110 case 1: /* first PLH detected */
3115 case 2: /* DVB-S2 mode */
3116 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3117 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3120 case 3: /* DVB-S1/legacy mode */
3121 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3122 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3133 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3139 lock = stv090x_get_dmdlock(state, timeout_dmd);
3141 lock = stv090x_get_feclock(state, timeout_fec);
3146 while ((timer < timeout_fec) && (!lock)) {
3147 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3148 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3157 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3161 if (state->internal->dev_ver <= 0x20) {
3162 /* rolloff to auto mode if DVBS2 */
3163 reg = STV090x_READ_DEMOD(state, DEMOD);
3164 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3165 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3168 /* DVB-S2 rolloff to auto mode if DVBS2 */
3169 reg = STV090x_READ_DEMOD(state, DEMOD);
3170 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3171 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3176 dprintk(FE_ERROR, 1, "I/O error");
3181 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3183 struct dvb_frontend *fe = &state->frontend;
3184 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3186 s32 agc1_power, power_iq = 0, i;
3187 int lock = 0, low_sr = 0;
3189 reg = STV090x_READ_DEMOD(state, TSCFGH);
3190 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3191 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3194 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3197 if (state->internal->dev_ver >= 0x20) {
3198 if (state->srate > 5000000) {
3199 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3202 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3207 stv090x_get_lock_tmg(state);
3209 if (state->algo == STV090x_BLIND_SEARCH) {
3210 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3211 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3213 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3215 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
3219 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3221 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3224 if (state->srate < 2000000) {
3226 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3230 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3234 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3237 if (state->internal->dev_ver >= 0x20) {
3238 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3240 if (state->algo == STV090x_COLD_SEARCH)
3241 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3242 else if (state->algo == STV090x_WARM_SEARCH)
3243 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3246 /* if cold start or warm (Symbolrate is known)
3247 * use a Narrow symbol rate scan range
3249 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3252 if (stv090x_set_srate(state, state->srate) < 0)
3255 if (stv090x_set_max_srate(state, state->internal->mclk,
3258 if (stv090x_set_min_srate(state, state->internal->mclk,
3262 if (state->srate >= 10000000)
3269 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3272 if (state->config->tuner_set_bbgain) {
3273 reg = state->config->tuner_bbgain;
3275 reg = 10; /* default: 10dB */
3276 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3280 if (state->config->tuner_set_frequency) {
3281 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3285 if (state->config->tuner_set_bandwidth) {
3286 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3290 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3295 if (state->config->tuner_get_status) {
3296 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3298 if (state->config->tuner_get_status(fe, ®) < 0)
3300 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3304 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3306 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3307 return STV090x_NOCARRIER;
3312 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3313 STV090x_READ_DEMOD(state, AGCIQIN0));
3315 if (agc1_power == 0) {
3316 /* If AGC1 integrator value is 0
3317 * then read POWERI, POWERQ
3319 for (i = 0; i < 5; i++) {
3320 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3321 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3326 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3327 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3329 signal_state = STV090x_NOAGC1;
3331 reg = STV090x_READ_DEMOD(state, DEMOD);
3332 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3334 if (state->internal->dev_ver <= 0x20) {
3335 /* rolloff to auto mode if DVBS2 */
3336 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3338 /* DVB-S2 rolloff to auto mode if DVBS2 */
3339 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3341 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3344 if (stv090x_delivery_search(state) < 0)
3347 if (state->algo != STV090x_BLIND_SEARCH) {
3348 if (stv090x_start_search(state) < 0)
3353 if (signal_state == STV090x_NOAGC1)
3354 return signal_state;
3356 if (state->algo == STV090x_BLIND_SEARCH)
3357 lock = stv090x_blind_search(state);
3359 else if (state->algo == STV090x_COLD_SEARCH)
3360 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3362 else if (state->algo == STV090x_WARM_SEARCH)
3363 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3365 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3367 if (stv090x_chk_tmg(state))
3368 lock = stv090x_sw_algo(state);
3373 signal_state = stv090x_get_sig_params(state);
3375 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3376 stv090x_optimize_track(state);
3378 if (state->internal->dev_ver >= 0x20) {
3379 /* >= Cut 2.0 :release TS reset after
3380 * demod lock and optimized Tracking
3382 reg = STV090x_READ_DEMOD(state, TSCFGH);
3383 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3384 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3389 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3390 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3393 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3394 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3398 lock = stv090x_get_lock(state, state->FecTimeout,
3401 if (state->delsys == STV090x_DVBS2) {
3402 stv090x_set_s2rolloff(state);
3404 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3405 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3406 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3408 /* Reset DVBS2 packet delinator error counter */
3409 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3410 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3411 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3414 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3417 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3420 /* Reset the Total packet counter */
3421 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3423 /* Reset the packet Error counter2 */
3424 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3427 signal_state = STV090x_NODATA;
3428 stv090x_chk_signal(state);
3431 return signal_state;
3434 stv090x_i2c_gate_ctrl(state, 0);
3436 dprintk(FE_ERROR, 1, "I/O error");
3440 static int stv090x_set_mis(struct stv090x_state *state, int mis)
3444 if (mis < 0 || mis > 255) {
3445 dprintk(FE_DEBUG, 1, "Disable MIS filtering");
3446 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3447 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
3448 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3451 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
3452 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3453 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
3454 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3456 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
3458 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
3463 dprintk(FE_ERROR, 1, "I/O error");
3467 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
3469 struct stv090x_state *state = fe->demodulator_priv;
3470 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3472 if (props->frequency == 0)
3473 return DVBFE_ALGO_SEARCH_INVALID;
3475 switch (props->delivery_system) {
3477 state->delsys = STV090x_DSS;
3480 state->delsys = STV090x_DVBS1;
3483 state->delsys = STV090x_DVBS2;
3486 return DVBFE_ALGO_SEARCH_INVALID;
3489 state->frequency = props->frequency;
3490 state->srate = props->symbol_rate;
3491 state->search_mode = STV090x_SEARCH_AUTO;
3492 state->algo = STV090x_COLD_SEARCH;
3493 state->fec = STV090x_PRERR;
3494 if (state->srate > 10000000) {
3495 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3496 state->search_range = 10000000;
3498 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3499 state->search_range = 5000000;
3502 stv090x_set_mis(state, props->stream_id);
3504 if (stv090x_algo(state) == STV090x_RANGEOK) {
3505 dprintk(FE_DEBUG, 1, "Search success!");
3506 return DVBFE_ALGO_SEARCH_SUCCESS;
3508 dprintk(FE_DEBUG, 1, "Search failed!");
3509 return DVBFE_ALGO_SEARCH_FAILED;
3512 return DVBFE_ALGO_SEARCH_ERROR;
3515 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3517 struct stv090x_state *state = fe->demodulator_priv;
3523 dstatus = STV090x_READ_DEMOD(state, DSTATUS);
3524 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
3525 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
3527 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3528 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3530 switch (search_state) {
3531 case 0: /* searching */
3532 case 1: /* first PLH detected */
3534 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3537 case 2: /* DVB-S2 mode */
3538 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3539 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3540 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3541 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3542 *status |= FE_HAS_VITERBI;
3543 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3544 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3545 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3550 case 3: /* DVB-S1/legacy mode */
3551 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3552 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3553 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3554 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3555 *status |= FE_HAS_VITERBI;
3556 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3557 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3558 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3567 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3569 struct stv090x_state *state = fe->demodulator_priv;
3571 s32 count_4, count_3, count_2, count_1, count_0, count;
3573 enum fe_status status;
3575 stv090x_read_status(fe, &status);
3576 if (!(status & FE_HAS_LOCK)) {
3577 *per = 1 << 23; /* Max PER */
3580 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3581 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3583 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3584 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3586 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3587 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3589 *per = ((h << 16) | (m << 8) | l);
3591 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3592 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3593 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3594 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3595 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3597 if ((!count_4) && (!count_3)) {
3598 count = (count_2 & 0xff) << 16;
3599 count |= (count_1 & 0xff) << 8;
3600 count |= count_0 & 0xff;
3607 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3609 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3614 dprintk(FE_ERROR, 1, "I/O error");
3618 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3623 if ((val >= tab[min].read && val < tab[max].read) ||
3624 (val >= tab[max].read && val < tab[min].read)) {
3625 while ((max - min) > 1) {
3626 med = (max + min) / 2;
3627 if ((val >= tab[min].read && val < tab[med].read) ||
3628 (val >= tab[med].read && val < tab[min].read))
3633 res = ((val - tab[min].read) *
3634 (tab[max].real - tab[min].real) /
3635 (tab[max].read - tab[min].read)) +
3638 if (tab[min].read < tab[max].read) {
3639 if (val < tab[min].read)
3640 res = tab[min].real;
3641 else if (val >= tab[max].read)
3642 res = tab[max].real;
3644 if (val >= tab[min].read)
3645 res = tab[min].real;
3646 else if (val < tab[max].read)
3647 res = tab[max].real;
3654 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3656 struct stv090x_state *state = fe->demodulator_priv;
3658 s32 agc_0, agc_1, agc;
3661 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3662 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3663 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3664 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3665 agc = MAKEWORD16(agc_1, agc_0);
3667 str = stv090x_table_lookup(stv090x_rf_tab,
3668 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3669 if (agc > stv090x_rf_tab[0].read)
3671 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3673 *strength = (str + 100) * 0xFFFF / 100;
3678 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3680 struct stv090x_state *state = fe->demodulator_priv;
3681 u32 reg_0, reg_1, reg, i;
3682 s32 val_0, val_1, val = 0;
3687 switch (state->delsys) {
3689 reg = STV090x_READ_DEMOD(state, DSTATUS);
3690 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3693 for (i = 0; i < 16; i++) {
3694 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3695 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3696 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3697 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3698 val += MAKEWORD16(val_1, val_0);
3702 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3703 div = stv090x_s2cn_tab[0].read -
3704 stv090x_s2cn_tab[last].read;
3705 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3711 reg = STV090x_READ_DEMOD(state, DSTATUS);
3712 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3715 for (i = 0; i < 16; i++) {
3716 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3717 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3718 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3719 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3720 val += MAKEWORD16(val_1, val_0);
3724 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3725 div = stv090x_s1cn_tab[0].read -
3726 stv090x_s1cn_tab[last].read;
3727 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3737 static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
3739 struct stv090x_state *state = fe->demodulator_priv;
3742 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3745 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3746 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3747 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3749 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3750 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3755 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3756 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3757 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3766 dprintk(FE_ERROR, 1, "I/O error");
3771 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3773 return DVBFE_ALGO_CUSTOM;
3776 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3778 struct stv090x_state *state = fe->demodulator_priv;
3779 u32 reg, idle = 0, fifo_full = 1;
3782 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3784 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3785 (state->config->diseqc_envelope_mode) ? 4 : 2);
3786 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3787 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3789 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3790 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3793 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3794 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3797 for (i = 0; i < cmd->msg_len; i++) {
3800 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3801 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3804 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3807 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3808 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3809 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3814 while ((!idle) && (i < 10)) {
3815 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3816 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3823 dprintk(FE_ERROR, 1, "I/O error");
3827 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
3828 enum fe_sec_mini_cmd burst)
3830 struct stv090x_state *state = fe->demodulator_priv;
3831 u32 reg, idle = 0, fifo_full = 1;
3835 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3837 if (burst == SEC_MINI_A) {
3838 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3841 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3845 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3846 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3847 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3849 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3850 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3853 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3854 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3858 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3859 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3862 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3865 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3866 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3867 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3872 while ((!idle) && (i < 10)) {
3873 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3874 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3881 dprintk(FE_ERROR, 1, "I/O error");
3885 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3887 struct stv090x_state *state = fe->demodulator_priv;
3888 u32 reg = 0, i = 0, rx_end = 0;
3890 while ((rx_end != 1) && (i < 10)) {
3893 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3894 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3898 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3899 for (i = 0; i < reply->msg_len; i++)
3900 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3906 static int stv090x_sleep(struct dvb_frontend *fe)
3908 struct stv090x_state *state = fe->demodulator_priv;
3910 u8 full_standby = 0;
3912 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3915 if (state->config->tuner_sleep) {
3916 if (state->config->tuner_sleep(fe) < 0)
3920 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3923 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
3924 state->device == STV0900 ? "STV0900" : "STV0903",
3927 mutex_lock(&state->internal->demod_lock);
3929 switch (state->demod) {
3930 case STV090x_DEMODULATOR_0:
3931 /* power off ADC 1 */
3932 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3933 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3934 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3936 /* power off DiSEqC 1 */
3937 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3938 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3939 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3942 /* check whether path 2 is already sleeping, that is when
3944 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3945 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3949 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3950 /* packet delineator 1 clock */
3951 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3953 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3954 /* FEC clock is shared between the two paths, only stop it
3955 when full standby is possible */
3957 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3958 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3960 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3961 /* sampling 1 clock */
3962 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3963 /* viterbi 1 clock */
3964 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3965 /* TS clock is shared between the two paths, only stop it
3966 when full standby is possible */
3968 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3969 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3973 case STV090x_DEMODULATOR_1:
3974 /* power off ADC 2 */
3975 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3976 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3977 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3979 /* power off DiSEqC 2 */
3980 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3981 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3982 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3985 /* check whether path 1 is already sleeping, that is when
3987 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3988 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3992 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3993 /* packet delineator 2 clock */
3994 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3996 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
3997 /* FEC clock is shared between the two paths, only stop it
3998 when full standby is possible */
4000 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
4001 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4003 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4004 /* sampling 2 clock */
4005 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
4006 /* viterbi 2 clock */
4007 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
4008 /* TS clock is shared between the two paths, only stop it
4009 when full standby is possible */
4011 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
4012 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4017 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4022 /* general power off */
4023 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4024 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
4025 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4029 mutex_unlock(&state->internal->demod_lock);
4033 stv090x_i2c_gate_ctrl(state, 0);
4036 mutex_unlock(&state->internal->demod_lock);
4038 dprintk(FE_ERROR, 1, "I/O error");
4042 static int stv090x_wakeup(struct dvb_frontend *fe)
4044 struct stv090x_state *state = fe->demodulator_priv;
4047 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
4048 state->device == STV0900 ? "STV0900" : "STV0903",
4051 mutex_lock(&state->internal->demod_lock);
4053 /* general power on */
4054 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4055 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
4056 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4059 switch (state->demod) {
4060 case STV090x_DEMODULATOR_0:
4061 /* power on ADC 1 */
4062 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4063 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4064 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4066 /* power on DiSEqC 1 */
4067 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4068 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4069 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4072 /* activate clocks */
4073 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4074 /* packet delineator 1 clock */
4075 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4077 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4079 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4080 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4082 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4083 /* sampling 1 clock */
4084 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4085 /* viterbi 1 clock */
4086 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4088 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4089 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4093 case STV090x_DEMODULATOR_1:
4094 /* power on ADC 2 */
4095 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4096 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4097 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4099 /* power on DiSEqC 2 */
4100 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4101 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4102 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4105 /* activate clocks */
4106 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4107 /* packet delineator 2 clock */
4108 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4110 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4112 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4113 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4115 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4116 /* sampling 2 clock */
4117 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4118 /* viterbi 2 clock */
4119 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4121 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4122 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4127 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4131 mutex_unlock(&state->internal->demod_lock);
4134 mutex_unlock(&state->internal->demod_lock);
4135 dprintk(FE_ERROR, 1, "I/O error");
4139 static void stv090x_release(struct dvb_frontend *fe)
4141 struct stv090x_state *state = fe->demodulator_priv;
4143 state->internal->num_used--;
4144 if (state->internal->num_used <= 0) {
4146 dprintk(FE_ERROR, 1, "Actually removing");
4148 remove_dev(state->internal);
4149 kfree(state->internal);
4155 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
4159 reg = stv090x_read_reg(state, STV090x_GENCFG);
4161 switch (ldpc_mode) {
4164 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4165 /* set LDPC to dual mode */
4166 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4169 state->demod_mode = STV090x_DUAL;
4171 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4172 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4173 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4175 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4176 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4179 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
4181 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
4183 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
4185 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
4187 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
4189 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
4191 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
4194 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
4196 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
4198 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
4200 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
4202 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
4204 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
4206 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
4209 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
4211 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
4216 case STV090x_SINGLE:
4217 if (stv090x_stop_modcod(state) < 0)
4219 if (stv090x_activate_modcod_single(state) < 0)
4222 if (state->demod == STV090x_DEMODULATOR_1) {
4223 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4226 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4230 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4231 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4232 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4234 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4235 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4238 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4239 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
4240 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4242 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4243 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4250 dprintk(FE_ERROR, 1, "I/O error");
4254 /* return (Hz), clk in Hz*/
4255 static u32 stv090x_get_mclk(struct stv090x_state *state)
4257 const struct stv090x_config *config = state->config;
4261 div = stv090x_read_reg(state, STV090x_NCOARSE);
4262 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4263 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4265 return (div + 1) * config->xtal / ratio; /* kHz */
4268 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4270 const struct stv090x_config *config = state->config;
4271 u32 reg, div, clk_sel;
4273 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4274 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4276 div = ((clk_sel * mclk) / config->xtal) - 1;
4278 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4279 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4280 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4283 state->internal->mclk = stv090x_get_mclk(state);
4285 /*Set the DiseqC frequency to 22KHz */
4286 div = state->internal->mclk / 704000;
4287 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4289 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4294 dprintk(FE_ERROR, 1, "I/O error");
4298 static int stv0900_set_tspath(struct stv090x_state *state)
4302 if (state->internal->dev_ver >= 0x20) {
4303 switch (state->config->ts1_mode) {
4304 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4305 case STV090x_TSMODE_DVBCI:
4306 switch (state->config->ts2_mode) {
4307 case STV090x_TSMODE_SERIAL_PUNCTURED:
4308 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4310 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4313 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4314 case STV090x_TSMODE_DVBCI:
4315 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4317 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4318 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4319 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4321 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4322 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4323 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4325 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4327 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4333 case STV090x_TSMODE_SERIAL_PUNCTURED:
4334 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4336 switch (state->config->ts2_mode) {
4337 case STV090x_TSMODE_SERIAL_PUNCTURED:
4338 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4340 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4344 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4345 case STV090x_TSMODE_DVBCI:
4346 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4353 switch (state->config->ts1_mode) {
4354 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4355 case STV090x_TSMODE_DVBCI:
4356 switch (state->config->ts2_mode) {
4357 case STV090x_TSMODE_SERIAL_PUNCTURED:
4358 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4360 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4363 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4364 case STV090x_TSMODE_DVBCI:
4365 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4366 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4367 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4368 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4370 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4371 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4372 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4374 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4376 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4382 case STV090x_TSMODE_SERIAL_PUNCTURED:
4383 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4385 switch (state->config->ts2_mode) {
4386 case STV090x_TSMODE_SERIAL_PUNCTURED:
4387 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4389 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4392 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4393 case STV090x_TSMODE_DVBCI:
4394 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4401 switch (state->config->ts1_mode) {
4402 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4403 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4404 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4405 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4406 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4407 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4411 case STV090x_TSMODE_DVBCI:
4412 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4413 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4414 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4415 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4416 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4420 case STV090x_TSMODE_SERIAL_PUNCTURED:
4421 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4422 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4423 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4424 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4425 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4429 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4430 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4431 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4432 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4433 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4434 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4442 switch (state->config->ts2_mode) {
4443 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4444 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4445 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4446 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4447 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4448 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4452 case STV090x_TSMODE_DVBCI:
4453 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4454 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4455 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4456 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4457 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4461 case STV090x_TSMODE_SERIAL_PUNCTURED:
4462 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4463 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4464 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4465 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4466 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4470 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4471 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4472 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4473 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4474 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4475 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4483 if (state->config->ts1_clk > 0) {
4486 switch (state->config->ts1_mode) {
4487 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4488 case STV090x_TSMODE_DVBCI:
4490 speed = state->internal->mclk /
4491 (state->config->ts1_clk / 4);
4497 case STV090x_TSMODE_SERIAL_PUNCTURED:
4498 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4499 speed = state->internal->mclk /
4500 (state->config->ts1_clk / 32);
4507 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4508 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4509 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4511 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4515 if (state->config->ts2_clk > 0) {
4518 switch (state->config->ts2_mode) {
4519 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4520 case STV090x_TSMODE_DVBCI:
4522 speed = state->internal->mclk /
4523 (state->config->ts2_clk / 4);
4529 case STV090x_TSMODE_SERIAL_PUNCTURED:
4530 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4531 speed = state->internal->mclk /
4532 (state->config->ts2_clk / 32);
4539 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4540 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4541 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4543 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4547 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4548 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4549 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4551 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4552 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4555 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4556 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4557 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4559 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4560 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4565 dprintk(FE_ERROR, 1, "I/O error");
4569 static int stv0903_set_tspath(struct stv090x_state *state)
4573 if (state->internal->dev_ver >= 0x20) {
4574 switch (state->config->ts1_mode) {
4575 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4576 case STV090x_TSMODE_DVBCI:
4577 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4580 case STV090x_TSMODE_SERIAL_PUNCTURED:
4581 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4583 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4587 switch (state->config->ts1_mode) {
4588 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4589 case STV090x_TSMODE_DVBCI:
4590 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4593 case STV090x_TSMODE_SERIAL_PUNCTURED:
4594 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4596 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4601 switch (state->config->ts1_mode) {
4602 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4603 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4604 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4605 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4606 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4610 case STV090x_TSMODE_DVBCI:
4611 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4612 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4613 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4614 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4618 case STV090x_TSMODE_SERIAL_PUNCTURED:
4619 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4620 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4621 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4622 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4626 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4627 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4628 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4629 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4630 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4638 if (state->config->ts1_clk > 0) {
4641 switch (state->config->ts1_mode) {
4642 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4643 case STV090x_TSMODE_DVBCI:
4645 speed = state->internal->mclk /
4646 (state->config->ts1_clk / 4);
4652 case STV090x_TSMODE_SERIAL_PUNCTURED:
4653 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4654 speed = state->internal->mclk /
4655 (state->config->ts1_clk / 32);
4662 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4663 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4664 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4666 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4670 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4671 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4672 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4674 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4675 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4680 dprintk(FE_ERROR, 1, "I/O error");
4684 static int stv090x_init(struct dvb_frontend *fe)
4686 struct stv090x_state *state = fe->demodulator_priv;
4687 const struct stv090x_config *config = state->config;
4690 if (state->internal->mclk == 0) {
4691 /* call tuner init to configure the tuner's clock output
4692 divider directly before setting up the master clock of
4694 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4697 if (config->tuner_init) {
4698 if (config->tuner_init(fe) < 0)
4702 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4705 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4707 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4708 0x20 | config->clk_mode) < 0)
4710 stv090x_get_mclk(state);
4713 if (stv090x_wakeup(fe) < 0) {
4714 dprintk(FE_ERROR, 1, "Error waking device");
4718 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4721 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4722 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4723 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4725 reg = STV090x_READ_DEMOD(state, DEMOD);
4726 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4727 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4730 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4733 if (config->tuner_set_mode) {
4734 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4738 if (config->tuner_init) {
4739 if (config->tuner_init(fe) < 0)
4743 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4746 if (state->device == STV0900) {
4747 if (stv0900_set_tspath(state) < 0)
4750 if (stv0903_set_tspath(state) < 0)
4757 stv090x_i2c_gate_ctrl(state, 0);
4759 dprintk(FE_ERROR, 1, "I/O error");
4763 static int stv090x_setup(struct dvb_frontend *fe)
4765 struct stv090x_state *state = fe->demodulator_priv;
4766 const struct stv090x_config *config = state->config;
4767 const struct stv090x_reg *stv090x_initval = NULL;
4768 const struct stv090x_reg *stv090x_cut20_val = NULL;
4769 unsigned long t1_size = 0, t2_size = 0;
4774 if (state->device == STV0900) {
4775 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4776 stv090x_initval = stv0900_initval;
4777 t1_size = ARRAY_SIZE(stv0900_initval);
4778 stv090x_cut20_val = stv0900_cut20_val;
4779 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4780 } else if (state->device == STV0903) {
4781 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4782 stv090x_initval = stv0903_initval;
4783 t1_size = ARRAY_SIZE(stv0903_initval);
4784 stv090x_cut20_val = stv0903_cut20_val;
4785 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4791 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4793 if (state->device == STV0900)
4794 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4799 /* Set No Tuner Mode */
4800 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4802 if (state->device == STV0900)
4803 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4806 /* I2C repeater OFF */
4807 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4808 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4810 if (state->device == STV0900)
4811 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4814 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4817 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4819 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4824 dprintk(FE_DEBUG, 1, "Setting up initial values");
4825 for (i = 0; i < t1_size; i++) {
4826 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4830 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4831 if (state->internal->dev_ver >= 0x20) {
4832 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4835 /* write cut20_val*/
4836 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4837 for (i = 0; i < t2_size; i++) {
4838 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4842 } else if (state->internal->dev_ver < 0x20) {
4843 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4844 state->internal->dev_ver);
4847 } else if (state->internal->dev_ver > 0x30) {
4848 /* we shouldn't bail out from here */
4849 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4850 state->internal->dev_ver);
4854 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4855 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4856 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4857 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4861 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4862 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4863 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4864 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4867 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4869 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4874 dprintk(FE_ERROR, 1, "I/O error");
4878 static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
4879 u8 value, u8 xor_value)
4881 struct stv090x_state *state = fe->demodulator_priv;
4884 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4885 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4886 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4888 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4891 static struct dvb_frontend_ops stv090x_ops = {
4892 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
4894 .name = "STV090x Multistandard",
4895 .frequency_min = 950000,
4896 .frequency_max = 2150000,
4897 .frequency_stepsize = 0,
4898 .frequency_tolerance = 0,
4899 .symbol_rate_min = 1000000,
4900 .symbol_rate_max = 45000000,
4901 .caps = FE_CAN_INVERSION_AUTO |
4904 FE_CAN_2G_MODULATION
4907 .release = stv090x_release,
4908 .init = stv090x_init,
4910 .sleep = stv090x_sleep,
4911 .get_frontend_algo = stv090x_frontend_algo,
4913 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4914 .diseqc_send_burst = stv090x_send_diseqc_burst,
4915 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4916 .set_tone = stv090x_set_tone,
4918 .search = stv090x_search,
4919 .read_status = stv090x_read_status,
4920 .read_ber = stv090x_read_per,
4921 .read_signal_strength = stv090x_read_signal_strength,
4922 .read_snr = stv090x_read_cnr,
4926 struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
4927 struct i2c_adapter *i2c,
4928 enum stv090x_demodulator demod)
4930 struct stv090x_state *state = NULL;
4931 struct stv090x_dev *temp_int;
4933 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4937 state->verbose = &verbose;
4938 state->config = config;
4940 state->frontend.ops = stv090x_ops;
4941 state->frontend.demodulator_priv = state;
4942 state->demod = demod;
4943 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4944 state->device = config->device;
4945 state->rolloff = STV090x_RO_35; /* default */
4947 temp_int = find_dev(state->i2c,
4948 state->config->address);
4950 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4951 state->internal = temp_int->internal;
4952 state->internal->num_used++;
4953 dprintk(FE_INFO, 1, "Found Internal Structure!");
4955 state->internal = kmalloc(sizeof(struct stv090x_internal),
4957 if (!state->internal)
4959 temp_int = append_internal(state->internal);
4961 kfree(state->internal);
4964 state->internal->num_used = 1;
4965 state->internal->mclk = 0;
4966 state->internal->dev_ver = 0;
4967 state->internal->i2c_adap = state->i2c;
4968 state->internal->i2c_addr = state->config->address;
4969 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4971 mutex_init(&state->internal->demod_lock);
4972 mutex_init(&state->internal->tuner_lock);
4974 if (stv090x_setup(&state->frontend) < 0) {
4975 dprintk(FE_ERROR, 1, "Error setting up device");
4980 if (state->internal->dev_ver >= 0x30)
4981 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
4983 /* workaround for stuck DiSEqC output */
4984 if (config->diseqc_envelope_mode)
4985 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4987 config->set_gpio = stv090x_set_gpio;
4989 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4990 state->device == STV0900 ? "STV0900" : "STV0903",
4992 state->internal->dev_ver);
4994 return &state->frontend;
4997 remove_dev(state->internal);
4998 kfree(state->internal);
5003 EXPORT_SYMBOL(stv090x_attach);
5004 MODULE_PARM_DESC(verbose, "Set Verbosity level");
5005 MODULE_AUTHOR("Manu Abraham");
5006 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
5007 MODULE_LICENSE("GPL");