dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&wakeupgen>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 mmc0 = &mmc1;
  25                 mmc1 = &mmc2;
  26                 mmc2 = &mmc3;
  27                 mmc3 = &mmc4;
  28                 mmc4 = &mmc5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         compatible = "arm,cortex-a9";
  41                         device_type = "cpu";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x0>;
  44
  45                         clocks = <&dpll_mpu_ck>;
  46                         clock-names = "cpu";
  47
  48                         clock-latency = <300000>; /* From omap-cpufreq driver */
  49                 };
  50                 cpu@1 {
  51                         compatible = "arm,cortex-a9";
  52                         device_type = "cpu";
  53                         next-level-cache = <&L2>;
  54                         reg = <0x1>;
  55                 };
  56         };
  57
  58         gic: interrupt-controller@48241000 {
  59                 compatible = "arm,cortex-a9-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x48241000 0x1000>,
  63                       <0x48240100 0x0100>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         L2: l2-cache-controller@48242000 {
  68                 compatible = "arm,pl310-cache";
  69                 reg = <0x48242000 0x1000>;
  70                 cache-unified;
  71                 cache-level = <2>;
  72         };
  73
  74         local-timer@48240600 {
  75                 compatible = "arm,cortex-a9-twd-timer";
  76                 clocks = <&mpu_periphclk>;
  77                 reg = <0x48240600 0x20>;
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  79                 interrupt-parent = <&gic>;
  80         };
  81
  82         wakeupgen: interrupt-controller@48281000 {
  83                 compatible = "ti,omap4-wugen-mpu";
  84                 interrupt-controller;
  85                 #interrupt-cells = <3>;
  86                 reg = <0x48281000 0x1000>;
  87                 interrupt-parent = <&gic>;
  88         };
  89
  90         /*
  91          * The soc node represents the soc top level view. It is used for IPs
  92          * that are not memory mapped in the MPU view or for the MPU itself.
  93          */
  94         soc {
  95                 compatible = "ti,omap-infra";
  96                 mpu {
  97                         compatible = "ti,omap4-mpu";
  98                         ti,hwmods = "mpu";
  99                         sram = <&ocmcram>;
 100                 };
 101
 102                 dsp {
 103                         compatible = "ti,omap3-c64";
 104                         ti,hwmods = "dsp";
 105                 };
 106
 107                 iva {
 108                         compatible = "ti,ivahd";
 109                         ti,hwmods = "iva";
 110                 };
 111         };
 112
 113         /*
 114          * XXX: Use a flat representation of the OMAP4 interconnect.
 115          * The real OMAP interconnect network is quite complex.
 116          * Since it will not bring real advantage to represent that in DT for
 117          * the moment, just use a fake OCP bus entry to represent the whole bus
 118          * hierarchy.
 119          */
 120         ocp {
 121                 compatible = "ti,omap4-l3-noc", "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 126                 reg = <0x44000000 0x1000>,
 127                       <0x44800000 0x2000>,
 128                       <0x45000000 0x1000>;
 129                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 131
 132                 l4_cfg: l4@4a000000 {
 133                         compatible = "ti,omap4-l4-cfg", "simple-bus";
 134                         #address-cells = <1>;
 135                         #size-cells = <1>;
 136                         ranges = <0 0x4a000000 0x1000000>;
 137
 138                         cm1: cm1@4000 {
 139                                 compatible = "ti,omap4-cm1";
 140                                 reg = <0x4000 0x2000>;
 141
 142                                 cm1_clocks: clocks {
 143                                         #address-cells = <1>;
 144                                         #size-cells = <0>;
 145                                 };
 146
 147                                 cm1_clockdomains: clockdomains {
 148                                 };
 149                         };
 150
 151                         cm2: cm2@8000 {
 152                                 compatible = "ti,omap4-cm2";
 153                                 reg = <0x8000 0x3000>;
 154
 155                                 cm2_clocks: clocks {
 156                                         #address-cells = <1>;
 157                                         #size-cells = <0>;
 158                                 };
 159
 160                                 cm2_clockdomains: clockdomains {
 161                                 };
 162                         };
 163
 164                         omap4_scm_core: scm@2000 {
 165                                 compatible = "ti,omap4-scm-core", "simple-bus";
 166                                 reg = <0x2000 0x1000>;
 167                                 #address-cells = <1>;
 168                                 #size-cells = <1>;
 169                                 ranges = <0 0x2000 0x1000>;
 170
 171                                 scm_conf: scm_conf@0 {
 172                                         compatible = "syscon";
 173                                         reg = <0x0 0x800>;
 174                                         #address-cells = <1>;
 175                                         #size-cells = <1>;
 176                                 };
 177                         };
 178
 179                         omap4_padconf_core: scm@100000 {
 180                                 compatible = "ti,omap4-scm-padconf-core",
 181                                              "simple-bus";
 182                                 #address-cells = <1>;
 183                                 #size-cells = <1>;
 184                                 ranges = <0 0x100000 0x1000>;
 185
 186                                 omap4_pmx_core: pinmux@40 {
 187                                         compatible = "ti,omap4-padconf",
 188                                                      "pinctrl-single";
 189                                         reg = <0x40 0x0196>;
 190                                         #address-cells = <1>;
 191                                         #size-cells = <0>;
 192                                         #interrupt-cells = <1>;
 193                                         interrupt-controller;
 194                                         pinctrl-single,register-width = <16>;
 195                                         pinctrl-single,function-mask = <0x7fff>;
 196                                 };
 197
 198                                 omap4_padconf_global: omap4_padconf_global@5a0 {
 199                                         compatible = "syscon",
 200                                                      "simple-bus";
 201                                         reg = <0x5a0 0x170>;
 202                                         #address-cells = <1>;
 203                                         #size-cells = <1>;
 204                                         ranges = <0 0x5a0 0x170>;
 205
 206                                         pbias_regulator: pbias_regulator {
 207                                                 compatible = "ti,pbias-omap4", "ti,pbias-omap";
 208                                                 reg = <0x60 0x4>;
 209                                                 syscon = <&omap4_padconf_global>;
 210                                                 pbias_mmc_reg: pbias_mmc_omap4 {
 211                                                         regulator-name = "pbias_mmc_omap4";
 212                                                         regulator-min-microvolt = <1800000>;
 213                                                         regulator-max-microvolt = <3000000>;
 214                                                 };
 215                                         };
 216                                 };
 217                         };
 218
 219                         l4_wkup: l4@300000 {
 220                                 compatible = "ti,omap4-l4-wkup", "simple-bus";
 221                                 #address-cells = <1>;
 222                                 #size-cells = <1>;
 223                                 ranges = <0 0x300000 0x40000>;
 224
 225                                 counter32k: counter@4000 {
 226                                         compatible = "ti,omap-counter32k";
 227                                         reg = <0x4000 0x20>;
 228                                         ti,hwmods = "counter_32k";
 229                                 };
 230
 231                                 prm: prm@6000 {
 232                                         compatible = "ti,omap4-prm";
 233                                         reg = <0x6000 0x3000>;
 234                                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 235
 236                                         prm_clocks: clocks {
 237                                                 #address-cells = <1>;
 238                                                 #size-cells = <0>;
 239                                         };
 240
 241                                         prm_clockdomains: clockdomains {
 242                                         };
 243                                 };
 244
 245                                 scrm: scrm@a000 {
 246                                         compatible = "ti,omap4-scrm";
 247                                         reg = <0xa000 0x2000>;
 248
 249                                         scrm_clocks: clocks {
 250                                                 #address-cells = <1>;
 251                                                 #size-cells = <0>;
 252                                         };
 253
 254                                         scrm_clockdomains: clockdomains {
 255                                         };
 256                                 };
 257
 258                                 omap4_pmx_wkup: pinmux@1e040 {
 259                                         compatible = "ti,omap4-padconf",
 260                                                      "pinctrl-single";
 261                                         reg = <0x1e040 0x0038>;
 262                                         #address-cells = <1>;
 263                                         #size-cells = <0>;
 264                                         #interrupt-cells = <1>;
 265                                         interrupt-controller;
 266                                         pinctrl-single,register-width = <16>;
 267                                         pinctrl-single,function-mask = <0x7fff>;
 268                                 };
 269                         };
 270                 };
 271
 272                 ocmcram: ocmcram@40304000 {
 273                         compatible = "mmio-sram";
 274                         reg = <0x40304000 0xa000>; /* 40k */
 275                 };
 276
 277                 sdma: dma-controller@4a056000 {
 278                         compatible = "ti,omap4430-sdma";
 279                         reg = <0x4a056000 0x1000>;
 280                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         dma-channels = <32>;
 286                         dma-requests = <127>;
 287                 };
 288
 289                 gpio1: gpio@4a310000 {
 290                         compatible = "ti,omap4-gpio";
 291                         reg = <0x4a310000 0x200>;
 292                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 293                         ti,hwmods = "gpio1";
 294                         ti,gpio-always-on;
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio2: gpio@48055000 {
 302                         compatible = "ti,omap4-gpio";
 303                         reg = <0x48055000 0x200>;
 304                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 305                         ti,hwmods = "gpio2";
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311
 312                 gpio3: gpio@48057000 {
 313                         compatible = "ti,omap4-gpio";
 314                         reg = <0x48057000 0x200>;
 315                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "gpio3";
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                 };
 322
 323                 gpio4: gpio@48059000 {
 324                         compatible = "ti,omap4-gpio";
 325                         reg = <0x48059000 0x200>;
 326                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 327                         ti,hwmods = "gpio4";
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                 };
 333
 334                 gpio5: gpio@4805b000 {
 335                         compatible = "ti,omap4-gpio";
 336                         reg = <0x4805b000 0x200>;
 337                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 338                         ti,hwmods = "gpio5";
 339                         gpio-controller;
 340                         #gpio-cells = <2>;
 341                         interrupt-controller;
 342                         #interrupt-cells = <2>;
 343                 };
 344
 345                 gpio6: gpio@4805d000 {
 346                         compatible = "ti,omap4-gpio";
 347                         reg = <0x4805d000 0x200>;
 348                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 349                         ti,hwmods = "gpio6";
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                         interrupt-controller;
 353                         #interrupt-cells = <2>;
 354                 };
 355
 356                 gpmc: gpmc@50000000 {
 357                         compatible = "ti,omap4430-gpmc";
 358                         reg = <0x50000000 0x1000>;
 359                         #address-cells = <2>;
 360                         #size-cells = <1>;
 361                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 362                         gpmc,num-cs = <8>;
 363                         gpmc,num-waitpins = <4>;
 364                         ti,hwmods = "gpmc";
 365                         ti,no-idle-on-init;
 366                         clocks = <&l3_div_ck>;
 367                         clock-names = "fck";
 368                 };
 369
 370                 uart1: serial@4806a000 {
 371                         compatible = "ti,omap4-uart";
 372                         reg = <0x4806a000 0x100>;
 373                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 374                         ti,hwmods = "uart1";
 375                         clock-frequency = <48000000>;
 376                 };
 377
 378                 uart2: serial@4806c000 {
 379                         compatible = "ti,omap4-uart";
 380                         reg = <0x4806c000 0x100>;
 381                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 382                         ti,hwmods = "uart2";
 383                         clock-frequency = <48000000>;
 384                 };
 385
 386                 uart3: serial@48020000 {
 387                         compatible = "ti,omap4-uart";
 388                         reg = <0x48020000 0x100>;
 389                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "uart3";
 391                         clock-frequency = <48000000>;
 392                 };
 393
 394                 uart4: serial@4806e000 {
 395                         compatible = "ti,omap4-uart";
 396                         reg = <0x4806e000 0x100>;
 397                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 398                         ti,hwmods = "uart4";
 399                         clock-frequency = <48000000>;
 400                 };
 401
 402                 hwspinlock: spinlock@4a0f6000 {
 403                         compatible = "ti,omap4-hwspinlock";
 404                         reg = <0x4a0f6000 0x1000>;
 405                         ti,hwmods = "spinlock";
 406                         #hwlock-cells = <1>;
 407                 };
 408
 409                 i2c1: i2c@48070000 {
 410                         compatible = "ti,omap4-i2c";
 411                         reg = <0x48070000 0x100>;
 412                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         ti,hwmods = "i2c1";
 416                 };
 417
 418                 i2c2: i2c@48072000 {
 419                         compatible = "ti,omap4-i2c";
 420                         reg = <0x48072000 0x100>;
 421                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         ti,hwmods = "i2c2";
 425                 };
 426
 427                 i2c3: i2c@48060000 {
 428                         compatible = "ti,omap4-i2c";
 429                         reg = <0x48060000 0x100>;
 430                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         ti,hwmods = "i2c3";
 434                 };
 435
 436                 i2c4: i2c@48350000 {
 437                         compatible = "ti,omap4-i2c";
 438                         reg = <0x48350000 0x100>;
 439                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         ti,hwmods = "i2c4";
 443                 };
 444
 445                 mcspi1: spi@48098000 {
 446                         compatible = "ti,omap4-mcspi";
 447                         reg = <0x48098000 0x200>;
 448                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         ti,hwmods = "mcspi1";
 452                         ti,spi-num-cs = <4>;
 453                         dmas = <&sdma 35>,
 454                                <&sdma 36>,
 455                                <&sdma 37>,
 456                                <&sdma 38>,
 457                                <&sdma 39>,
 458                                <&sdma 40>,
 459                                <&sdma 41>,
 460                                <&sdma 42>;
 461                         dma-names = "tx0", "rx0", "tx1", "rx1",
 462                                     "tx2", "rx2", "tx3", "rx3";
 463                 };
 464
 465                 mcspi2: spi@4809a000 {
 466                         compatible = "ti,omap4-mcspi";
 467                         reg = <0x4809a000 0x200>;
 468                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         ti,hwmods = "mcspi2";
 472                         ti,spi-num-cs = <2>;
 473                         dmas = <&sdma 43>,
 474                                <&sdma 44>,
 475                                <&sdma 45>,
 476                                <&sdma 46>;
 477                         dma-names = "tx0", "rx0", "tx1", "rx1";
 478                 };
 479
 480                 mcspi3: spi@480b8000 {
 481                         compatible = "ti,omap4-mcspi";
 482                         reg = <0x480b8000 0x200>;
 483                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         ti,hwmods = "mcspi3";
 487                         ti,spi-num-cs = <2>;
 488                         dmas = <&sdma 15>, <&sdma 16>;
 489                         dma-names = "tx0", "rx0";
 490                 };
 491
 492                 mcspi4: spi@480ba000 {
 493                         compatible = "ti,omap4-mcspi";
 494                         reg = <0x480ba000 0x200>;
 495                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         ti,hwmods = "mcspi4";
 499                         ti,spi-num-cs = <1>;
 500                         dmas = <&sdma 70>, <&sdma 71>;
 501                         dma-names = "tx0", "rx0";
 502                 };
 503
 504                 mmc1: mmc@4809c000 {
 505                         compatible = "ti,omap4-hsmmc";
 506                         reg = <0x4809c000 0x400>;
 507                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 508                         ti,hwmods = "mmc1";
 509                         ti,dual-volt;
 510                         ti,needs-special-reset;
 511                         dmas = <&sdma 61>, <&sdma 62>;
 512                         dma-names = "tx", "rx";
 513                         pbias-supply = <&pbias_mmc_reg>;
 514                 };
 515
 516                 mmc2: mmc@480b4000 {
 517                         compatible = "ti,omap4-hsmmc";
 518                         reg = <0x480b4000 0x400>;
 519                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mmc2";
 521                         ti,needs-special-reset;
 522                         dmas = <&sdma 47>, <&sdma 48>;
 523                         dma-names = "tx", "rx";
 524                 };
 525
 526                 mmc3: mmc@480ad000 {
 527                         compatible = "ti,omap4-hsmmc";
 528                         reg = <0x480ad000 0x400>;
 529                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 530                         ti,hwmods = "mmc3";
 531                         ti,needs-special-reset;
 532                         dmas = <&sdma 77>, <&sdma 78>;
 533                         dma-names = "tx", "rx";
 534                 };
 535
 536                 mmc4: mmc@480d1000 {
 537                         compatible = "ti,omap4-hsmmc";
 538                         reg = <0x480d1000 0x400>;
 539                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 540                         ti,hwmods = "mmc4";
 541                         ti,needs-special-reset;
 542                         dmas = <&sdma 57>, <&sdma 58>;
 543                         dma-names = "tx", "rx";
 544                 };
 545
 546                 mmc5: mmc@480d5000 {
 547                         compatible = "ti,omap4-hsmmc";
 548                         reg = <0x480d5000 0x400>;
 549                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 550                         ti,hwmods = "mmc5";
 551                         ti,needs-special-reset;
 552                         dmas = <&sdma 59>, <&sdma 60>;
 553                         dma-names = "tx", "rx";
 554                 };
 555
 556                 mmu_dsp: mmu@4a066000 {
 557                         compatible = "ti,omap4-iommu";
 558                         reg = <0x4a066000 0x100>;
 559                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 560                         ti,hwmods = "mmu_dsp";
 561                         #iommu-cells = <0>;
 562                 };
 563
 564                 mmu_ipu: mmu@55082000 {
 565                         compatible = "ti,omap4-iommu";
 566                         reg = <0x55082000 0x100>;
 567                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 568                         ti,hwmods = "mmu_ipu";
 569                         #iommu-cells = <0>;
 570                         ti,iommu-bus-err-back;
 571                 };
 572
 573                 wdt2: wdt@4a314000 {
 574                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 575                         reg = <0x4a314000 0x80>;
 576                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 577                         ti,hwmods = "wd_timer2";
 578                 };
 579
 580                 mcpdm: mcpdm@40132000 {
 581                         compatible = "ti,omap4-mcpdm";
 582                         reg = <0x40132000 0x7f>, /* MPU private access */
 583                               <0x49032000 0x7f>; /* L3 Interconnect */
 584                         reg-names = "mpu", "dma";
 585                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 586                         ti,hwmods = "mcpdm";
 587                         dmas = <&sdma 65>,
 588                                <&sdma 66>;
 589                         dma-names = "up_link", "dn_link";
 590                         status = "disabled";
 591                 };
 592
 593                 dmic: dmic@4012e000 {
 594                         compatible = "ti,omap4-dmic";
 595                         reg = <0x4012e000 0x7f>, /* MPU private access */
 596                               <0x4902e000 0x7f>; /* L3 Interconnect */
 597                         reg-names = "mpu", "dma";
 598                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 599                         ti,hwmods = "dmic";
 600                         dmas = <&sdma 67>;
 601                         dma-names = "up_link";
 602                         status = "disabled";
 603                 };
 604
 605                 mcbsp1: mcbsp@40122000 {
 606                         compatible = "ti,omap4-mcbsp";
 607                         reg = <0x40122000 0xff>, /* MPU private access */
 608                               <0x49022000 0xff>; /* L3 Interconnect */
 609                         reg-names = "mpu", "dma";
 610                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 611                         interrupt-names = "common";
 612                         ti,buffer-size = <128>;
 613                         ti,hwmods = "mcbsp1";
 614                         dmas = <&sdma 33>,
 615                                <&sdma 34>;
 616                         dma-names = "tx", "rx";
 617                         status = "disabled";
 618                 };
 619
 620                 mcbsp2: mcbsp@40124000 {
 621                         compatible = "ti,omap4-mcbsp";
 622                         reg = <0x40124000 0xff>, /* MPU private access */
 623                               <0x49024000 0xff>; /* L3 Interconnect */
 624                         reg-names = "mpu", "dma";
 625                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 626                         interrupt-names = "common";
 627                         ti,buffer-size = <128>;
 628                         ti,hwmods = "mcbsp2";
 629                         dmas = <&sdma 17>,
 630                                <&sdma 18>;
 631                         dma-names = "tx", "rx";
 632                         status = "disabled";
 633                 };
 634
 635                 mcbsp3: mcbsp@40126000 {
 636                         compatible = "ti,omap4-mcbsp";
 637                         reg = <0x40126000 0xff>, /* MPU private access */
 638                               <0x49026000 0xff>; /* L3 Interconnect */
 639                         reg-names = "mpu", "dma";
 640                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 641                         interrupt-names = "common";
 642                         ti,buffer-size = <128>;
 643                         ti,hwmods = "mcbsp3";
 644                         dmas = <&sdma 19>,
 645                                <&sdma 20>;
 646                         dma-names = "tx", "rx";
 647                         status = "disabled";
 648                 };
 649
 650                 mcbsp4: mcbsp@48096000 {
 651                         compatible = "ti,omap4-mcbsp";
 652                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 653                         reg-names = "mpu";
 654                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 655                         interrupt-names = "common";
 656                         ti,buffer-size = <128>;
 657                         ti,hwmods = "mcbsp4";
 658                         dmas = <&sdma 31>,
 659                                <&sdma 32>;
 660                         dma-names = "tx", "rx";
 661                         status = "disabled";
 662                 };
 663
 664                 keypad: keypad@4a31c000 {
 665                         compatible = "ti,omap4-keypad";
 666                         reg = <0x4a31c000 0x80>;
 667                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 668                         reg-names = "mpu";
 669                         ti,hwmods = "kbd";
 670                 };
 671
 672                 dmm@4e000000 {
 673                         compatible = "ti,omap4-dmm";
 674                         reg = <0x4e000000 0x800>;
 675                         interrupts = <0 113 0x4>;
 676                         ti,hwmods = "dmm";
 677                 };
 678
 679                 emif1: emif@4c000000 {
 680                         compatible = "ti,emif-4d";
 681                         reg = <0x4c000000 0x100>;
 682                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 683                         ti,hwmods = "emif1";
 684                         ti,no-idle-on-init;
 685                         phy-type = <1>;
 686                         hw-caps-read-idle-ctrl;
 687                         hw-caps-ll-interface;
 688                         hw-caps-temp-alert;
 689                 };
 690
 691                 emif2: emif@4d000000 {
 692                         compatible = "ti,emif-4d";
 693                         reg = <0x4d000000 0x100>;
 694                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 695                         ti,hwmods = "emif2";
 696                         ti,no-idle-on-init;
 697                         phy-type = <1>;
 698                         hw-caps-read-idle-ctrl;
 699                         hw-caps-ll-interface;
 700                         hw-caps-temp-alert;
 701                 };
 702
 703                 ocp2scp@4a0ad000 {
 704                         compatible = "ti,omap-ocp2scp";
 705                         reg = <0x4a0ad000 0x1f>;
 706                         #address-cells = <1>;
 707                         #size-cells = <1>;
 708                         ranges;
 709                         ti,hwmods = "ocp2scp_usb_phy";
 710                         usb2_phy: usb2phy@4a0ad080 {
 711                                 compatible = "ti,omap-usb2";
 712                                 reg = <0x4a0ad080 0x58>;
 713                                 ctrl-module = <&omap_control_usb2phy>;
 714                                 clocks = <&usb_phy_cm_clk32k>;
 715                                 clock-names = "wkupclk";
 716                                 #phy-cells = <0>;
 717                         };
 718                 };
 719
 720                 mailbox: mailbox@4a0f4000 {
 721                         compatible = "ti,omap4-mailbox";
 722                         reg = <0x4a0f4000 0x200>;
 723                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 724                         ti,hwmods = "mailbox";
 725                         #mbox-cells = <1>;
 726                         ti,mbox-num-users = <3>;
 727                         ti,mbox-num-fifos = <8>;
 728                         mbox_ipu: mbox_ipu {
 729                                 ti,mbox-tx = <0 0 0>;
 730                                 ti,mbox-rx = <1 0 0>;
 731                         };
 732                         mbox_dsp: mbox_dsp {
 733                                 ti,mbox-tx = <3 0 0>;
 734                                 ti,mbox-rx = <2 0 0>;
 735                         };
 736                 };
 737
 738                 timer1: timer@4a318000 {
 739                         compatible = "ti,omap3430-timer";
 740                         reg = <0x4a318000 0x80>;
 741                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 742                         ti,hwmods = "timer1";
 743                         ti,timer-alwon;
 744                 };
 745
 746                 timer2: timer@48032000 {
 747                         compatible = "ti,omap3430-timer";
 748                         reg = <0x48032000 0x80>;
 749                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 750                         ti,hwmods = "timer2";
 751                 };
 752
 753                 timer3: timer@48034000 {
 754                         compatible = "ti,omap4430-timer";
 755                         reg = <0x48034000 0x80>;
 756                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 757                         ti,hwmods = "timer3";
 758                 };
 759
 760                 timer4: timer@48036000 {
 761                         compatible = "ti,omap4430-timer";
 762                         reg = <0x48036000 0x80>;
 763                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 764                         ti,hwmods = "timer4";
 765                 };
 766
 767                 timer5: timer@40138000 {
 768                         compatible = "ti,omap4430-timer";
 769                         reg = <0x40138000 0x80>,
 770                               <0x49038000 0x80>;
 771                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 772                         ti,hwmods = "timer5";
 773                         ti,timer-dsp;
 774                 };
 775
 776                 timer6: timer@4013a000 {
 777                         compatible = "ti,omap4430-timer";
 778                         reg = <0x4013a000 0x80>,
 779                               <0x4903a000 0x80>;
 780                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 781                         ti,hwmods = "timer6";
 782                         ti,timer-dsp;
 783                 };
 784
 785                 timer7: timer@4013c000 {
 786                         compatible = "ti,omap4430-timer";
 787                         reg = <0x4013c000 0x80>,
 788                               <0x4903c000 0x80>;
 789                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "timer7";
 791                         ti,timer-dsp;
 792                 };
 793
 794                 timer8: timer@4013e000 {
 795                         compatible = "ti,omap4430-timer";
 796                         reg = <0x4013e000 0x80>,
 797                               <0x4903e000 0x80>;
 798                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 799                         ti,hwmods = "timer8";
 800                         ti,timer-pwm;
 801                         ti,timer-dsp;
 802                 };
 803
 804                 timer9: timer@4803e000 {
 805                         compatible = "ti,omap4430-timer";
 806                         reg = <0x4803e000 0x80>;
 807                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 808                         ti,hwmods = "timer9";
 809                         ti,timer-pwm;
 810                 };
 811
 812                 timer10: timer@48086000 {
 813                         compatible = "ti,omap3430-timer";
 814                         reg = <0x48086000 0x80>;
 815                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 816                         ti,hwmods = "timer10";
 817                         ti,timer-pwm;
 818                 };
 819
 820                 timer11: timer@48088000 {
 821                         compatible = "ti,omap4430-timer";
 822                         reg = <0x48088000 0x80>;
 823                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 824                         ti,hwmods = "timer11";
 825                         ti,timer-pwm;
 826                 };
 827
 828                 usbhstll: usbhstll@4a062000 {
 829                         compatible = "ti,usbhs-tll";
 830                         reg = <0x4a062000 0x1000>;
 831                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 832                         ti,hwmods = "usb_tll_hs";
 833                 };
 834
 835                 usbhshost: usbhshost@4a064000 {
 836                         compatible = "ti,usbhs-host";
 837                         reg = <0x4a064000 0x800>;
 838                         ti,hwmods = "usb_host_hs";
 839                         #address-cells = <1>;
 840                         #size-cells = <1>;
 841                         ranges;
 842                         clocks = <&init_60m_fclk>,
 843                                  <&xclk60mhsp1_ck>,
 844                                  <&xclk60mhsp2_ck>;
 845                         clock-names = "refclk_60m_int",
 846                                       "refclk_60m_ext_p1",
 847                                       "refclk_60m_ext_p2";
 848
 849                         usbhsohci: ohci@4a064800 {
 850                                 compatible = "ti,ohci-omap3";
 851                                 reg = <0x4a064800 0x400>;
 852                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 853                         };
 854
 855                         usbhsehci: ehci@4a064c00 {
 856                                 compatible = "ti,ehci-omap";
 857                                 reg = <0x4a064c00 0x400>;
 858                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 859                         };
 860                 };
 861
 862                 omap_control_usb2phy: control-phy@4a002300 {
 863                         compatible = "ti,control-phy-usb2";
 864                         reg = <0x4a002300 0x4>;
 865                         reg-names = "power";
 866                 };
 867
 868                 omap_control_usbotg: control-phy@4a00233c {
 869                         compatible = "ti,control-phy-otghs";
 870                         reg = <0x4a00233c 0x4>;
 871                         reg-names = "otghs_control";
 872                 };
 873
 874                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 875                         compatible = "ti,omap4-musb";
 876                         reg = <0x4a0ab000 0x7ff>;
 877                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 878                         interrupt-names = "mc", "dma";
 879                         ti,hwmods = "usb_otg_hs";
 880                         usb-phy = <&usb2_phy>;
 881                         phys = <&usb2_phy>;
 882                         phy-names = "usb2-phy";
 883                         multipoint = <1>;
 884                         num-eps = <16>;
 885                         ram-bits = <12>;
 886                         ctrl-module = <&omap_control_usbotg>;
 887                 };
 888
 889                 aes: aes@4b501000 {
 890                         compatible = "ti,omap4-aes";
 891                         ti,hwmods = "aes";
 892                         reg = <0x4b501000 0xa0>;
 893                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 894                         dmas = <&sdma 111>, <&sdma 110>;
 895                         dma-names = "tx", "rx";
 896                 };
 897
 898                 des: des@480a5000 {
 899                         compatible = "ti,omap4-des";
 900                         ti,hwmods = "des";
 901                         reg = <0x480a5000 0xa0>;
 902                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 903                         dmas = <&sdma 117>, <&sdma 116>;
 904                         dma-names = "tx", "rx";
 905                 };
 906
 907                 abb_mpu: regulator-abb-mpu {
 908                         compatible = "ti,abb-v2";
 909                         regulator-name = "abb_mpu";
 910                         #address-cells = <0>;
 911                         #size-cells = <0>;
 912                         ti,tranxdone-status-mask = <0x80>;
 913                         clocks = <&sys_clkin_ck>;
 914                         ti,settling-time = <50>;
 915                         ti,clock-cycles = <16>;
 916
 917                         status = "disabled";
 918                 };
 919
 920                 abb_iva: regulator-abb-iva {
 921                         compatible = "ti,abb-v2";
 922                         regulator-name = "abb_iva";
 923                         #address-cells = <0>;
 924                         #size-cells = <0>;
 925                         ti,tranxdone-status-mask = <0x80000000>;
 926                         clocks = <&sys_clkin_ck>;
 927                         ti,settling-time = <50>;
 928                         ti,clock-cycles = <16>;
 929
 930                         status = "disabled";
 931                 };
 932
 933                 dss: dss@58000000 {
 934                         compatible = "ti,omap4-dss";
 935                         reg = <0x58000000 0x80>;
 936                         status = "disabled";
 937                         ti,hwmods = "dss_core";
 938                         clocks = <&dss_dss_clk>;
 939                         clock-names = "fck";
 940                         #address-cells = <1>;
 941                         #size-cells = <1>;
 942                         ranges;
 943
 944                         dispc@58001000 {
 945                                 compatible = "ti,omap4-dispc";
 946                                 reg = <0x58001000 0x1000>;
 947                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 948                                 ti,hwmods = "dss_dispc";
 949                                 clocks = <&dss_dss_clk>;
 950                                 clock-names = "fck";
 951                         };
 952
 953                         rfbi: encoder@58002000  {
 954                                 compatible = "ti,omap4-rfbi";
 955                                 reg = <0x58002000 0x1000>;
 956                                 status = "disabled";
 957                                 ti,hwmods = "dss_rfbi";
 958                                 clocks = <&dss_dss_clk>, <&l3_div_ck>;
 959                                 clock-names = "fck", "ick";
 960                         };
 961
 962                         venc: encoder@58003000 {
 963                                 compatible = "ti,omap4-venc";
 964                                 reg = <0x58003000 0x1000>;
 965                                 status = "disabled";
 966                                 ti,hwmods = "dss_venc";
 967                                 clocks = <&dss_tv_clk>;
 968                                 clock-names = "fck";
 969                         };
 970
 971                         dsi1: encoder@58004000 {
 972                                 compatible = "ti,omap4-dsi";
 973                                 reg = <0x58004000 0x200>,
 974                                       <0x58004200 0x40>,
 975                                       <0x58004300 0x20>;
 976                                 reg-names = "proto", "phy", "pll";
 977                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 978                                 status = "disabled";
 979                                 ti,hwmods = "dss_dsi1";
 980                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 981                                 clock-names = "fck", "sys_clk";
 982                         };
 983
 984                         dsi2: encoder@58005000 {
 985                                 compatible = "ti,omap4-dsi";
 986                                 reg = <0x58005000 0x200>,
 987                                       <0x58005200 0x40>,
 988                                       <0x58005300 0x20>;
 989                                 reg-names = "proto", "phy", "pll";
 990                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 991                                 status = "disabled";
 992                                 ti,hwmods = "dss_dsi2";
 993                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 994                                 clock-names = "fck", "sys_clk";
 995                         };
 996
 997                         hdmi: encoder@58006000 {
 998                                 compatible = "ti,omap4-hdmi";
 999                                 reg = <0x58006000 0x200>,
1000                                       <0x58006200 0x100>,
1001                                       <0x58006300 0x100>,
1002                                       <0x58006400 0x1000>;
1003                                 reg-names = "wp", "pll", "phy", "core";
1004                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1005                                 status = "disabled";
1006                                 ti,hwmods = "dss_hdmi";
1007                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1008                                 clock-names = "fck", "sys_clk";
1009                                 dmas = <&sdma 76>;
1010                                 dma-names = "audio_tx";
1011                         };
1012                 };
1013         };
1014 };
1015
1016 /include/ "omap44xx-clocks.dtsi"