1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MIPI Display Bus Interface (DBI) LCD controller support
5 * Copyright 2016 Noralf Trønnes
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/module.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/spi/spi.h>
15 #include <drm/drm_connector.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_file.h>
19 #include <drm/drm_format_helper.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_mipi_dbi.h>
24 #include <drm/drm_modes.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_rect.h>
27 #include <video/mipi_display.h>
29 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
31 #define DCS_POWER_MODE_DISPLAY BIT(2)
32 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
33 #define DCS_POWER_MODE_SLEEP_MODE BIT(4)
34 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
35 #define DCS_POWER_MODE_IDLE_MODE BIT(6)
36 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
41 * This library provides helpers for MIPI Display Bus Interface (DBI)
42 * compatible display controllers.
44 * Many controllers for tiny lcd displays are MIPI compliant and can use this
45 * library. If a controller uses registers 0x2A and 0x2B to set the area to
46 * update and uses register 0x2C to write to frame memory, it is most likely
49 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
51 * There are 3 MIPI DBI implementation types:
53 * A. Motorola 6800 type parallel bus
55 * B. Intel 8080 type parallel bus
57 * C. SPI type with 3 options:
59 * 1. 9-bit with the Data/Command signal as the ninth bit
60 * 2. Same as above except it's sent as 16 bits
61 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
63 * Currently mipi_dbi only supports Type C options 1 and 3 with
64 * mipi_dbi_spi_init().
67 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
77 static const u8 mipi_dbi_dcs_read_commands[] = {
78 MIPI_DCS_GET_DISPLAY_ID,
79 MIPI_DCS_GET_RED_CHANNEL,
80 MIPI_DCS_GET_GREEN_CHANNEL,
81 MIPI_DCS_GET_BLUE_CHANNEL,
82 MIPI_DCS_GET_DISPLAY_STATUS,
83 MIPI_DCS_GET_POWER_MODE,
84 MIPI_DCS_GET_ADDRESS_MODE,
85 MIPI_DCS_GET_PIXEL_FORMAT,
86 MIPI_DCS_GET_DISPLAY_MODE,
87 MIPI_DCS_GET_SIGNAL_MODE,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 MIPI_DCS_READ_MEMORY_START,
90 MIPI_DCS_READ_MEMORY_CONTINUE,
91 MIPI_DCS_GET_SCANLINE,
92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 MIPI_DCS_GET_CONTROL_DISPLAY,
94 MIPI_DCS_GET_POWER_SAVE,
95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 MIPI_DCS_READ_DDB_START,
97 MIPI_DCS_READ_DDB_CONTINUE,
101 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
105 if (!dbi->read_commands)
108 for (i = 0; i < 0xff; i++) {
109 if (!dbi->read_commands[i])
111 if (cmd == dbi->read_commands[i])
119 * mipi_dbi_command_read - MIPI DCS read command
120 * @dbi: MIPI DBI structure
124 * Send MIPI DCS read command to the controller.
127 * Zero on success, negative error code on failure.
129 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
131 if (!dbi->read_commands)
134 if (!mipi_dbi_command_is_read(dbi, cmd))
137 return mipi_dbi_command_buf(dbi, cmd, val, 1);
139 EXPORT_SYMBOL(mipi_dbi_command_read);
142 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
143 * @dbi: MIPI DBI structure
145 * @data: Parameter buffer
146 * @len: Buffer length
149 * Zero on success, negative error code on failure.
151 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
156 /* SPI requires dma-safe buffers */
157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
161 mutex_lock(&dbi->cmdlock);
162 ret = dbi->command(dbi, cmdbuf, data, len);
163 mutex_unlock(&dbi->cmdlock);
169 EXPORT_SYMBOL(mipi_dbi_command_buf);
171 /* This should only be used by mipi_dbi_command() */
172 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
178 buf = kmemdup(data, len, GFP_KERNEL);
182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
188 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
191 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
192 * @dst: The destination buffer
193 * @fb: The source framebuffer
194 * @clip: Clipping rectangle of the area to be copied
195 * @swap: When true, swap MSB/LSB of 16-bit values
198 * Zero on success, negative error code on failure.
200 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
201 struct drm_rect *clip, bool swap)
203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204 struct iosys_map map[DRM_FORMAT_MAX_PLANES];
205 struct iosys_map data[DRM_FORMAT_MAX_PLANES];
209 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
213 ret = drm_gem_fb_vmap(fb, map, data);
215 goto out_drm_gem_fb_end_cpu_access;
216 src = data[0].vaddr; /* TODO: Use mapping abstraction properly */
218 switch (fb->format->format) {
219 case DRM_FORMAT_RGB565:
221 drm_fb_swab(dst, 0, src, fb, clip, !gem->import_attach);
223 drm_fb_memcpy(dst, 0, src, fb, clip);
225 case DRM_FORMAT_XRGB8888:
226 drm_fb_xrgb8888_to_rgb565(dst, 0, src, fb, clip, swap);
229 drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
230 &fb->format->format);
234 drm_gem_fb_vunmap(fb, map);
235 out_drm_gem_fb_end_cpu_access:
236 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
240 EXPORT_SYMBOL(mipi_dbi_buf_copy);
242 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
243 unsigned int xs, unsigned int xe,
244 unsigned int ys, unsigned int ye)
246 struct mipi_dbi *dbi = &dbidev->dbi;
248 xs += dbidev->left_offset;
249 xe += dbidev->left_offset;
250 ys += dbidev->top_offset;
251 ye += dbidev->top_offset;
253 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
254 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
255 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
256 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
259 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
261 struct iosys_map map[DRM_FORMAT_MAX_PLANES];
262 struct iosys_map data[DRM_FORMAT_MAX_PLANES];
263 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
264 unsigned int height = rect->y2 - rect->y1;
265 unsigned int width = rect->x2 - rect->x1;
266 struct mipi_dbi *dbi = &dbidev->dbi;
267 bool swap = dbi->swap_bytes;
275 if (!drm_dev_enter(fb->dev, &idx))
278 ret = drm_gem_fb_vmap(fb, map, data);
280 goto err_drm_dev_exit;
282 full = width == fb->width && height == fb->height;
284 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
286 if (!dbi->dc || !full || swap ||
287 fb->format->format == DRM_FORMAT_XRGB8888) {
289 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
293 tr = data[0].vaddr; /* TODO: Use mapping abstraction properly */
296 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
299 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
303 drm_err_once(fb->dev, "Failed to update display %d\n", ret);
305 drm_gem_fb_vunmap(fb, map);
312 * mipi_dbi_pipe_update - Display pipe update helper
313 * @pipe: Simple display pipe
314 * @old_state: Old plane state
316 * This function handles framebuffer flushing and vblank events. Drivers can use
317 * this as their &drm_simple_display_pipe_funcs->update callback.
319 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
320 struct drm_plane_state *old_state)
322 struct drm_plane_state *state = pipe->plane.state;
323 struct drm_rect rect;
325 if (!pipe->crtc.state->active)
328 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
329 mipi_dbi_fb_dirty(state->fb, &rect);
331 EXPORT_SYMBOL(mipi_dbi_pipe_update);
334 * mipi_dbi_enable_flush - MIPI DBI enable helper
335 * @dbidev: MIPI DBI device structure
336 * @crtc_state: CRTC state
337 * @plane_state: Plane state
339 * Flushes the whole framebuffer and enables the backlight. Drivers can use this
340 * in their &drm_simple_display_pipe_funcs->enable callback.
342 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
343 * framebuffer flushing, can't use this function since they both use the same
346 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
347 struct drm_crtc_state *crtc_state,
348 struct drm_plane_state *plane_state)
350 struct drm_framebuffer *fb = plane_state->fb;
351 struct drm_rect rect = {
359 if (!drm_dev_enter(&dbidev->drm, &idx))
362 mipi_dbi_fb_dirty(fb, &rect);
363 backlight_enable(dbidev->backlight);
367 EXPORT_SYMBOL(mipi_dbi_enable_flush);
369 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
371 struct drm_device *drm = &dbidev->drm;
372 u16 height = drm->mode_config.min_height;
373 u16 width = drm->mode_config.min_width;
374 struct mipi_dbi *dbi = &dbidev->dbi;
375 size_t len = width * height * 2;
378 if (!drm_dev_enter(drm, &idx))
381 memset(dbidev->tx_buf, 0, len);
383 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
384 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
385 (u8 *)dbidev->tx_buf, len);
391 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
392 * @pipe: Display pipe
394 * This function disables backlight if present, if not the display memory is
395 * blanked. The regulator is disabled if in use. Drivers can use this as their
396 * &drm_simple_display_pipe_funcs->disable callback.
398 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
400 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
404 if (dbidev->backlight)
405 backlight_disable(dbidev->backlight);
407 mipi_dbi_blank(dbidev);
409 if (dbidev->regulator)
410 regulator_disable(dbidev->regulator);
412 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
414 static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
416 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
417 struct drm_display_mode *mode;
419 mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
421 DRM_ERROR("Failed to duplicate mode\n");
425 if (mode->name[0] == '\0')
426 drm_mode_set_name(mode);
428 mode->type |= DRM_MODE_TYPE_PREFERRED;
429 drm_mode_probed_add(connector, mode);
431 if (mode->width_mm) {
432 connector->display_info.width_mm = mode->width_mm;
433 connector->display_info.height_mm = mode->height_mm;
439 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
440 .get_modes = mipi_dbi_connector_get_modes,
443 static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
444 .reset = drm_atomic_helper_connector_reset,
445 .fill_modes = drm_helper_probe_single_connector_modes,
446 .destroy = drm_connector_cleanup,
447 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
448 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
451 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
452 unsigned int rotation)
454 if (rotation == 0 || rotation == 180) {
456 } else if (rotation == 90 || rotation == 270) {
457 swap(mode->hdisplay, mode->vdisplay);
458 swap(mode->hsync_start, mode->vsync_start);
459 swap(mode->hsync_end, mode->vsync_end);
460 swap(mode->htotal, mode->vtotal);
461 swap(mode->width_mm, mode->height_mm);
468 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
469 .fb_create = drm_gem_fb_create_with_dirty,
470 .atomic_check = drm_atomic_helper_check,
471 .atomic_commit = drm_atomic_helper_commit,
474 static const uint32_t mipi_dbi_formats[] = {
480 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
481 * @dbidev: MIPI DBI device structure to initialize
482 * @funcs: Display pipe functions
483 * @formats: Array of supported formats (DRM_FORMAT\_\*).
484 * @format_count: Number of elements in @formats
485 * @mode: Display mode
486 * @rotation: Initial rotation in degrees Counter Clock Wise
487 * @tx_buf_size: Allocate a transmit buffer of this size.
489 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
490 * has one fixed &drm_display_mode which is rotated according to @rotation.
491 * This mode is used to set the mode config min/max width/height properties.
493 * Use mipi_dbi_dev_init() if you don't need custom formats.
496 * Some of the helper functions expects RGB565 to be the default format and the
497 * transmit buffer sized to fit that.
500 * Zero on success, negative error code on failure.
502 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
503 const struct drm_simple_display_pipe_funcs *funcs,
504 const uint32_t *formats, unsigned int format_count,
505 const struct drm_display_mode *mode,
506 unsigned int rotation, size_t tx_buf_size)
508 static const uint64_t modifiers[] = {
509 DRM_FORMAT_MOD_LINEAR,
510 DRM_FORMAT_MOD_INVALID
512 struct drm_device *drm = &dbidev->drm;
515 if (!dbidev->dbi.command)
518 ret = drmm_mode_config_init(drm);
522 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
526 drm_mode_copy(&dbidev->mode, mode);
527 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
529 DRM_ERROR("Illegal rotation value %u\n", rotation);
533 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
534 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
535 DRM_MODE_CONNECTOR_SPI);
539 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
540 modifiers, &dbidev->connector);
544 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
546 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
547 drm->mode_config.min_width = dbidev->mode.hdisplay;
548 drm->mode_config.max_width = dbidev->mode.hdisplay;
549 drm->mode_config.min_height = dbidev->mode.vdisplay;
550 drm->mode_config.max_height = dbidev->mode.vdisplay;
551 dbidev->rotation = rotation;
553 DRM_DEBUG_KMS("rotation = %u\n", rotation);
557 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
560 * mipi_dbi_dev_init - MIPI DBI device initialization
561 * @dbidev: MIPI DBI device structure to initialize
562 * @funcs: Display pipe functions
563 * @mode: Display mode
564 * @rotation: Initial rotation in degrees Counter Clock Wise
566 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
567 * has one fixed &drm_display_mode which is rotated according to @rotation.
568 * This mode is used to set the mode config min/max width/height properties.
569 * Additionally &mipi_dbi.tx_buf is allocated.
571 * Supported formats: Native RGB565 and emulated XRGB8888.
574 * Zero on success, negative error code on failure.
576 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
577 const struct drm_simple_display_pipe_funcs *funcs,
578 const struct drm_display_mode *mode, unsigned int rotation)
580 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
582 dbidev->drm.mode_config.preferred_depth = 16;
584 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
585 ARRAY_SIZE(mipi_dbi_formats), mode,
588 EXPORT_SYMBOL(mipi_dbi_dev_init);
591 * mipi_dbi_hw_reset - Hardware reset of controller
592 * @dbi: MIPI DBI structure
594 * Reset controller if the &mipi_dbi->reset gpio is set.
596 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
601 gpiod_set_value_cansleep(dbi->reset, 0);
602 usleep_range(20, 1000);
603 gpiod_set_value_cansleep(dbi->reset, 1);
606 EXPORT_SYMBOL(mipi_dbi_hw_reset);
609 * mipi_dbi_display_is_on - Check if display is on
610 * @dbi: MIPI DBI structure
612 * This function checks the Power Mode register (if readable) to see if
613 * display output is turned on. This can be used to see if the bootloader
614 * has already turned on the display avoiding flicker when the pipeline is
618 * true if the display can be verified to be on, false otherwise.
620 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
624 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
627 val &= ~DCS_POWER_MODE_RESERVED_MASK;
629 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
630 if (val != (DCS_POWER_MODE_DISPLAY |
631 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
634 DRM_DEBUG_DRIVER("Display is ON\n");
638 EXPORT_SYMBOL(mipi_dbi_display_is_on);
640 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
642 struct device *dev = dbidev->drm.dev;
643 struct mipi_dbi *dbi = &dbidev->dbi;
646 if (dbidev->regulator) {
647 ret = regulator_enable(dbidev->regulator);
649 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
654 if (cond && mipi_dbi_display_is_on(dbi))
657 mipi_dbi_hw_reset(dbi);
658 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
660 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
661 if (dbidev->regulator)
662 regulator_disable(dbidev->regulator);
667 * If we did a hw reset, we know the controller is in Sleep mode and
668 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
669 * we assume worst case and wait 120ms.
672 usleep_range(5000, 20000);
680 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
681 * @dbidev: MIPI DBI device structure
683 * This function enables the regulator if used and does a hardware and software
687 * Zero on success, or a negative error code.
689 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
691 return mipi_dbi_poweron_reset_conditional(dbidev, false);
693 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
696 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
697 * @dbidev: MIPI DBI device structure
699 * This function enables the regulator if used and if the display is off, it
700 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
701 * that the display is on, no reset is performed.
704 * Zero if the controller was reset, 1 if the display was already on, or a
705 * negative error code.
707 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
709 return mipi_dbi_poweron_reset_conditional(dbidev, true);
711 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
713 #if IS_ENABLED(CONFIG_SPI)
716 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
718 * @len: The transfer buffer length.
720 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
721 * that. Increase reliability by running pixel data at max speed and the rest
722 * at 10MHz, preventing transfer glitches from messing up the init settings.
724 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
727 return 0; /* use default */
729 return min_t(u32, 10000000, spi->max_speed_hz);
731 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
733 static bool mipi_dbi_machine_little_endian(void)
735 #if defined(__LITTLE_ENDIAN)
743 * MIPI DBI Type C Option 1
745 * If the SPI controller doesn't have 9 bits per word support,
746 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
747 * Pad partial blocks with MIPI_DCS_NOP (zero).
748 * This is how the D/C bit (x) is added:
760 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
761 const void *buf, size_t len,
764 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
765 size_t chunk, max_chunk = dbi->tx_buf9_len;
766 struct spi_device *spi = dbi->spi;
767 struct spi_transfer tr = {
768 .tx_buf = dbi->tx_buf9,
771 struct spi_message m;
776 if (drm_debug_enabled(DRM_UT_DRIVER))
777 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
778 __func__, dc, max_chunk);
780 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
781 spi_message_init_with_transfers(&m, &tr, 1);
784 if (WARN_ON_ONCE(len != 1))
787 /* Command: pad no-op's (zeroes) at beginning of block */
793 return spi_sync(spi, &m);
796 /* max with room for adding one bit per byte */
797 max_chunk = max_chunk / 9 * 8;
798 /* but no bigger than len */
799 max_chunk = min(max_chunk, len);
801 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
806 chunk = min(len, max_chunk);
813 /* Data: pad no-op's (zeroes) at end of block */
817 for (i = 1; i < (chunk + 1); i++) {
819 *dst++ = carry | BIT(8 - i) | (val >> i);
820 carry = val << (8 - i);
823 *dst++ = carry | BIT(8 - i) | (val >> i);
824 carry = val << (8 - i);
829 for (i = 1; i < (chunk + 1); i++) {
831 *dst++ = carry | BIT(8 - i) | (val >> i);
832 carry = val << (8 - i);
840 for (i = 0; i < chunk; i += 8) {
842 *dst++ = BIT(7) | (src[1] >> 1);
843 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
844 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
845 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
846 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
847 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
848 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
849 *dst++ = (src[7] << 1) | BIT(0);
852 *dst++ = BIT(7) | (src[0] >> 1);
853 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
854 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
855 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
856 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
857 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
858 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
859 *dst++ = (src[6] << 1) | BIT(0);
868 tr.len = chunk + added;
870 ret = spi_sync(spi, &m);
878 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
879 const void *buf, size_t len,
882 struct spi_device *spi = dbi->spi;
883 struct spi_transfer tr = {
886 const u16 *src16 = buf;
887 const u8 *src8 = buf;
888 struct spi_message m;
893 if (!spi_is_bpw_supported(spi, 9))
894 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
896 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
897 max_chunk = dbi->tx_buf9_len;
898 dst16 = dbi->tx_buf9;
900 if (drm_debug_enabled(DRM_UT_DRIVER))
901 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
902 __func__, dc, max_chunk);
904 max_chunk = min(max_chunk / 2, len);
906 spi_message_init_with_transfers(&m, &tr, 1);
910 size_t chunk = min(len, max_chunk);
913 if (bpw == 16 && mipi_dbi_machine_little_endian()) {
914 for (i = 0; i < (chunk * 2); i += 2) {
915 dst16[i] = *src16 >> 8;
916 dst16[i + 1] = *src16++ & 0xFF;
919 dst16[i + 1] |= 0x0100;
923 for (i = 0; i < chunk; i++) {
933 ret = spi_sync(spi, &m);
941 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
942 u8 *data, size_t len)
944 struct spi_device *spi = dbi->spi;
945 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
946 spi->max_speed_hz / 2);
947 struct spi_transfer tr[2] = {
949 .speed_hz = speed_hz,
951 .tx_buf = dbi->tx_buf9,
954 .speed_hz = speed_hz,
960 struct spi_message m;
967 if (!spi_is_bpw_supported(spi, 9)) {
969 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
970 * for reads using emulation.
973 "reading on host not supporting 9 bpw not yet implemented\n");
978 * Turn the 8bit command into a 16bit version of the command in the
979 * buffer. Only 9 bits of this will be used when executing the actual
982 dst16 = dbi->tx_buf9;
985 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
986 ret = spi_sync(spi, &m);
989 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
994 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
995 u8 *parameters, size_t num)
997 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
1000 if (mipi_dbi_command_is_read(dbi, *cmd))
1001 return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1003 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1005 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1009 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1012 /* MIPI DBI Type C Option 3 */
1014 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1015 u8 *data, size_t len)
1017 struct spi_device *spi = dbi->spi;
1018 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1019 spi->max_speed_hz / 2);
1020 struct spi_transfer tr[2] = {
1022 .speed_hz = speed_hz,
1026 .speed_hz = speed_hz,
1030 struct spi_message m;
1038 * Support non-standard 24-bit and 32-bit Nokia read commands which
1039 * start with a dummy clock, so we need to read an extra byte.
1041 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1042 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1043 if (!(len == 3 || len == 4))
1046 tr[1].len = len + 1;
1049 buf = kmalloc(tr[1].len, GFP_KERNEL);
1054 gpiod_set_value_cansleep(dbi->dc, 0);
1056 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1057 ret = spi_sync(spi, &m);
1061 if (tr[1].len == len) {
1062 memcpy(data, buf, len);
1066 for (i = 0; i < len; i++)
1067 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1070 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1078 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1079 u8 *par, size_t num)
1081 struct spi_device *spi = dbi->spi;
1082 unsigned int bpw = 8;
1086 if (mipi_dbi_command_is_read(dbi, *cmd))
1087 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1089 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1091 gpiod_set_value_cansleep(dbi->dc, 0);
1092 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1093 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1097 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1100 gpiod_set_value_cansleep(dbi->dc, 1);
1101 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1103 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1107 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1109 * @dbi: MIPI DBI structure to initialize
1110 * @dc: D/C gpio (optional)
1112 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1113 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1114 * a driver-specific init.
1116 * If @dc is set, a Type C Option 3 interface is assumed, if not
1119 * If the SPI master driver doesn't support the necessary bits per word,
1120 * the following transformation is used:
1122 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
1123 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
1126 * Zero on success, negative error code on failure.
1128 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1129 struct gpio_desc *dc)
1131 struct device *dev = &spi->dev;
1135 * Even though it's not the SPI device that does DMA (the master does),
1136 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1137 * (e.g., drm_gem_cma_create()). The dma_addr returned will be a physical
1138 * address which might be different from the bus address, but this is
1139 * not a problem since the address will not be used.
1140 * The virtual address is used in the transfer and the SPI core
1141 * re-maps it on the SPI master device using the DMA streaming API
1144 if (!dev->coherent_dma_mask) {
1145 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1147 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1153 dbi->read_commands = mipi_dbi_dcs_read_commands;
1156 dbi->command = mipi_dbi_typec3_command;
1158 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1159 dbi->swap_bytes = true;
1161 dbi->command = mipi_dbi_typec1_command;
1162 dbi->tx_buf9_len = SZ_16K;
1163 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1168 mutex_init(&dbi->cmdlock);
1170 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1174 EXPORT_SYMBOL(mipi_dbi_spi_init);
1177 * mipi_dbi_spi_transfer - SPI transfer helper
1179 * @speed_hz: Override speed (optional)
1180 * @bpw: Bits per word
1181 * @buf: Buffer to transfer
1182 * @len: Buffer length
1184 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1185 * the SPI controller driver can handle.
1188 * Zero on success, negative error code on failure.
1190 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1191 u8 bpw, const void *buf, size_t len)
1193 size_t max_chunk = spi_max_transfer_size(spi);
1194 struct spi_transfer tr = {
1195 .bits_per_word = bpw,
1196 .speed_hz = speed_hz,
1198 struct spi_message m;
1202 spi_message_init_with_transfers(&m, &tr, 1);
1205 chunk = min(len, max_chunk);
1212 ret = spi_sync(spi, &m);
1219 EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1221 #endif /* CONFIG_SPI */
1223 #ifdef CONFIG_DEBUG_FS
1225 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1226 const char __user *ubuf,
1227 size_t count, loff_t *ppos)
1229 struct seq_file *m = file->private_data;
1230 struct mipi_dbi_dev *dbidev = m->private;
1231 u8 val, cmd = 0, parameters[64];
1232 char *buf, *pos, *token;
1235 if (!drm_dev_enter(&dbidev->drm, &idx))
1238 buf = memdup_user_nul(ubuf, count);
1244 /* strip trailing whitespace */
1245 for (i = count - 1; i > 0; i--)
1246 if (isspace(buf[i]))
1253 token = strsep(&pos, " ");
1259 ret = kstrtou8(token, 16, &val);
1266 parameters[i++] = val;
1274 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1281 return ret < 0 ? ret : count;
1284 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1286 struct mipi_dbi_dev *dbidev = m->private;
1287 struct mipi_dbi *dbi = &dbidev->dbi;
1292 if (!drm_dev_enter(&dbidev->drm, &idx))
1295 for (cmd = 0; cmd < 255; cmd++) {
1296 if (!mipi_dbi_command_is_read(dbi, cmd))
1300 case MIPI_DCS_READ_MEMORY_START:
1301 case MIPI_DCS_READ_MEMORY_CONTINUE:
1304 case MIPI_DCS_GET_DISPLAY_ID:
1307 case MIPI_DCS_GET_DISPLAY_STATUS:
1315 seq_printf(m, "%02x: ", cmd);
1316 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1318 seq_puts(m, "XX\n");
1321 seq_printf(m, "%*phN\n", (int)len, val);
1329 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1332 return single_open(file, mipi_dbi_debugfs_command_show,
1336 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1337 .owner = THIS_MODULE,
1338 .open = mipi_dbi_debugfs_command_open,
1340 .llseek = seq_lseek,
1341 .release = single_release,
1342 .write = mipi_dbi_debugfs_command_write,
1346 * mipi_dbi_debugfs_init - Create debugfs entries
1349 * This function creates a 'command' debugfs file for sending commands to the
1350 * controller or getting the read command values.
1351 * Drivers can use this as their &drm_driver->debugfs_init callback.
1354 void mipi_dbi_debugfs_init(struct drm_minor *minor)
1356 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1357 umode_t mode = S_IFREG | S_IWUSR;
1359 if (dbidev->dbi.read_commands)
1361 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1362 &mipi_dbi_debugfs_command_fops);
1364 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1368 MODULE_LICENSE("GPL");