2 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
27 #define SCDC_SINK_VERSION 0x01
29 #define SCDC_SOURCE_VERSION 0x02
31 #define SCDC_UPDATE_0 0x10
32 #define SCDC_READ_REQUEST_TEST (1 << 2)
33 #define SCDC_CED_UPDATE (1 << 1)
34 #define SCDC_STATUS_UPDATE (1 << 0)
36 #define SCDC_UPDATE_1 0x11
38 #define SCDC_TMDS_CONFIG 0x20
39 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
40 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
41 #define SCDC_SCRAMBLING_ENABLE (1 << 0)
43 #define SCDC_SCRAMBLER_STATUS 0x21
44 #define SCDC_SCRAMBLING_STATUS (1 << 0)
46 #define SCDC_CONFIG_0 0x30
47 #define SCDC_READ_REQUEST_ENABLE (1 << 0)
49 #define SCDC_STATUS_FLAGS_0 0x40
50 #define SCDC_CH2_LOCK (1 << 3)
51 #define SCDC_CH1_LOCK (1 << 2)
52 #define SCDC_CH0_LOCK (1 << 1)
53 #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
54 #define SCDC_CLOCK_DETECT (1 << 0)
56 #define SCDC_STATUS_FLAGS_1 0x41
58 #define SCDC_ERR_DET_0_L 0x50
59 #define SCDC_ERR_DET_0_H 0x51
60 #define SCDC_ERR_DET_1_L 0x52
61 #define SCDC_ERR_DET_1_H 0x53
62 #define SCDC_ERR_DET_2_L 0x54
63 #define SCDC_ERR_DET_2_H 0x55
64 #define SCDC_CHANNEL_VALID (1 << 7)
66 #define SCDC_ERR_DET_CHECKSUM 0x56
68 #define SCDC_TEST_CONFIG_0 0xc0
69 #define SCDC_TEST_READ_REQUEST (1 << 7)
70 #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
72 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
73 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
75 #define SCDC_DEVICE_ID 0xd3
76 #define SCDC_DEVICE_ID_SIZE 8
78 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
79 #define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
80 #define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
82 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
83 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
85 #define SCDC_MANUFACTURER_SPECIFIC 0xde
86 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34