drivers/watchdog/stm32_iwdg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STM32 Independent Watchdog
   4  *
   5  * Copyright (C) STMicroelectronics 2017
   6  * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   7  *
   8  * This driver is based on tegra_wdt.c
   9  *
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/watchdog.h>
  23
  24 #define DEFAULT_TIMEOUT 10
  25
  26 /* IWDG registers */
  27 #define IWDG_KR         0x00 /* Key register */
  28 #define IWDG_PR         0x04 /* Prescaler Register */
  29 #define IWDG_RLR        0x08 /* ReLoad Register */
  30 #define IWDG_SR         0x0C /* Status Register */
  31 #define IWDG_WINR       0x10 /* Windows Register */
  32
  33 /* IWDG_KR register bit mask */
  34 #define KR_KEY_RELOAD   0xAAAA /* reload counter enable */
  35 #define KR_KEY_ENABLE   0xCCCC /* peripheral enable */
  36 #define KR_KEY_EWA      0x5555 /* write access enable */
  37 #define KR_KEY_DWA      0x0000 /* write access disable */
  38
  39 /* IWDG_PR register */
  40 #define PR_SHIFT        2
  41 #define PR_MIN          BIT(PR_SHIFT)
  42
  43 /* IWDG_RLR register values */
  44 #define RLR_MIN         0x2             /* min value recommended */
  45 #define RLR_MAX         GENMASK(11, 0)  /* max value of reload register */
  46
  47 /* IWDG_SR register bit mask */
  48 #define SR_PVU  BIT(0) /* Watchdog prescaler value update */
  49 #define SR_RVU  BIT(1) /* Watchdog counter reload value update */
  50
  51 /* set timeout to 100000 us */
  52 #define TIMEOUT_US      100000
  53 #define SLEEP_US        1000
  54
  55 struct stm32_iwdg_data {
  56         bool has_pclk;
  57         u32 max_prescaler;
  58 };
  59
  60 static const struct stm32_iwdg_data stm32_iwdg_data = {
  61         .has_pclk = false,
  62         .max_prescaler = 256,
  63 };
  64
  65 static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
  66         .has_pclk = true,
  67         .max_prescaler = 1024,
  68 };
  69
  70 struct stm32_iwdg {
  71         struct watchdog_device  wdd;
  72         const struct stm32_iwdg_data *data;
  73         void __iomem            *regs;
  74         struct clk              *clk_lsi;
  75         struct clk              *clk_pclk;
  76         unsigned int            rate;
  77 };
  78
  79 static inline u32 reg_read(void __iomem *base, u32 reg)
  80 {
  81         return readl_relaxed(base + reg);
  82 }
  83
  84 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
  85 {
  86         writel_relaxed(val, base + reg);
  87 }
  88
  89 static int stm32_iwdg_start(struct watchdog_device *wdd)
  90 {
  91         struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
  92         u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
  93         int ret;
  94
  95         dev_dbg(wdd->parent, "%s\n", __func__);
  96
  97         tout = clamp_t(unsigned int, wdd->timeout,
  98                        wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
  99
 100         presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
 101
 102         /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
 103         presc = roundup_pow_of_two(presc);
 104         iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
 105         iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
 106
 107         /* enable write access */
 108         reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
 109
 110         /* set prescaler & reload registers */
 111         reg_write(wdt->regs, IWDG_PR, iwdg_pr);
 112         reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
 113         reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
 114
 115         /* wait for the registers to be updated (max 100ms) */
 116         ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
 117                                          !(iwdg_sr & (SR_PVU | SR_RVU)),
 118                                          SLEEP_US, TIMEOUT_US);
 119         if (ret) {
 120                 dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
 121                 return ret;
 122         }
 123
 124         /* reload watchdog */
 125         reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
 126
 127         return 0;
 128 }
 129
 130 static int stm32_iwdg_ping(struct watchdog_device *wdd)
 131 {
 132         struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
 133
 134         dev_dbg(wdd->parent, "%s\n", __func__);
 135
 136         /* reload watchdog */
 137         reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
 138
 139         return 0;
 140 }
 141
 142 static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
 143                                   unsigned int timeout)
 144 {
 145         dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
 146
 147         wdd->timeout = timeout;
 148
 149         if (watchdog_active(wdd))
 150                 return stm32_iwdg_start(wdd);
 151
 152         return 0;
 153 }
 154
 155 static void stm32_clk_disable_unprepare(void *data)
 156 {
 157         clk_disable_unprepare(data);
 158 }
 159
 160 static int stm32_iwdg_clk_init(struct platform_device *pdev,
 161                                struct stm32_iwdg *wdt)
 162 {
 163         struct device *dev = &pdev->dev;
 164         u32 ret;
 165
 166         wdt->clk_lsi = devm_clk_get(dev, "lsi");
 167         if (IS_ERR(wdt->clk_lsi))
 168                 return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
 169
 170         /* optional peripheral clock */
 171         if (wdt->data->has_pclk) {
 172                 wdt->clk_pclk = devm_clk_get(dev, "pclk");
 173                 if (IS_ERR(wdt->clk_pclk))
 174                         return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
 175                                              "Unable to get pclk clock\n");
 176
 177                 ret = clk_prepare_enable(wdt->clk_pclk);
 178                 if (ret) {
 179                         dev_err(dev, "Unable to prepare pclk clock\n");
 180                         return ret;
 181                 }
 182                 ret = devm_add_action_or_reset(dev,
 183                                                stm32_clk_disable_unprepare,
 184                                                wdt->clk_pclk);
 185                 if (ret)
 186                         return ret;
 187         }
 188
 189         ret = clk_prepare_enable(wdt->clk_lsi);
 190         if (ret) {
 191                 dev_err(dev, "Unable to prepare lsi clock\n");
 192                 return ret;
 193         }
 194         ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
 195                                        wdt->clk_lsi);
 196         if (ret)
 197                 return ret;
 198
 199         wdt->rate = clk_get_rate(wdt->clk_lsi);
 200
 201         return 0;
 202 }
 203
 204 static const struct watchdog_info stm32_iwdg_info = {
 205         .options        = WDIOF_SETTIMEOUT |
 206                           WDIOF_MAGICCLOSE |
 207                           WDIOF_KEEPALIVEPING,
 208         .identity       = "STM32 Independent Watchdog",
 209 };
 210
 211 static const struct watchdog_ops stm32_iwdg_ops = {
 212         .owner          = THIS_MODULE,
 213         .start          = stm32_iwdg_start,
 214         .ping           = stm32_iwdg_ping,
 215         .set_timeout    = stm32_iwdg_set_timeout,
 216 };
 217
 218 static const struct of_device_id stm32_iwdg_of_match[] = {
 219         { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
 220         { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
 221         { /* end node */ }
 222 };
 223 MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
 224
 225 static int stm32_iwdg_probe(struct platform_device *pdev)
 226 {
 227         struct device *dev = &pdev->dev;
 228         struct watchdog_device *wdd;
 229         struct stm32_iwdg *wdt;
 230         int ret;
 231
 232         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 233         if (!wdt)
 234                 return -ENOMEM;
 235
 236         wdt->data = of_device_get_match_data(&pdev->dev);
 237         if (!wdt->data)
 238                 return -ENODEV;
 239
 240         /* This is the timer base. */
 241         wdt->regs = devm_platform_ioremap_resource(pdev, 0);
 242         if (IS_ERR(wdt->regs))
 243                 return PTR_ERR(wdt->regs);
 244
 245         ret = stm32_iwdg_clk_init(pdev, wdt);
 246         if (ret)
 247                 return ret;
 248
 249         /* Initialize struct watchdog_device. */
 250         wdd = &wdt->wdd;
 251         wdd->parent = dev;
 252         wdd->info = &stm32_iwdg_info;
 253         wdd->ops = &stm32_iwdg_ops;
 254         wdd->timeout = DEFAULT_TIMEOUT;
 255         wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
 256         wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
 257                                     1000) / wdt->rate;
 258
 259         watchdog_set_drvdata(wdd, wdt);
 260         watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
 261         watchdog_init_timeout(wdd, 0, dev);
 262
 263         /*
 264          * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
 265          * (Means U-Boot/bootloaders leaves the watchdog running)
 266          * When we get here we should make a decision to prevent
 267          * any side effects before user space daemon will take care of it.
 268          * The best option, taking into consideration that there is no
 269          * way to read values back from hardware, is to enforce watchdog
 270          * being run with deterministic values.
 271          */
 272         if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
 273                 ret = stm32_iwdg_start(wdd);
 274                 if (ret)
 275                         return ret;
 276
 277                 /* Make sure the watchdog is serviced */
 278                 set_bit(WDOG_HW_RUNNING, &wdd->status);
 279         }
 280
 281         ret = devm_watchdog_register_device(dev, wdd);
 282         if (ret)
 283                 return ret;
 284
 285         platform_set_drvdata(pdev, wdt);
 286
 287         return 0;
 288 }
 289
 290 static struct platform_driver stm32_iwdg_driver = {
 291         .probe          = stm32_iwdg_probe,
 292         .driver = {
 293                 .name   = "iwdg",
 294                 .of_match_table = of_match_ptr(stm32_iwdg_of_match),
 295         },
 296 };
 297 module_platform_driver(stm32_iwdg_driver);
 298
 299 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
 300 MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
 301 MODULE_LICENSE("GPL v2");