1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STM32 Independent Watchdog
5 * Copyright (C) STMicroelectronics 2017
6 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
8 * This driver is based on tegra_wdt.c
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/watchdog.h>
24 #define DEFAULT_TIMEOUT 10
27 #define IWDG_KR 0x00 /* Key register */
28 #define IWDG_PR 0x04 /* Prescaler Register */
29 #define IWDG_RLR 0x08 /* ReLoad Register */
30 #define IWDG_SR 0x0C /* Status Register */
31 #define IWDG_WINR 0x10 /* Windows Register */
33 /* IWDG_KR register bit mask */
34 #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
35 #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
36 #define KR_KEY_EWA 0x5555 /* write access enable */
37 #define KR_KEY_DWA 0x0000 /* write access disable */
39 /* IWDG_PR register */
41 #define PR_MIN BIT(PR_SHIFT)
43 /* IWDG_RLR register values */
44 #define RLR_MIN 0x2 /* min value recommended */
45 #define RLR_MAX GENMASK(11, 0) /* max value of reload register */
47 /* IWDG_SR register bit mask */
48 #define SR_PVU BIT(0) /* Watchdog prescaler value update */
49 #define SR_RVU BIT(1) /* Watchdog counter reload value update */
51 /* set timeout to 100000 us */
52 #define TIMEOUT_US 100000
55 struct stm32_iwdg_data {
60 static const struct stm32_iwdg_data stm32_iwdg_data = {
65 static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
67 .max_prescaler = 1024,
71 struct watchdog_device wdd;
72 const struct stm32_iwdg_data *data;
79 static inline u32 reg_read(void __iomem *base, u32 reg)
81 return readl_relaxed(base + reg);
84 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
86 writel_relaxed(val, base + reg);
89 static int stm32_iwdg_start(struct watchdog_device *wdd)
91 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
92 u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
95 dev_dbg(wdd->parent, "%s\n", __func__);
97 tout = clamp_t(unsigned int, wdd->timeout,
98 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
100 presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
102 /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
103 presc = roundup_pow_of_two(presc);
104 iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
105 iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
107 /* enable write access */
108 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
110 /* set prescaler & reload registers */
111 reg_write(wdt->regs, IWDG_PR, iwdg_pr);
112 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
113 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
115 /* wait for the registers to be updated (max 100ms) */
116 ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
117 !(iwdg_sr & (SR_PVU | SR_RVU)),
118 SLEEP_US, TIMEOUT_US);
120 dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
124 /* reload watchdog */
125 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
130 static int stm32_iwdg_ping(struct watchdog_device *wdd)
132 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
134 dev_dbg(wdd->parent, "%s\n", __func__);
136 /* reload watchdog */
137 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
142 static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
143 unsigned int timeout)
145 dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
147 wdd->timeout = timeout;
149 if (watchdog_active(wdd))
150 return stm32_iwdg_start(wdd);
155 static void stm32_clk_disable_unprepare(void *data)
157 clk_disable_unprepare(data);
160 static int stm32_iwdg_clk_init(struct platform_device *pdev,
161 struct stm32_iwdg *wdt)
163 struct device *dev = &pdev->dev;
166 wdt->clk_lsi = devm_clk_get(dev, "lsi");
167 if (IS_ERR(wdt->clk_lsi)) {
168 dev_err(dev, "Unable to get lsi clock\n");
169 return PTR_ERR(wdt->clk_lsi);
172 /* optional peripheral clock */
173 if (wdt->data->has_pclk) {
174 wdt->clk_pclk = devm_clk_get(dev, "pclk");
175 if (IS_ERR(wdt->clk_pclk)) {
176 dev_err(dev, "Unable to get pclk clock\n");
177 return PTR_ERR(wdt->clk_pclk);
180 ret = clk_prepare_enable(wdt->clk_pclk);
182 dev_err(dev, "Unable to prepare pclk clock\n");
185 ret = devm_add_action_or_reset(dev,
186 stm32_clk_disable_unprepare,
192 ret = clk_prepare_enable(wdt->clk_lsi);
194 dev_err(dev, "Unable to prepare lsi clock\n");
197 ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
202 wdt->rate = clk_get_rate(wdt->clk_lsi);
207 static const struct watchdog_info stm32_iwdg_info = {
208 .options = WDIOF_SETTIMEOUT |
211 .identity = "STM32 Independent Watchdog",
214 static const struct watchdog_ops stm32_iwdg_ops = {
215 .owner = THIS_MODULE,
216 .start = stm32_iwdg_start,
217 .ping = stm32_iwdg_ping,
218 .set_timeout = stm32_iwdg_set_timeout,
221 static const struct of_device_id stm32_iwdg_of_match[] = {
222 { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
223 { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
226 MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
228 static int stm32_iwdg_probe(struct platform_device *pdev)
230 struct device *dev = &pdev->dev;
231 struct watchdog_device *wdd;
232 struct stm32_iwdg *wdt;
235 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
239 wdt->data = of_device_get_match_data(&pdev->dev);
243 /* This is the timer base. */
244 wdt->regs = devm_platform_ioremap_resource(pdev, 0);
245 if (IS_ERR(wdt->regs)) {
246 dev_err(dev, "Could not get resource\n");
247 return PTR_ERR(wdt->regs);
250 ret = stm32_iwdg_clk_init(pdev, wdt);
254 /* Initialize struct watchdog_device. */
257 wdd->info = &stm32_iwdg_info;
258 wdd->ops = &stm32_iwdg_ops;
259 wdd->timeout = DEFAULT_TIMEOUT;
260 wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
261 wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
264 watchdog_set_drvdata(wdd, wdt);
265 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
266 watchdog_init_timeout(wdd, 0, dev);
269 * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
270 * (Means U-Boot/bootloaders leaves the watchdog running)
271 * When we get here we should make a decision to prevent
272 * any side effects before user space daemon will take care of it.
273 * The best option, taking into consideration that there is no
274 * way to read values back from hardware, is to enforce watchdog
275 * being run with deterministic values.
277 if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
278 ret = stm32_iwdg_start(wdd);
282 /* Make sure the watchdog is serviced */
283 set_bit(WDOG_HW_RUNNING, &wdd->status);
286 ret = devm_watchdog_register_device(dev, wdd);
290 platform_set_drvdata(pdev, wdt);
295 static struct platform_driver stm32_iwdg_driver = {
296 .probe = stm32_iwdg_probe,
299 .of_match_table = of_match_ptr(stm32_iwdg_of_match),
302 module_platform_driver(stm32_iwdg_driver);
304 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
305 MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
306 MODULE_LICENSE("GPL v2");