2 * Spreadtrum watchdog driver
3 * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
15 #include <linux/bitops.h>
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/watchdog.h>
28 #define SPRD_WDT_LOAD_LOW 0x0
29 #define SPRD_WDT_LOAD_HIGH 0x4
30 #define SPRD_WDT_CTRL 0x8
31 #define SPRD_WDT_INT_CLR 0xc
32 #define SPRD_WDT_INT_RAW 0x10
33 #define SPRD_WDT_INT_MSK 0x14
34 #define SPRD_WDT_CNT_LOW 0x18
35 #define SPRD_WDT_CNT_HIGH 0x1c
36 #define SPRD_WDT_LOCK 0x20
37 #define SPRD_WDT_IRQ_LOAD_LOW 0x2c
38 #define SPRD_WDT_IRQ_LOAD_HIGH 0x30
41 #define SPRD_WDT_INT_EN_BIT BIT(0)
42 #define SPRD_WDT_CNT_EN_BIT BIT(1)
43 #define SPRD_WDT_NEW_VER_EN BIT(2)
44 #define SPRD_WDT_RST_EN_BIT BIT(3)
47 #define SPRD_WDT_INT_CLEAR_BIT BIT(0)
48 #define SPRD_WDT_RST_CLEAR_BIT BIT(3)
51 #define SPRD_WDT_INT_RAW_BIT BIT(0)
52 #define SPRD_WDT_RST_RAW_BIT BIT(3)
53 #define SPRD_WDT_LD_BUSY_BIT BIT(4)
55 /* 1s equal to 32768 counter steps */
56 #define SPRD_WDT_CNT_STEP 32768
58 #define SPRD_WDT_UNLOCK_KEY 0xe551
59 #define SPRD_WDT_MIN_TIMEOUT 3
60 #define SPRD_WDT_MAX_TIMEOUT 60
62 #define SPRD_WDT_CNT_HIGH_SHIFT 16
63 #define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0)
64 #define SPRD_WDT_LOAD_TIMEOUT 1000
68 struct watchdog_device wdd;
70 struct clk *rtc_enable;
74 static inline struct sprd_wdt *to_sprd_wdt(struct watchdog_device *wdd)
76 return container_of(wdd, struct sprd_wdt, wdd);
79 static inline void sprd_wdt_lock(void __iomem *addr)
81 writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
84 static inline void sprd_wdt_unlock(void __iomem *addr)
86 writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
89 static irqreturn_t sprd_wdt_isr(int irq, void *dev_id)
91 struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id;
93 sprd_wdt_unlock(wdt->base);
94 writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
95 sprd_wdt_lock(wdt->base);
96 watchdog_notify_pretimeout(&wdt->wdd);
100 static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt)
104 val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) <<
105 SPRD_WDT_CNT_HIGH_SHIFT;
106 val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) &
107 SPRD_WDT_LOW_VALUE_MASK;
112 static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout,
115 u32 val, delay_cnt = 0;
116 u32 tmr_step = timeout * SPRD_WDT_CNT_STEP;
117 u32 prtmr_step = pretimeout * SPRD_WDT_CNT_STEP;
120 * Waiting the load value operation done,
121 * it needs two or three RTC clock cycles.
124 val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW);
125 if (!(val & SPRD_WDT_LD_BUSY_BIT))
129 } while (delay_cnt++ < SPRD_WDT_LOAD_TIMEOUT);
131 if (delay_cnt >= SPRD_WDT_LOAD_TIMEOUT)
134 sprd_wdt_unlock(wdt->base);
135 writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
136 SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH);
137 writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
138 wdt->base + SPRD_WDT_LOAD_LOW);
139 writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
140 SPRD_WDT_LOW_VALUE_MASK,
141 wdt->base + SPRD_WDT_IRQ_LOAD_HIGH);
142 writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
143 wdt->base + SPRD_WDT_IRQ_LOAD_LOW);
144 sprd_wdt_lock(wdt->base);
149 static int sprd_wdt_enable(struct sprd_wdt *wdt)
154 ret = clk_prepare_enable(wdt->enable);
157 ret = clk_prepare_enable(wdt->rtc_enable);
159 clk_disable_unprepare(wdt->enable);
163 sprd_wdt_unlock(wdt->base);
164 val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
165 val |= SPRD_WDT_NEW_VER_EN;
166 writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
167 sprd_wdt_lock(wdt->base);
171 static void sprd_wdt_disable(void *_data)
173 struct sprd_wdt *wdt = _data;
175 sprd_wdt_unlock(wdt->base);
176 writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
177 sprd_wdt_lock(wdt->base);
179 clk_disable_unprepare(wdt->rtc_enable);
180 clk_disable_unprepare(wdt->enable);
183 static int sprd_wdt_start(struct watchdog_device *wdd)
185 struct sprd_wdt *wdt = to_sprd_wdt(wdd);
189 ret = sprd_wdt_load_value(wdt, wdd->timeout, wdd->pretimeout);
193 sprd_wdt_unlock(wdt->base);
194 val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
195 val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT;
196 writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
197 sprd_wdt_lock(wdt->base);
198 set_bit(WDOG_HW_RUNNING, &wdd->status);
203 static int sprd_wdt_stop(struct watchdog_device *wdd)
205 struct sprd_wdt *wdt = to_sprd_wdt(wdd);
208 sprd_wdt_unlock(wdt->base);
209 val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
210 val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT |
211 SPRD_WDT_INT_EN_BIT);
212 writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
213 sprd_wdt_lock(wdt->base);
217 static int sprd_wdt_set_timeout(struct watchdog_device *wdd,
220 struct sprd_wdt *wdt = to_sprd_wdt(wdd);
222 if (timeout == wdd->timeout)
225 wdd->timeout = timeout;
227 return sprd_wdt_load_value(wdt, timeout, wdd->pretimeout);
230 static int sprd_wdt_set_pretimeout(struct watchdog_device *wdd,
233 struct sprd_wdt *wdt = to_sprd_wdt(wdd);
235 if (new_pretimeout < wdd->min_timeout)
238 wdd->pretimeout = new_pretimeout;
240 return sprd_wdt_load_value(wdt, wdd->timeout, new_pretimeout);
243 static u32 sprd_wdt_get_timeleft(struct watchdog_device *wdd)
245 struct sprd_wdt *wdt = to_sprd_wdt(wdd);
248 val = sprd_wdt_get_cnt_value(wdt);
249 val = val / SPRD_WDT_CNT_STEP;
254 static const struct watchdog_ops sprd_wdt_ops = {
255 .owner = THIS_MODULE,
256 .start = sprd_wdt_start,
257 .stop = sprd_wdt_stop,
258 .set_timeout = sprd_wdt_set_timeout,
259 .set_pretimeout = sprd_wdt_set_pretimeout,
260 .get_timeleft = sprd_wdt_get_timeleft,
263 static const struct watchdog_info sprd_wdt_info = {
264 .options = WDIOF_SETTIMEOUT |
268 .identity = "Spreadtrum Watchdog Timer",
271 static int sprd_wdt_probe(struct platform_device *pdev)
273 struct resource *wdt_res;
274 struct sprd_wdt *wdt;
277 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
281 wdt_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
282 wdt->base = devm_ioremap_resource(&pdev->dev, wdt_res);
283 if (IS_ERR(wdt->base))
284 return PTR_ERR(wdt->base);
286 wdt->enable = devm_clk_get(&pdev->dev, "enable");
287 if (IS_ERR(wdt->enable)) {
288 dev_err(&pdev->dev, "can't get the enable clock\n");
289 return PTR_ERR(wdt->enable);
292 wdt->rtc_enable = devm_clk_get(&pdev->dev, "rtc_enable");
293 if (IS_ERR(wdt->rtc_enable)) {
294 dev_err(&pdev->dev, "can't get the rtc enable clock\n");
295 return PTR_ERR(wdt->rtc_enable);
298 wdt->irq = platform_get_irq(pdev, 0);
300 dev_err(&pdev->dev, "failed to get IRQ resource\n");
304 ret = devm_request_irq(&pdev->dev, wdt->irq, sprd_wdt_isr,
305 IRQF_NO_SUSPEND, "sprd-wdt", (void *)wdt);
307 dev_err(&pdev->dev, "failed to register irq\n");
311 wdt->wdd.info = &sprd_wdt_info;
312 wdt->wdd.ops = &sprd_wdt_ops;
313 wdt->wdd.parent = &pdev->dev;
314 wdt->wdd.min_timeout = SPRD_WDT_MIN_TIMEOUT;
315 wdt->wdd.max_timeout = SPRD_WDT_MAX_TIMEOUT;
316 wdt->wdd.timeout = SPRD_WDT_MAX_TIMEOUT;
318 ret = sprd_wdt_enable(wdt);
320 dev_err(&pdev->dev, "failed to enable wdt\n");
323 ret = devm_add_action(&pdev->dev, sprd_wdt_disable, wdt);
325 sprd_wdt_disable(wdt);
326 dev_err(&pdev->dev, "Failed to add wdt disable action\n");
330 watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
331 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
333 ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
335 sprd_wdt_disable(wdt);
336 dev_err(&pdev->dev, "failed to register watchdog\n");
339 platform_set_drvdata(pdev, wdt);
344 static int __maybe_unused sprd_wdt_pm_suspend(struct device *dev)
346 struct sprd_wdt *wdt = dev_get_drvdata(dev);
348 if (watchdog_active(&wdt->wdd))
349 sprd_wdt_stop(&wdt->wdd);
350 sprd_wdt_disable(wdt);
355 static int __maybe_unused sprd_wdt_pm_resume(struct device *dev)
357 struct sprd_wdt *wdt = dev_get_drvdata(dev);
360 ret = sprd_wdt_enable(wdt);
364 if (watchdog_active(&wdt->wdd))
365 ret = sprd_wdt_start(&wdt->wdd);
370 static const struct dev_pm_ops sprd_wdt_pm_ops = {
371 SET_SYSTEM_SLEEP_PM_OPS(sprd_wdt_pm_suspend,
375 static const struct of_device_id sprd_wdt_match_table[] = {
376 { .compatible = "sprd,sp9860-wdt", },
379 MODULE_DEVICE_TABLE(of, sprd_wdt_match_table);
381 static struct platform_driver sprd_watchdog_driver = {
382 .probe = sprd_wdt_probe,
385 .of_match_table = sprd_wdt_match_table,
386 .pm = &sprd_wdt_pm_ops,
389 module_platform_driver(sprd_watchdog_driver);
391 MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
392 MODULE_DESCRIPTION("Spreadtrum Watchdog Timer Controller Driver");
393 MODULE_LICENSE("GPL v2");