2 * SBSA(Server Base System Architecture) Generic Watchdog driver
4 * Copyright (c) 2015, Linaro Ltd.
5 * Author: Fu Wei <fu.wei@linaro.org>
6 * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
7 * Al Stone <al.stone@linaro.org>
8 * Timur Tabi <timur@codeaurora.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License 2 as published
12 * by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * ARM SBSA Generic Watchdog has two stage timeouts:
20 * the first signal (WS0) is for alerting the system by interrupt,
21 * the second one (WS1) is a real hardware reset.
22 * More details about the hardware specification of this device:
23 * ARM DEN0029B - Server Base System Architecture (SBSA)
25 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
26 * or a two stages watchdog, it's set up by the module parameter "action".
27 * In the single stage mode, when the timeout is reached, your system
28 * will be reset by WS1. The first signal (WS0) is ignored.
29 * In the two stages mode, when the timeout is reached, the first signal (WS0)
30 * will trigger panic. If the system is getting into trouble and cannot be reset
31 * by panic or restart properly by the kdump kernel(if supported), then the
32 * second stage (as long as the first stage) will be reached, system will be
33 * reset by WS1. This function can help administrator to backup the system
34 * context info by panic console output or kdump.
37 * if action is 1 (the two stages mode):
38 * |--------WOR-------WS0--------WOR-------WS1
39 * |----timeout-----(panic)----timeout-----reset
41 * if action is 0 (the single stage mode):
42 * |------WOR-----WS0(ignored)-----WOR------WS1
43 * |--------------timeout-------------------reset
45 * Note: Since this watchdog timer has two stages, and each stage is determined
46 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
47 * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
48 * is half of that in the single stage mode.
53 #include <linux/io-64-nonatomic-lo-hi.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
58 #include <linux/of_device.h>
59 #include <linux/platform_device.h>
60 #include <linux/uaccess.h>
61 #include <linux/watchdog.h>
62 #include <asm/arch_timer.h>
64 #define DRV_NAME "sbsa-gwdt"
65 #define WATCHDOG_NAME "SBSA Generic Watchdog"
67 /* SBSA Generic Watchdog register definitions */
69 #define SBSA_GWDT_WRR 0x000
72 #define SBSA_GWDT_WCS 0x000
73 #define SBSA_GWDT_WOR 0x008
74 #define SBSA_GWDT_WCV 0x010
76 /* refresh/control frame */
77 #define SBSA_GWDT_W_IIDR 0xfcc
78 #define SBSA_GWDT_IDR 0xfd0
80 /* Watchdog Control and Status Register */
81 #define SBSA_GWDT_WCS_EN BIT(0)
82 #define SBSA_GWDT_WCS_WS0 BIT(1)
83 #define SBSA_GWDT_WCS_WS1 BIT(2)
86 * struct sbsa_gwdt - Internal representation of the SBSA GWDT
87 * @wdd: kernel watchdog_device structure
88 * @clk: store the System Counter clock frequency, in Hz.
89 * @refresh_base: Virtual address of the watchdog refresh frame
90 * @control_base: Virtual address of the watchdog control frame
93 struct watchdog_device wdd;
95 void __iomem *refresh_base;
96 void __iomem *control_base;
99 #define DEFAULT_TIMEOUT 10 /* seconds */
101 static unsigned int timeout;
102 module_param(timeout, uint, 0);
103 MODULE_PARM_DESC(timeout,
104 "Watchdog timeout in seconds. (>=0, default="
105 __MODULE_STRING(DEFAULT_TIMEOUT) ")");
108 * action refers to action taken when watchdog gets WS0
111 * defaults to skip (0)
114 module_param(action, int, 0);
115 MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
116 "0 = skip(*) 1 = panic");
118 static bool nowayout = WATCHDOG_NOWAYOUT;
119 module_param(nowayout, bool, S_IRUGO);
120 MODULE_PARM_DESC(nowayout,
121 "Watchdog cannot be stopped once started (default="
122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
125 * watchdog operation functions
127 static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
128 unsigned int timeout)
130 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
132 wdd->timeout = timeout;
133 timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000);
136 writel(gwdt->clk * timeout,
137 gwdt->control_base + SBSA_GWDT_WOR);
140 * In the single stage mode, The first signal (WS0) is ignored,
141 * the timeout is (WOR * 2), so the WOR should be configured
142 * to half value of timeout.
144 writel(gwdt->clk / 2 * timeout,
145 gwdt->control_base + SBSA_GWDT_WOR);
150 static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
152 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
156 * In the single stage mode, if WS0 is deasserted
157 * (watchdog is in the first stage),
158 * timeleft = WOR + (WCV - system counter)
161 !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
162 timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
164 timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
165 arch_counter_get_cntvct();
167 do_div(timeleft, gwdt->clk);
172 static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
174 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
177 * Writing WRR for an explicit watchdog refresh.
178 * You can write anyting (like 0).
180 writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
185 static int sbsa_gwdt_start(struct watchdog_device *wdd)
187 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
189 /* writing WCS will cause an explicit watchdog refresh */
190 writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
195 static int sbsa_gwdt_stop(struct watchdog_device *wdd)
197 struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
199 /* Simply write 0 to WCS to clean WCS_EN bit */
200 writel(0, gwdt->control_base + SBSA_GWDT_WCS);
205 static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
207 panic(WATCHDOG_NAME " timeout");
212 static const struct watchdog_info sbsa_gwdt_info = {
213 .identity = WATCHDOG_NAME,
214 .options = WDIOF_SETTIMEOUT |
215 WDIOF_KEEPALIVEPING |
220 static const struct watchdog_ops sbsa_gwdt_ops = {
221 .owner = THIS_MODULE,
222 .start = sbsa_gwdt_start,
223 .stop = sbsa_gwdt_stop,
224 .ping = sbsa_gwdt_keepalive,
225 .set_timeout = sbsa_gwdt_set_timeout,
226 .get_timeleft = sbsa_gwdt_get_timeleft,
229 static int sbsa_gwdt_probe(struct platform_device *pdev)
231 void __iomem *rf_base, *cf_base;
232 struct device *dev = &pdev->dev;
233 struct watchdog_device *wdd;
234 struct sbsa_gwdt *gwdt;
235 struct resource *res;
239 gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
242 platform_set_drvdata(pdev, gwdt);
244 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
245 cf_base = devm_ioremap_resource(dev, res);
247 return PTR_ERR(cf_base);
249 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
250 rf_base = devm_ioremap_resource(dev, res);
252 return PTR_ERR(rf_base);
255 * Get the frequency of system counter from the cp15 interface of ARM
256 * Generic timer. We don't need to check it, because if it returns "0",
257 * system would panic in very early stage.
259 gwdt->clk = arch_timer_get_cntfrq();
260 gwdt->refresh_base = rf_base;
261 gwdt->control_base = cf_base;
265 wdd->info = &sbsa_gwdt_info;
266 wdd->ops = &sbsa_gwdt_ops;
267 wdd->min_timeout = 1;
268 wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
269 wdd->timeout = DEFAULT_TIMEOUT;
270 watchdog_set_drvdata(wdd, gwdt);
271 watchdog_set_nowayout(wdd, nowayout);
273 status = readl(cf_base + SBSA_GWDT_WCS);
274 if (status & SBSA_GWDT_WCS_WS1) {
275 dev_warn(dev, "System reset by WDT.\n");
276 wdd->bootstatus |= WDIOF_CARDRESET;
278 if (status & SBSA_GWDT_WCS_EN)
279 set_bit(WDOG_HW_RUNNING, &wdd->status);
282 irq = platform_get_irq(pdev, 0);
285 dev_warn(dev, "unable to get ws0 interrupt.\n");
288 * In case there is a pending ws0 interrupt, just ping
289 * the watchdog before registering the interrupt routine
291 writel(0, rf_base + SBSA_GWDT_WRR);
292 if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
295 dev_warn(dev, "unable to request IRQ %d.\n",
300 dev_warn(dev, "falling back to single stage mode.\n");
303 * In the single stage mode, The first signal (WS0) is ignored,
304 * the timeout is (WOR * 2), so the maximum timeout should be doubled.
307 wdd->max_hw_heartbeat_ms *= 2;
309 watchdog_init_timeout(wdd, timeout, dev);
311 * Update timeout to WOR.
312 * Because of the explicit watchdog refresh mechanism,
313 * it's also a ping, if watchdog is enabled.
315 sbsa_gwdt_set_timeout(wdd, wdd->timeout);
317 ret = watchdog_register_device(wdd);
321 dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
322 wdd->timeout, gwdt->clk, action,
323 status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
328 static void sbsa_gwdt_shutdown(struct platform_device *pdev)
330 struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
332 sbsa_gwdt_stop(&gwdt->wdd);
335 static int sbsa_gwdt_remove(struct platform_device *pdev)
337 struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
339 watchdog_unregister_device(&gwdt->wdd);
344 /* Disable watchdog if it is active during suspend */
345 static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
347 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
349 if (watchdog_active(&gwdt->wdd))
350 sbsa_gwdt_stop(&gwdt->wdd);
355 /* Enable watchdog if necessary */
356 static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
358 struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
360 if (watchdog_active(&gwdt->wdd))
361 sbsa_gwdt_start(&gwdt->wdd);
366 static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
367 SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
370 static const struct of_device_id sbsa_gwdt_of_match[] = {
371 { .compatible = "arm,sbsa-gwdt", },
374 MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
376 static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
377 { .name = DRV_NAME, },
380 MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
382 static struct platform_driver sbsa_gwdt_driver = {
385 .pm = &sbsa_gwdt_pm_ops,
386 .of_match_table = sbsa_gwdt_of_match,
388 .probe = sbsa_gwdt_probe,
389 .remove = sbsa_gwdt_remove,
390 .shutdown = sbsa_gwdt_shutdown,
391 .id_table = sbsa_gwdt_pdev_match,
394 module_platform_driver(sbsa_gwdt_driver);
396 MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
397 MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
398 MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
399 MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
400 MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
401 MODULE_LICENSE("GPL v2");
402 MODULE_ALIAS("platform:" DRV_NAME);