drivers/watchdog/renesas_wdt.c

   1 /*
   2  * Watchdog driver for Renesas WDT watchdog
   3  *
   4  * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   5  * Copyright (C) 2015-17 Renesas Electronics Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/smp.h>
  20 #include <linux/sys_soc.h>
  21 #include <linux/watchdog.h>
  22
  23 #define RWTCNT          0
  24 #define RWTCSRA         4
  25 #define RWTCSRA_WOVF    BIT(4)
  26 #define RWTCSRA_WRFLG   BIT(5)
  27 #define RWTCSRA_TME     BIT(7)
  28 #define RWTCSRB         8
  29
  30 #define RWDT_DEFAULT_TIMEOUT 60U
  31
  32 /*
  33  * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
  34  * divider (12 bits). d is only a factor to fully utilize the WDT counter and
  35  * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
  36  */
  37 #define MUL_BY_CLKS_PER_SEC(p, d) \
  38         DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
  39
  40 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
  41 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
  42
  43 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
  44
  45 static bool nowayout = WATCHDOG_NOWAYOUT;
  46 module_param(nowayout, bool, 0);
  47 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  48                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  49
  50 struct rwdt_priv {
  51         void __iomem *base;
  52         struct watchdog_device wdev;
  53         unsigned long clk_rate;
  54         u16 time_left;
  55         u8 cks;
  56 };
  57
  58 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
  59 {
  60         if (reg == RWTCNT)
  61                 val |= 0x5a5a0000;
  62         else
  63                 val |= 0xa5a5a500;
  64
  65         writel_relaxed(val, priv->base + reg);
  66 }
  67
  68 static int rwdt_init_timeout(struct watchdog_device *wdev)
  69 {
  70         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  71
  72         rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
  73
  74         return 0;
  75 }
  76
  77 static int rwdt_start(struct watchdog_device *wdev)
  78 {
  79         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  80         u8 val;
  81
  82         pm_runtime_get_sync(wdev->parent);
  83
  84         /* Stop the timer before we modify any register */
  85         val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
  86         rwdt_write(priv, val, RWTCSRA);
  87
  88         rwdt_init_timeout(wdev);
  89         rwdt_write(priv, priv->cks, RWTCSRA);
  90         rwdt_write(priv, 0, RWTCSRB);
  91
  92         while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
  93                 cpu_relax();
  94
  95         rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
  96
  97         return 0;
  98 }
  99
 100 static int rwdt_stop(struct watchdog_device *wdev)
 101 {
 102         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 103
 104         rwdt_write(priv, priv->cks, RWTCSRA);
 105         pm_runtime_put(wdev->parent);
 106
 107         return 0;
 108 }
 109
 110 static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 111 {
 112         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 113         u16 val = readw_relaxed(priv->base + RWTCNT);
 114
 115         return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
 116 }
 117
 118 static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
 119                         void *data)
 120 {
 121         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 122
 123         rwdt_start(wdev);
 124         rwdt_write(priv, 0xffff, RWTCNT);
 125         return 0;
 126 }
 127
 128 static const struct watchdog_info rwdt_ident = {
 129         .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
 130                 WDIOF_CARDRESET,
 131         .identity = "Renesas WDT Watchdog",
 132 };
 133
 134 static const struct watchdog_ops rwdt_ops = {
 135         .owner = THIS_MODULE,
 136         .start = rwdt_start,
 137         .stop = rwdt_stop,
 138         .ping = rwdt_init_timeout,
 139         .get_timeleft = rwdt_get_timeleft,
 140         .restart = rwdt_restart,
 141 };
 142
 143 #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
 144 /*
 145  * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
 146  */
 147 static const struct soc_device_attribute rwdt_quirks_match[] = {
 148         {
 149                 .soc_id = "r8a7790",
 150                 .revision = "ES1.*",
 151                 .data = (void *)1,      /* needs single CPU */
 152         }, {
 153                 .soc_id = "r8a7791",
 154                 .revision = "ES1.*",
 155                 .data = (void *)1,      /* needs single CPU */
 156         }, {
 157                 .soc_id = "r8a7792",
 158                 .revision = "*",
 159                 .data = (void *)0,      /* needs SMP disabled */
 160         },
 161         { /* sentinel */ }
 162 };
 163
 164 static bool rwdt_blacklisted(struct device *dev)
 165 {
 166         const struct soc_device_attribute *attr;
 167
 168         attr = soc_device_match(rwdt_quirks_match);
 169         if (attr && setup_max_cpus > (uintptr_t)attr->data) {
 170                 dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
 171                          attr->revision);
 172                 return true;
 173         }
 174
 175         return false;
 176 }
 177 #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
 178 static inline bool rwdt_blacklisted(struct device *dev) { return false; }
 179 #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
 180
 181 static int rwdt_probe(struct platform_device *pdev)
 182 {
 183         struct rwdt_priv *priv;
 184         struct resource *res;
 185         struct clk *clk;
 186         unsigned long clks_per_sec;
 187         int ret, i;
 188
 189         if (rwdt_blacklisted(&pdev->dev))
 190                 return -ENODEV;
 191
 192         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 193         if (!priv)
 194                 return -ENOMEM;
 195
 196         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 197         priv->base = devm_ioremap_resource(&pdev->dev, res);
 198         if (IS_ERR(priv->base))
 199                 return PTR_ERR(priv->base);
 200
 201         clk = devm_clk_get(&pdev->dev, NULL);
 202         if (IS_ERR(clk))
 203                 return PTR_ERR(clk);
 204
 205         pm_runtime_enable(&pdev->dev);
 206         pm_runtime_get_sync(&pdev->dev);
 207         priv->clk_rate = clk_get_rate(clk);
 208         priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) &
 209                                 RWTCSRA_WOVF) ? WDIOF_CARDRESET : 0;
 210         pm_runtime_put(&pdev->dev);
 211
 212         if (!priv->clk_rate) {
 213                 ret = -ENOENT;
 214                 goto out_pm_disable;
 215         }
 216
 217         for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
 218                 clks_per_sec = priv->clk_rate / clk_divs[i];
 219                 if (clks_per_sec && clks_per_sec < 65536) {
 220                         priv->cks = i;
 221                         break;
 222                 }
 223         }
 224
 225         if (i < 0) {
 226                 dev_err(&pdev->dev, "Can't find suitable clock divider\n");
 227                 ret = -ERANGE;
 228                 goto out_pm_disable;
 229         }
 230
 231         priv->wdev.info = &rwdt_ident,
 232         priv->wdev.ops = &rwdt_ops,
 233         priv->wdev.parent = &pdev->dev;
 234         priv->wdev.min_timeout = 1;
 235         priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
 236         priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
 237
 238         platform_set_drvdata(pdev, priv);
 239         watchdog_set_drvdata(&priv->wdev, priv);
 240         watchdog_set_nowayout(&priv->wdev, nowayout);
 241         watchdog_set_restart_priority(&priv->wdev, 0);
 242         watchdog_stop_on_unregister(&priv->wdev);
 243
 244         /* This overrides the default timeout only if DT configuration was found */
 245         ret = watchdog_init_timeout(&priv->wdev, 0, &pdev->dev);
 246         if (ret)
 247                 dev_warn(&pdev->dev, "Specified timeout value invalid, using default\n");
 248
 249         ret = watchdog_register_device(&priv->wdev);
 250         if (ret < 0)
 251                 goto out_pm_disable;
 252
 253         return 0;
 254
 255  out_pm_disable:
 256         pm_runtime_disable(&pdev->dev);
 257         return ret;
 258 }
 259
 260 static int rwdt_remove(struct platform_device *pdev)
 261 {
 262         struct rwdt_priv *priv = platform_get_drvdata(pdev);
 263
 264         watchdog_unregister_device(&priv->wdev);
 265         pm_runtime_disable(&pdev->dev);
 266
 267         return 0;
 268 }
 269
 270 static int __maybe_unused rwdt_suspend(struct device *dev)
 271 {
 272         struct rwdt_priv *priv = dev_get_drvdata(dev);
 273
 274         if (watchdog_active(&priv->wdev)) {
 275                 priv->time_left = readw(priv->base + RWTCNT);
 276                 rwdt_stop(&priv->wdev);
 277         }
 278         return 0;
 279 }
 280
 281 static int __maybe_unused rwdt_resume(struct device *dev)
 282 {
 283         struct rwdt_priv *priv = dev_get_drvdata(dev);
 284
 285         if (watchdog_active(&priv->wdev)) {
 286                 rwdt_start(&priv->wdev);
 287                 rwdt_write(priv, priv->time_left, RWTCNT);
 288         }
 289         return 0;
 290 }
 291
 292 static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
 293
 294 static const struct of_device_id rwdt_ids[] = {
 295         { .compatible = "renesas,rcar-gen2-wdt", },
 296         { .compatible = "renesas,rcar-gen3-wdt", },
 297         { /* sentinel */ }
 298 };
 299 MODULE_DEVICE_TABLE(of, rwdt_ids);
 300
 301 static struct platform_driver rwdt_driver = {
 302         .driver = {
 303                 .name = "renesas_wdt",
 304                 .of_match_table = rwdt_ids,
 305                 .pm = &rwdt_pm_ops,
 306         },
 307         .probe = rwdt_probe,
 308         .remove = rwdt_remove,
 309 };
 310 module_platform_driver(rwdt_driver);
 311
 312 MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
 313 MODULE_LICENSE("GPL v2");
 314 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");