drivers/watchdog/qcom-wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  */
   4 #include <linux/bits.h>
   5 #include <linux/clk.h>
   6 #include <linux/delay.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/watchdog.h>
  14 #include <linux/of_device.h>
  15
  16 enum wdt_reg {
  17         WDT_RST,
  18         WDT_EN,
  19         WDT_STS,
  20         WDT_BARK_TIME,
  21         WDT_BITE_TIME,
  22 };
  23
  24 #define QCOM_WDT_ENABLE         BIT(0)
  25
  26 static const u32 reg_offset_data_apcs_tmr[] = {
  27         [WDT_RST] = 0x38,
  28         [WDT_EN] = 0x40,
  29         [WDT_STS] = 0x44,
  30         [WDT_BARK_TIME] = 0x4C,
  31         [WDT_BITE_TIME] = 0x5C,
  32 };
  33
  34 static const u32 reg_offset_data_kpss[] = {
  35         [WDT_RST] = 0x4,
  36         [WDT_EN] = 0x8,
  37         [WDT_STS] = 0xC,
  38         [WDT_BARK_TIME] = 0x10,
  39         [WDT_BITE_TIME] = 0x14,
  40 };
  41
  42 struct qcom_wdt {
  43         struct watchdog_device  wdd;
  44         unsigned long           rate;
  45         void __iomem            *base;
  46         const u32               *layout;
  47 };
  48
  49 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
  50 {
  51         return wdt->base + wdt->layout[reg];
  52 }
  53
  54 static inline
  55 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
  56 {
  57         return container_of(wdd, struct qcom_wdt, wdd);
  58 }
  59
  60 static irqreturn_t qcom_wdt_isr(int irq, void *arg)
  61 {
  62         struct watchdog_device *wdd = arg;
  63
  64         watchdog_notify_pretimeout(wdd);
  65
  66         return IRQ_HANDLED;
  67 }
  68
  69 static int qcom_wdt_start(struct watchdog_device *wdd)
  70 {
  71         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  72         unsigned int bark = wdd->timeout - wdd->pretimeout;
  73
  74         writel(0, wdt_addr(wdt, WDT_EN));
  75         writel(1, wdt_addr(wdt, WDT_RST));
  76         writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
  77         writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
  78         writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
  79         return 0;
  80 }
  81
  82 static int qcom_wdt_stop(struct watchdog_device *wdd)
  83 {
  84         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  85
  86         writel(0, wdt_addr(wdt, WDT_EN));
  87         return 0;
  88 }
  89
  90 static int qcom_wdt_ping(struct watchdog_device *wdd)
  91 {
  92         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  93
  94         writel(1, wdt_addr(wdt, WDT_RST));
  95         return 0;
  96 }
  97
  98 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
  99                                 unsigned int timeout)
 100 {
 101         wdd->timeout = timeout;
 102         return qcom_wdt_start(wdd);
 103 }
 104
 105 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
 106                                    unsigned int timeout)
 107 {
 108         wdd->pretimeout = timeout;
 109         return qcom_wdt_start(wdd);
 110 }
 111
 112 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
 113                             void *data)
 114 {
 115         struct qcom_wdt *wdt = to_qcom_wdt(wdd);
 116         u32 timeout;
 117
 118         /*
 119          * Trigger watchdog bite:
 120          *    Setup BITE_TIME to be 128ms, and enable WDT.
 121          */
 122         timeout = 128 * wdt->rate / 1000;
 123
 124         writel(0, wdt_addr(wdt, WDT_EN));
 125         writel(1, wdt_addr(wdt, WDT_RST));
 126         writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
 127         writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
 128         writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
 129
 130         /*
 131          * Actually make sure the above sequence hits hardware before sleeping.
 132          */
 133         wmb();
 134
 135         mdelay(150);
 136         return 0;
 137 }
 138
 139 static const struct watchdog_ops qcom_wdt_ops = {
 140         .start          = qcom_wdt_start,
 141         .stop           = qcom_wdt_stop,
 142         .ping           = qcom_wdt_ping,
 143         .set_timeout    = qcom_wdt_set_timeout,
 144         .set_pretimeout = qcom_wdt_set_pretimeout,
 145         .restart        = qcom_wdt_restart,
 146         .owner          = THIS_MODULE,
 147 };
 148
 149 static const struct watchdog_info qcom_wdt_info = {
 150         .options        = WDIOF_KEEPALIVEPING
 151                         | WDIOF_MAGICCLOSE
 152                         | WDIOF_SETTIMEOUT
 153                         | WDIOF_CARDRESET,
 154         .identity       = KBUILD_MODNAME,
 155 };
 156
 157 static const struct watchdog_info qcom_wdt_pt_info = {
 158         .options        = WDIOF_KEEPALIVEPING
 159                         | WDIOF_MAGICCLOSE
 160                         | WDIOF_SETTIMEOUT
 161                         | WDIOF_PRETIMEOUT
 162                         | WDIOF_CARDRESET,
 163         .identity       = KBUILD_MODNAME,
 164 };
 165
 166 static void qcom_clk_disable_unprepare(void *data)
 167 {
 168         clk_disable_unprepare(data);
 169 }
 170
 171 static int qcom_wdt_probe(struct platform_device *pdev)
 172 {
 173         struct device *dev = &pdev->dev;
 174         struct qcom_wdt *wdt;
 175         struct resource *res;
 176         struct device_node *np = dev->of_node;
 177         const u32 *regs;
 178         u32 percpu_offset;
 179         int irq, ret;
 180         struct clk *clk;
 181
 182         regs = of_device_get_match_data(dev);
 183         if (!regs) {
 184                 dev_err(dev, "Unsupported QCOM WDT module\n");
 185                 return -ENODEV;
 186         }
 187
 188         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 189         if (!wdt)
 190                 return -ENOMEM;
 191
 192         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 193         if (!res)
 194                 return -ENOMEM;
 195
 196         /* We use CPU0's DGT for the watchdog */
 197         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 198                 percpu_offset = 0;
 199
 200         res->start += percpu_offset;
 201         res->end += percpu_offset;
 202
 203         wdt->base = devm_ioremap_resource(dev, res);
 204         if (IS_ERR(wdt->base))
 205                 return PTR_ERR(wdt->base);
 206
 207         clk = devm_clk_get(dev, NULL);
 208         if (IS_ERR(clk)) {
 209                 dev_err(dev, "failed to get input clock\n");
 210                 return PTR_ERR(clk);
 211         }
 212
 213         ret = clk_prepare_enable(clk);
 214         if (ret) {
 215                 dev_err(dev, "failed to setup clock\n");
 216                 return ret;
 217         }
 218         ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
 219         if (ret)
 220                 return ret;
 221
 222         /*
 223          * We use the clock rate to calculate the max timeout, so ensure it's
 224          * not zero to avoid a divide-by-zero exception.
 225          *
 226          * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
 227          * that it would bite before a second elapses it's usefulness is
 228          * limited.  Bail if this is the case.
 229          */
 230         wdt->rate = clk_get_rate(clk);
 231         if (wdt->rate == 0 ||
 232             wdt->rate > 0x10000000U) {
 233                 dev_err(dev, "invalid clock rate\n");
 234                 return -EINVAL;
 235         }
 236
 237         /* check if there is pretimeout support */
 238         irq = platform_get_irq_optional(pdev, 0);
 239         if (irq > 0) {
 240                 ret = devm_request_irq(dev, irq, qcom_wdt_isr,
 241                                        IRQF_TRIGGER_RISING,
 242                                        "wdt_bark", &wdt->wdd);
 243                 if (ret)
 244                         return ret;
 245
 246                 wdt->wdd.info = &qcom_wdt_pt_info;
 247                 wdt->wdd.pretimeout = 1;
 248         } else {
 249                 if (irq == -EPROBE_DEFER)
 250                         return -EPROBE_DEFER;
 251
 252                 wdt->wdd.info = &qcom_wdt_info;
 253         }
 254
 255         wdt->wdd.ops = &qcom_wdt_ops;
 256         wdt->wdd.min_timeout = 1;
 257         wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
 258         wdt->wdd.parent = dev;
 259         wdt->layout = regs;
 260
 261         if (readl(wdt_addr(wdt, WDT_STS)) & 1)
 262                 wdt->wdd.bootstatus = WDIOF_CARDRESET;
 263
 264         /*
 265          * If 'timeout-sec' unspecified in devicetree, assume a 30 second
 266          * default, unless the max timeout is less than 30 seconds, then use
 267          * the max instead.
 268          */
 269         wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
 270         watchdog_init_timeout(&wdt->wdd, 0, dev);
 271
 272         ret = devm_watchdog_register_device(dev, &wdt->wdd);
 273         if (ret)
 274                 return ret;
 275
 276         platform_set_drvdata(pdev, wdt);
 277         return 0;
 278 }
 279
 280 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
 281 {
 282         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 283
 284         if (watchdog_active(&wdt->wdd))
 285                 qcom_wdt_stop(&wdt->wdd);
 286
 287         return 0;
 288 }
 289
 290 static int __maybe_unused qcom_wdt_resume(struct device *dev)
 291 {
 292         struct qcom_wdt *wdt = dev_get_drvdata(dev);
 293
 294         if (watchdog_active(&wdt->wdd))
 295                 qcom_wdt_start(&wdt->wdd);
 296
 297         return 0;
 298 }
 299
 300 static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
 301
 302 static const struct of_device_id qcom_wdt_of_table[] = {
 303         { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
 304         { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
 305         { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
 306         { },
 307 };
 308 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
 309
 310 static struct platform_driver qcom_watchdog_driver = {
 311         .probe  = qcom_wdt_probe,
 312         .driver = {
 313                 .name           = KBUILD_MODNAME,
 314                 .of_match_table = qcom_wdt_of_table,
 315                 .pm             = &qcom_wdt_pm_ops,
 316         },
 317 };
 318 module_platform_driver(qcom_watchdog_driver);
 319
 320 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
 321 MODULE_LICENSE("GPL v2");