1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/char/watchdog/ixp4xx_wdt.c
5 * Watchdog driver for Intel IXP4xx network processors
7 * Author: Deepak Saxena <dsaxena@plexity.net>
8 * Author: Linus Walleij <linus.walleij@linaro.org>
10 * Copyright 2004 (c) MontaVista, Software, Inc.
11 * Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/watchdog.h>
18 #include <linux/bits.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/soc/ixp4xx/cpu.h>
24 struct watchdog_device wdd;
29 /* Fallback if we do not have a clock for this */
30 #define IXP4XX_TIMER_FREQ 66666000
32 /* Registers after the timer registers */
33 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
34 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
35 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
36 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
38 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
39 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
40 #define IXP4XX_WDT_KEY 0x0000482E
41 #define IXP4XX_WDT_RESET_ENABLE 0x00000001
42 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002
43 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004
46 struct ixp4xx_wdt *to_ixp4xx_wdt(struct watchdog_device *wdd)
48 return container_of(wdd, struct ixp4xx_wdt, wdd);
51 static int ixp4xx_wdt_start(struct watchdog_device *wdd)
53 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
55 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
56 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
57 __raw_writel(wdd->timeout * iwdt->rate,
58 iwdt->base + IXP4XX_OSWT_OFFSET);
59 __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
60 iwdt->base + IXP4XX_OSWE_OFFSET);
61 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
66 static int ixp4xx_wdt_stop(struct watchdog_device *wdd)
68 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
70 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
71 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET);
72 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET);
77 static int ixp4xx_wdt_set_timeout(struct watchdog_device *wdd,
80 wdd->timeout = timeout;
81 if (watchdog_active(wdd))
82 ixp4xx_wdt_start(wdd);
87 static int ixp4xx_wdt_restart(struct watchdog_device *wdd,
88 unsigned long action, void *data)
90 struct ixp4xx_wdt *iwdt = to_ixp4xx_wdt(wdd);
92 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET);
93 __raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET);
94 __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE,
95 iwdt->base + IXP4XX_OSWE_OFFSET);
100 static const struct watchdog_ops ixp4xx_wdt_ops = {
101 .start = ixp4xx_wdt_start,
102 .stop = ixp4xx_wdt_stop,
103 .set_timeout = ixp4xx_wdt_set_timeout,
104 .restart = ixp4xx_wdt_restart,
105 .owner = THIS_MODULE,
109 * The A0 version of the IXP422 had a bug in the watchdog making
110 * is useless, but we still need to use it to restart the system
111 * as it is the only way, so in this special case we register a
112 * "dummy" watchdog that doesn't really work, but will support
113 * the restart operation.
115 static int ixp4xx_wdt_dummy(struct watchdog_device *wdd)
120 static const struct watchdog_ops ixp4xx_wdt_restart_only_ops = {
121 .start = ixp4xx_wdt_dummy,
122 .stop = ixp4xx_wdt_dummy,
123 .restart = ixp4xx_wdt_restart,
124 .owner = THIS_MODULE,
127 static const struct watchdog_info ixp4xx_wdt_info = {
128 .options = WDIOF_KEEPALIVEPING
131 .identity = KBUILD_MODNAME,
134 /* Devres-handled clock disablement */
135 static void ixp4xx_clock_action(void *d)
137 clk_disable_unprepare(d);
140 static int ixp4xx_wdt_probe(struct platform_device *pdev)
142 static const struct watchdog_ops *iwdt_ops;
143 struct device *dev = &pdev->dev;
144 struct ixp4xx_wdt *iwdt;
148 if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
149 dev_info(dev, "Rev. A0 IXP42x CPU detected - only restart supported\n");
150 iwdt_ops = &ixp4xx_wdt_restart_only_ops;
152 iwdt_ops = &ixp4xx_wdt_ops;
155 iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
158 iwdt->base = (void __iomem *)dev->platform_data;
161 * Retrieve rate from a fixed clock from the device tree if
162 * the parent has that, else use the default clock rate.
164 clk = devm_clk_get(dev->parent, NULL);
166 ret = clk_prepare_enable(clk);
169 ret = devm_add_action_or_reset(dev, ixp4xx_clock_action, clk);
172 iwdt->rate = clk_get_rate(clk);
175 iwdt->rate = IXP4XX_TIMER_FREQ;
177 iwdt->wdd.info = &ixp4xx_wdt_info;
178 iwdt->wdd.ops = iwdt_ops;
179 iwdt->wdd.min_timeout = 1;
180 iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
181 iwdt->wdd.parent = dev;
182 /* Default to 60 seconds */
183 iwdt->wdd.timeout = 60U;
184 watchdog_init_timeout(&iwdt->wdd, 0, dev);
186 if (__raw_readl(iwdt->base + IXP4XX_OSST_OFFSET) &
187 IXP4XX_OSST_TIMER_WARM_RESET)
188 iwdt->wdd.bootstatus = WDIOF_CARDRESET;
190 ret = devm_watchdog_register_device(dev, &iwdt->wdd);
194 dev_info(dev, "IXP4xx watchdog available\n");
199 static struct platform_driver ixp4xx_wdt_driver = {
200 .probe = ixp4xx_wdt_probe,
202 .name = "ixp4xx-watchdog",
205 module_platform_driver(ixp4xx_wdt_driver);
207 MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
208 MODULE_DESCRIPTION("IXP4xx Network Processor Watchdog");
209 MODULE_LICENSE("GPL");