2 * Copyright 2016 IBM Corporation
4 * Joel Stanley <joel@jms.id.au>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/watchdog.h>
21 struct watchdog_device wdd;
26 struct aspeed_wdt_config {
27 u32 ext_pulse_width_mask;
30 static const struct aspeed_wdt_config ast2400_config = {
31 .ext_pulse_width_mask = 0xff,
34 static const struct aspeed_wdt_config ast2500_config = {
35 .ext_pulse_width_mask = 0xfffff,
38 static const struct of_device_id aspeed_wdt_of_table[] = {
39 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
40 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
41 { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
44 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
46 #define WDT_STATUS 0x00
47 #define WDT_RELOAD_VALUE 0x04
48 #define WDT_RESTART 0x08
50 #define WDT_CTRL_BOOT_SECONDARY BIT(7)
51 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
52 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
53 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
54 #define WDT_CTRL_1MHZ_CLK BIT(4)
55 #define WDT_CTRL_WDT_EXT BIT(3)
56 #define WDT_CTRL_WDT_INTR BIT(2)
57 #define WDT_CTRL_RESET_SYSTEM BIT(1)
58 #define WDT_CTRL_ENABLE BIT(0)
61 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
62 * enabled), specifically:
65 * * Drive mode: push-pull vs open-drain
66 * * Polarity: Active high or active low
68 * Pulse duration configuration is available on both the AST2400 and AST2500,
69 * though the field changes between SoCs:
74 * This difference is captured in struct aspeed_wdt_config.
76 * The AST2500 exposes the drive mode and polarity options, but not in a
77 * regular fashion. For read purposes, bit 31 represents active high or low,
78 * and bit 30 represents push-pull or open-drain. With respect to write, magic
79 * values need to be written to the top byte to change the state of the drive
80 * mode and polarity bits. Any other value written to the top byte has no
81 * effect on the state of the drive mode or polarity bits. However, the pulse
82 * width value must be preserved (as desired) if written.
84 #define WDT_RESET_WIDTH 0x18
85 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
86 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
87 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
88 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
89 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
90 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
92 #define WDT_RESTART_MAGIC 0x4755
94 /* 32 bits at 1MHz, in milliseconds */
95 #define WDT_MAX_TIMEOUT_MS 4294967
96 #define WDT_DEFAULT_TIMEOUT 30
97 #define WDT_RATE_1MHZ 1000000
99 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
101 return container_of(wdd, struct aspeed_wdt, wdd);
104 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
106 wdt->ctrl |= WDT_CTRL_ENABLE;
108 writel(0, wdt->base + WDT_CTRL);
109 writel(count, wdt->base + WDT_RELOAD_VALUE);
110 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
111 writel(wdt->ctrl, wdt->base + WDT_CTRL);
114 static int aspeed_wdt_start(struct watchdog_device *wdd)
116 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
118 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
123 static int aspeed_wdt_stop(struct watchdog_device *wdd)
125 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
127 wdt->ctrl &= ~WDT_CTRL_ENABLE;
128 writel(wdt->ctrl, wdt->base + WDT_CTRL);
133 static int aspeed_wdt_ping(struct watchdog_device *wdd)
135 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
137 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
142 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
143 unsigned int timeout)
145 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
148 wdd->timeout = timeout;
150 actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
152 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
153 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
158 static int aspeed_wdt_restart(struct watchdog_device *wdd,
159 unsigned long action, void *data)
161 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
163 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
164 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
171 static const struct watchdog_ops aspeed_wdt_ops = {
172 .start = aspeed_wdt_start,
173 .stop = aspeed_wdt_stop,
174 .ping = aspeed_wdt_ping,
175 .set_timeout = aspeed_wdt_set_timeout,
176 .restart = aspeed_wdt_restart,
177 .owner = THIS_MODULE,
180 static const struct watchdog_info aspeed_wdt_info = {
181 .options = WDIOF_KEEPALIVEPING
184 .identity = KBUILD_MODNAME,
187 static int aspeed_wdt_probe(struct platform_device *pdev)
189 const struct aspeed_wdt_config *config;
190 const struct of_device_id *ofdid;
191 struct aspeed_wdt *wdt;
192 struct resource *res;
193 struct device_node *np;
194 const char *reset_type;
198 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
203 wdt->base = devm_ioremap_resource(&pdev->dev, res);
204 if (IS_ERR(wdt->base))
205 return PTR_ERR(wdt->base);
207 wdt->wdd.info = &aspeed_wdt_info;
208 wdt->wdd.ops = &aspeed_wdt_ops;
209 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
210 wdt->wdd.parent = &pdev->dev;
212 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
213 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
215 np = pdev->dev.of_node;
217 ofdid = of_match_node(aspeed_wdt_of_table, np);
220 config = ofdid->data;
224 * - ast2400 wdt can run at PCLK, or 1MHz
225 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
226 * - ast2600 always runs at 1MHz
228 * Set the ast2400 to run at 1MHz as it simplifies the driver.
230 if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
231 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
234 * Control reset on a per-device basis to ensure the
235 * host is not affected by a BMC reboot
237 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
239 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
241 if (!strcmp(reset_type, "cpu"))
242 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
243 WDT_CTRL_RESET_SYSTEM;
244 else if (!strcmp(reset_type, "soc"))
245 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
246 WDT_CTRL_RESET_SYSTEM;
247 else if (!strcmp(reset_type, "system"))
248 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
249 WDT_CTRL_RESET_SYSTEM;
250 else if (strcmp(reset_type, "none"))
253 if (of_property_read_bool(np, "aspeed,external-signal"))
254 wdt->ctrl |= WDT_CTRL_WDT_EXT;
255 if (of_property_read_bool(np, "aspeed,alt-boot"))
256 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
258 writel(wdt->ctrl, wdt->base + WDT_CTRL);
260 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
261 aspeed_wdt_start(&wdt->wdd);
262 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
265 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
266 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
267 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
269 reg &= config->ext_pulse_width_mask;
270 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
271 reg |= WDT_PUSH_PULL_MAGIC;
273 reg |= WDT_OPEN_DRAIN_MAGIC;
275 writel(reg, wdt->base + WDT_RESET_WIDTH);
277 reg &= config->ext_pulse_width_mask;
278 if (of_property_read_bool(np, "aspeed,ext-active-high"))
279 reg |= WDT_ACTIVE_HIGH_MAGIC;
281 reg |= WDT_ACTIVE_LOW_MAGIC;
283 writel(reg, wdt->base + WDT_RESET_WIDTH);
286 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
287 u32 max_duration = config->ext_pulse_width_mask + 1;
289 if (duration == 0 || duration > max_duration) {
290 dev_err(&pdev->dev, "Invalid pulse duration: %uus\n",
292 duration = max(1U, min(max_duration, duration));
293 dev_info(&pdev->dev, "Pulse duration set to %uus\n",
298 * The watchdog is always configured with a 1MHz source, so
299 * there is no need to scale the microsecond value. However we
300 * need to offset it - from the datasheet:
302 * "This register decides the asserting duration of wdt_ext and
303 * wdt_rstarm signal. The default value is 0xFF. It means the
304 * default asserting duration of wdt_ext and wdt_rstarm is
307 * This implies a value of 0 gives a 1us pulse.
309 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
312 ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
314 dev_err(&pdev->dev, "failed to register\n");
321 static struct platform_driver aspeed_watchdog_driver = {
322 .probe = aspeed_wdt_probe,
324 .name = KBUILD_MODNAME,
325 .of_match_table = of_match_ptr(aspeed_wdt_of_table),
328 module_platform_driver(aspeed_watchdog_driver);
330 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
331 MODULE_LICENSE("GPL");