drivers/watchdog/aspeed_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2016 IBM Corporation
   4  *
   5  * Joel Stanley <joel@jms.id.au>
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/kstrtox.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/watchdog.h>
  19
  20 static bool nowayout = WATCHDOG_NOWAYOUT;
  21 module_param(nowayout, bool, 0);
  22 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  23                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  24
  25 struct aspeed_wdt_config {
  26         u32 ext_pulse_width_mask;
  27         u32 irq_shift;
  28         u32 irq_mask;
  29 };
  30
  31 struct aspeed_wdt {
  32         struct watchdog_device  wdd;
  33         void __iomem            *base;
  34         u32                     ctrl;
  35         const struct aspeed_wdt_config *cfg;
  36 };
  37
  38 static const struct aspeed_wdt_config ast2400_config = {
  39         .ext_pulse_width_mask = 0xff,
  40         .irq_shift = 0,
  41         .irq_mask = 0,
  42 };
  43
  44 static const struct aspeed_wdt_config ast2500_config = {
  45         .ext_pulse_width_mask = 0xfffff,
  46         .irq_shift = 12,
  47         .irq_mask = GENMASK(31, 12),
  48 };
  49
  50 static const struct aspeed_wdt_config ast2600_config = {
  51         .ext_pulse_width_mask = 0xfffff,
  52         .irq_shift = 0,
  53         .irq_mask = GENMASK(31, 10),
  54 };
  55
  56 static const struct of_device_id aspeed_wdt_of_table[] = {
  57         { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
  58         { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
  59         { .compatible = "aspeed,ast2600-wdt", .data = &ast2600_config },
  60         { },
  61 };
  62 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
  63
  64 #define WDT_STATUS              0x00
  65 #define WDT_RELOAD_VALUE        0x04
  66 #define WDT_RESTART             0x08
  67 #define WDT_CTRL                0x0C
  68 #define   WDT_CTRL_BOOT_SECONDARY       BIT(7)
  69 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
  70 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
  71 #define   WDT_CTRL_RESET_MODE_ARM_CPU   (0x10 << 5)
  72 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
  73 #define   WDT_CTRL_WDT_EXT              BIT(3)
  74 #define   WDT_CTRL_WDT_INTR             BIT(2)
  75 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
  76 #define   WDT_CTRL_ENABLE               BIT(0)
  77 #define WDT_TIMEOUT_STATUS      0x10
  78 #define   WDT_TIMEOUT_STATUS_IRQ                BIT(2)
  79 #define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY     BIT(1)
  80 #define WDT_CLEAR_TIMEOUT_STATUS        0x14
  81 #define   WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION     BIT(0)
  82 #define WDT_RESET_MASK1         0x1c
  83 #define WDT_RESET_MASK2         0x20
  84
  85 /*
  86  * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
  87  * enabled), specifically:
  88  *
  89  * * Pulse duration
  90  * * Drive mode: push-pull vs open-drain
  91  * * Polarity: Active high or active low
  92  *
  93  * Pulse duration configuration is available on both the AST2400 and AST2500,
  94  * though the field changes between SoCs:
  95  *
  96  * AST2400: Bits 7:0
  97  * AST2500: Bits 19:0
  98  *
  99  * This difference is captured in struct aspeed_wdt_config.
 100  *
 101  * The AST2500 exposes the drive mode and polarity options, but not in a
 102  * regular fashion. For read purposes, bit 31 represents active high or low,
 103  * and bit 30 represents push-pull or open-drain. With respect to write, magic
 104  * values need to be written to the top byte to change the state of the drive
 105  * mode and polarity bits. Any other value written to the top byte has no
 106  * effect on the state of the drive mode or polarity bits. However, the pulse
 107  * width value must be preserved (as desired) if written.
 108  */
 109 #define WDT_RESET_WIDTH         0x18
 110 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
 111 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
 112 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
 113 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
 114 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
 115 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
 116
 117 #define WDT_RESTART_MAGIC       0x4755
 118
 119 /* 32 bits at 1MHz, in milliseconds */
 120 #define WDT_MAX_TIMEOUT_MS      4294967
 121 #define WDT_DEFAULT_TIMEOUT     30
 122 #define WDT_RATE_1MHZ           1000000
 123
 124 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
 125 {
 126         return container_of(wdd, struct aspeed_wdt, wdd);
 127 }
 128
 129 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
 130 {
 131         wdt->ctrl |= WDT_CTRL_ENABLE;
 132
 133         writel(0, wdt->base + WDT_CTRL);
 134         writel(count, wdt->base + WDT_RELOAD_VALUE);
 135         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 136         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 137 }
 138
 139 static int aspeed_wdt_start(struct watchdog_device *wdd)
 140 {
 141         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 142
 143         aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
 144
 145         return 0;
 146 }
 147
 148 static int aspeed_wdt_stop(struct watchdog_device *wdd)
 149 {
 150         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 151
 152         wdt->ctrl &= ~WDT_CTRL_ENABLE;
 153         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 154
 155         return 0;
 156 }
 157
 158 static int aspeed_wdt_ping(struct watchdog_device *wdd)
 159 {
 160         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 161
 162         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 163
 164         return 0;
 165 }
 166
 167 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
 168                                   unsigned int timeout)
 169 {
 170         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 171         u32 actual;
 172
 173         wdd->timeout = timeout;
 174
 175         actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
 176
 177         writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
 178         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 179
 180         return 0;
 181 }
 182
 183 static int aspeed_wdt_set_pretimeout(struct watchdog_device *wdd,
 184                                      unsigned int pretimeout)
 185 {
 186         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 187         u32 actual = pretimeout * WDT_RATE_1MHZ;
 188         u32 s = wdt->cfg->irq_shift;
 189         u32 m = wdt->cfg->irq_mask;
 190
 191         wdd->pretimeout = pretimeout;
 192         wdt->ctrl &= ~m;
 193         if (pretimeout)
 194                 wdt->ctrl |= ((actual << s) & m) | WDT_CTRL_WDT_INTR;
 195         else
 196                 wdt->ctrl &= ~WDT_CTRL_WDT_INTR;
 197
 198         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 199
 200         return 0;
 201 }
 202
 203 static int aspeed_wdt_restart(struct watchdog_device *wdd,
 204                               unsigned long action, void *data)
 205 {
 206         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 207
 208         wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
 209         aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
 210
 211         mdelay(1000);
 212
 213         return 0;
 214 }
 215
 216 /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
 217 static ssize_t access_cs0_show(struct device *dev,
 218                                struct device_attribute *attr, char *buf)
 219 {
 220         struct aspeed_wdt *wdt = dev_get_drvdata(dev);
 221         u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 222
 223         return sysfs_emit(buf, "%u\n",
 224                           !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
 225 }
 226
 227 static ssize_t access_cs0_store(struct device *dev,
 228                                 struct device_attribute *attr, const char *buf,
 229                                 size_t size)
 230 {
 231         struct aspeed_wdt *wdt = dev_get_drvdata(dev);
 232         unsigned long val;
 233
 234         if (kstrtoul(buf, 10, &val))
 235                 return -EINVAL;
 236
 237         if (val)
 238                 writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
 239                        wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
 240
 241         return size;
 242 }
 243
 244 /*
 245  * This attribute exists only if the system has booted from the alternate
 246  * flash with 'alt-boot' option.
 247  *
 248  * At alternate flash the 'access_cs0' sysfs node provides:
 249  *   ast2400: a way to get access to the primary SPI flash chip at CS0
 250  *            after booting from the alternate chip at CS1.
 251  *   ast2500: a way to restore the normal address mapping from
 252  *            (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
 253  *
 254  * Clearing the boot code selection and timeout counter also resets to the
 255  * initial state the chip select line mapping. When the SoC is in normal
 256  * mapping state (i.e. booted from CS0), clearing those bits does nothing for
 257  * both versions of the SoC. For alternate boot mode (booted from CS1 due to
 258  * wdt2 expiration) the behavior differs as described above.
 259  *
 260  * This option can be used with wdt2 (watchdog1) only.
 261  */
 262 static DEVICE_ATTR_RW(access_cs0);
 263
 264 static struct attribute *bswitch_attrs[] = {
 265         &dev_attr_access_cs0.attr,
 266         NULL
 267 };
 268 ATTRIBUTE_GROUPS(bswitch);
 269
 270 static const struct watchdog_ops aspeed_wdt_ops = {
 271         .start          = aspeed_wdt_start,
 272         .stop           = aspeed_wdt_stop,
 273         .ping           = aspeed_wdt_ping,
 274         .set_timeout    = aspeed_wdt_set_timeout,
 275         .set_pretimeout = aspeed_wdt_set_pretimeout,
 276         .restart        = aspeed_wdt_restart,
 277         .owner          = THIS_MODULE,
 278 };
 279
 280 static const struct watchdog_info aspeed_wdt_info = {
 281         .options        = WDIOF_KEEPALIVEPING
 282                         | WDIOF_MAGICCLOSE
 283                         | WDIOF_SETTIMEOUT,
 284         .identity       = KBUILD_MODNAME,
 285 };
 286
 287 static const struct watchdog_info aspeed_wdt_pretimeout_info = {
 288         .options        = WDIOF_KEEPALIVEPING
 289                         | WDIOF_PRETIMEOUT
 290                         | WDIOF_MAGICCLOSE
 291                         | WDIOF_SETTIMEOUT,
 292         .identity       = KBUILD_MODNAME,
 293 };
 294
 295 static irqreturn_t aspeed_wdt_irq(int irq, void *arg)
 296 {
 297         struct watchdog_device *wdd = arg;
 298         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 299         u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 300
 301         if (status & WDT_TIMEOUT_STATUS_IRQ)
 302                 watchdog_notify_pretimeout(wdd);
 303
 304         return IRQ_HANDLED;
 305 }
 306
 307 static int aspeed_wdt_probe(struct platform_device *pdev)
 308 {
 309         struct device *dev = &pdev->dev;
 310         const struct of_device_id *ofdid;
 311         struct aspeed_wdt *wdt;
 312         struct device_node *np;
 313         const char *reset_type;
 314         u32 duration;
 315         u32 status;
 316         int ret;
 317
 318         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 319         if (!wdt)
 320                 return -ENOMEM;
 321
 322         np = dev->of_node;
 323
 324         ofdid = of_match_node(aspeed_wdt_of_table, np);
 325         if (!ofdid)
 326                 return -EINVAL;
 327         wdt->cfg = ofdid->data;
 328
 329         wdt->base = devm_platform_ioremap_resource(pdev, 0);
 330         if (IS_ERR(wdt->base))
 331                 return PTR_ERR(wdt->base);
 332
 333         wdt->wdd.info = &aspeed_wdt_info;
 334
 335         if (wdt->cfg->irq_mask) {
 336                 int irq = platform_get_irq_optional(pdev, 0);
 337
 338                 if (irq > 0) {
 339                         ret = devm_request_irq(dev, irq, aspeed_wdt_irq,
 340                                                IRQF_SHARED, dev_name(dev),
 341                                                wdt);
 342                         if (ret)
 343                                 return ret;
 344
 345                         wdt->wdd.info = &aspeed_wdt_pretimeout_info;
 346                 }
 347         }
 348
 349         wdt->wdd.ops = &aspeed_wdt_ops;
 350         wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
 351         wdt->wdd.parent = dev;
 352
 353         wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
 354         watchdog_init_timeout(&wdt->wdd, 0, dev);
 355
 356         watchdog_set_nowayout(&wdt->wdd, nowayout);
 357
 358         /*
 359          * On clock rates:
 360          *  - ast2400 wdt can run at PCLK, or 1MHz
 361          *  - ast2500 only runs at 1MHz, hard coding bit 4 to 1
 362          *  - ast2600 always runs at 1MHz
 363          *
 364          * Set the ast2400 to run at 1MHz as it simplifies the driver.
 365          */
 366         if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
 367                 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
 368
 369         /*
 370          * Control reset on a per-device basis to ensure the
 371          * host is not affected by a BMC reboot
 372          */
 373         ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
 374         if (ret) {
 375                 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
 376         } else {
 377                 if (!strcmp(reset_type, "cpu"))
 378                         wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
 379                                      WDT_CTRL_RESET_SYSTEM;
 380                 else if (!strcmp(reset_type, "soc"))
 381                         wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
 382                                      WDT_CTRL_RESET_SYSTEM;
 383                 else if (!strcmp(reset_type, "system"))
 384                         wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
 385                                      WDT_CTRL_RESET_SYSTEM;
 386                 else if (strcmp(reset_type, "none"))
 387                         return -EINVAL;
 388         }
 389         if (of_property_read_bool(np, "aspeed,external-signal"))
 390                 wdt->ctrl |= WDT_CTRL_WDT_EXT;
 391         if (of_property_read_bool(np, "aspeed,alt-boot"))
 392                 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
 393
 394         if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
 395                 /*
 396                  * The watchdog is running, but invoke aspeed_wdt_start() to
 397                  * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
 398                  * configuration conforms to the driver's expectations.
 399                  * Primarily, ensure we're using the 1MHz clock source.
 400                  */
 401                 aspeed_wdt_start(&wdt->wdd);
 402                 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
 403         }
 404
 405         if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
 406                 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
 407                 u32 reset_mask[2];
 408                 size_t nrstmask = of_device_is_compatible(np, "aspeed,ast2600-wdt") ? 2 : 1;
 409                 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
 410
 411                 reg &= wdt->cfg->ext_pulse_width_mask;
 412                 if (of_property_read_bool(np, "aspeed,ext-active-high"))
 413                         reg |= WDT_ACTIVE_HIGH_MAGIC;
 414                 else
 415                         reg |= WDT_ACTIVE_LOW_MAGIC;
 416
 417                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 418
 419                 reg &= wdt->cfg->ext_pulse_width_mask;
 420                 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
 421                         reg |= WDT_PUSH_PULL_MAGIC;
 422                 else
 423                         reg |= WDT_OPEN_DRAIN_MAGIC;
 424
 425                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 426
 427                 ret = of_property_read_u32_array(np, "aspeed,reset-mask", reset_mask, nrstmask);
 428                 if (!ret) {
 429                         writel(reset_mask[0], wdt->base + WDT_RESET_MASK1);
 430                         if (nrstmask > 1)
 431                                 writel(reset_mask[1], wdt->base + WDT_RESET_MASK2);
 432                 }
 433         }
 434
 435         if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
 436                 u32 max_duration = wdt->cfg->ext_pulse_width_mask + 1;
 437
 438                 if (duration == 0 || duration > max_duration) {
 439                         dev_err(dev, "Invalid pulse duration: %uus\n",
 440                                 duration);
 441                         duration = max(1U, min(max_duration, duration));
 442                         dev_info(dev, "Pulse duration set to %uus\n",
 443                                  duration);
 444                 }
 445
 446                 /*
 447                  * The watchdog is always configured with a 1MHz source, so
 448                  * there is no need to scale the microsecond value. However we
 449                  * need to offset it - from the datasheet:
 450                  *
 451                  * "This register decides the asserting duration of wdt_ext and
 452                  * wdt_rstarm signal. The default value is 0xFF. It means the
 453                  * default asserting duration of wdt_ext and wdt_rstarm is
 454                  * 256us."
 455                  *
 456                  * This implies a value of 0 gives a 1us pulse.
 457                  */
 458                 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
 459         }
 460
 461         status = readl(wdt->base + WDT_TIMEOUT_STATUS);
 462         if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
 463                 wdt->wdd.bootstatus = WDIOF_CARDRESET;
 464
 465                 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
 466                     of_device_is_compatible(np, "aspeed,ast2500-wdt"))
 467                         wdt->wdd.groups = bswitch_groups;
 468         }
 469
 470         dev_set_drvdata(dev, wdt);
 471
 472         return devm_watchdog_register_device(dev, &wdt->wdd);
 473 }
 474
 475 static struct platform_driver aspeed_watchdog_driver = {
 476         .probe = aspeed_wdt_probe,
 477         .driver = {
 478                 .name = KBUILD_MODNAME,
 479                 .of_match_table = aspeed_wdt_of_table,
 480         },
 481 };
 482
 483 static int __init aspeed_wdt_init(void)
 484 {
 485         return platform_driver_register(&aspeed_watchdog_driver);
 486 }
 487 arch_initcall(aspeed_wdt_init);
 488
 489 static void __exit aspeed_wdt_exit(void)
 490 {
 491         platform_driver_unregister(&aspeed_watchdog_driver);
 492 }
 493 module_exit(aspeed_wdt_exit);
 494
 495 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
 496 MODULE_LICENSE("GPL");