drivers/vme/bridges/vme_tsi148.c

   1 /*
   2  * Support for the Tundra TSI148 VME-PCI Bridge Chip
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/mm.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/pci.h>
  23 #include <linux/poll.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/time.h>
  30 #include <linux/io.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/byteorder/generic.h>
  33 #include <linux/vme.h>
  34
  35 #include "../vme_bridge.h"
  36 #include "vme_tsi148.h"
  37
  38 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  39 static void tsi148_remove(struct pci_dev *);
  40
  41
  42 /* Module parameter */
  43 static bool err_chk;
  44 static int geoid;
  45
  46 static const char driver_name[] = "vme_tsi148";
  47
  48 static const struct pci_device_id tsi148_ids[] = {
  49         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  50         { },
  51 };
  52
  53 MODULE_DEVICE_TABLE(pci, tsi148_ids);
  54
  55 static struct pci_driver tsi148_driver = {
  56         .name = driver_name,
  57         .id_table = tsi148_ids,
  58         .probe = tsi148_probe,
  59         .remove = tsi148_remove,
  60 };
  61
  62 static void reg_join(unsigned int high, unsigned int low,
  63         unsigned long long *variable)
  64 {
  65         *variable = (unsigned long long)high << 32;
  66         *variable |= (unsigned long long)low;
  67 }
  68
  69 static void reg_split(unsigned long long variable, unsigned int *high,
  70         unsigned int *low)
  71 {
  72         *low = (unsigned int)variable & 0xFFFFFFFF;
  73         *high = (unsigned int)(variable >> 32);
  74 }
  75
  76 /*
  77  * Wakes up DMA queue.
  78  */
  79 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
  80         int channel_mask)
  81 {
  82         u32 serviced = 0;
  83
  84         if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
  85                 wake_up(&bridge->dma_queue[0]);
  86                 serviced |= TSI148_LCSR_INTC_DMA0C;
  87         }
  88         if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
  89                 wake_up(&bridge->dma_queue[1]);
  90                 serviced |= TSI148_LCSR_INTC_DMA1C;
  91         }
  92
  93         return serviced;
  94 }
  95
  96 /*
  97  * Wake up location monitor queue
  98  */
  99 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
 100 {
 101         int i;
 102         u32 serviced = 0;
 103
 104         for (i = 0; i < 4; i++) {
 105                 if (stat & TSI148_LCSR_INTS_LMS[i]) {
 106                         /* We only enable interrupts if the callback is set */
 107                         bridge->lm_callback[i](bridge->lm_data[i]);
 108                         serviced |= TSI148_LCSR_INTC_LMC[i];
 109                 }
 110         }
 111
 112         return serviced;
 113 }
 114
 115 /*
 116  * Wake up mail box queue.
 117  *
 118  * XXX This functionality is not exposed up though API.
 119  */
 120 static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
 121 {
 122         int i;
 123         u32 val;
 124         u32 serviced = 0;
 125         struct tsi148_driver *bridge;
 126
 127         bridge = tsi148_bridge->driver_priv;
 128
 129         for (i = 0; i < 4; i++) {
 130                 if (stat & TSI148_LCSR_INTS_MBS[i]) {
 131                         val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
 132                         dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
 133                                 ": 0x%x\n", i, val);
 134                         serviced |= TSI148_LCSR_INTC_MBC[i];
 135                 }
 136         }
 137
 138         return serviced;
 139 }
 140
 141 /*
 142  * Display error & status message when PERR (PCI) exception interrupt occurs.
 143  */
 144 static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
 145 {
 146         struct tsi148_driver *bridge;
 147
 148         bridge = tsi148_bridge->driver_priv;
 149
 150         dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
 151                 "attributes: %08x\n",
 152                 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
 153                 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
 154                 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
 155
 156         dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
 157                 "completion reg: %08x\n",
 158                 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
 159                 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
 160
 161         iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
 162
 163         return TSI148_LCSR_INTC_PERRC;
 164 }
 165
 166 /*
 167  * Save address and status when VME error interrupt occurs.
 168  */
 169 static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
 170 {
 171         unsigned int error_addr_high, error_addr_low;
 172         unsigned long long error_addr;
 173         u32 error_attrib;
 174         int error_am;
 175         struct tsi148_driver *bridge;
 176
 177         bridge = tsi148_bridge->driver_priv;
 178
 179         error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
 180         error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
 181         error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
 182         error_am = (error_attrib & TSI148_LCSR_VEAT_AM_M) >> 8;
 183
 184         reg_join(error_addr_high, error_addr_low, &error_addr);
 185
 186         /* Check for exception register overflow (we have lost error data) */
 187         if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
 188                 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
 189                         "Occurred\n");
 190         }
 191
 192         if (err_chk)
 193                 vme_bus_error_handler(tsi148_bridge, error_addr, error_am);
 194         else
 195                 dev_err(tsi148_bridge->parent,
 196                         "VME Bus Error at address: 0x%llx, attributes: %08x\n",
 197                         error_addr, error_attrib);
 198
 199         /* Clear Status */
 200         iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
 201
 202         return TSI148_LCSR_INTC_VERRC;
 203 }
 204
 205 /*
 206  * Wake up IACK queue.
 207  */
 208 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
 209 {
 210         wake_up(&bridge->iack_queue);
 211
 212         return TSI148_LCSR_INTC_IACKC;
 213 }
 214
 215 /*
 216  * Calling VME bus interrupt callback if provided.
 217  */
 218 static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
 219         u32 stat)
 220 {
 221         int vec, i, serviced = 0;
 222         struct tsi148_driver *bridge;
 223
 224         bridge = tsi148_bridge->driver_priv;
 225
 226         for (i = 7; i > 0; i--) {
 227                 if (stat & (1 << i)) {
 228                         /*
 229                          * Note: Even though the registers are defined as
 230                          * 32-bits in the spec, we only want to issue 8-bit
 231                          * IACK cycles on the bus, read from offset 3.
 232                          */
 233                         vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
 234
 235                         vme_irq_handler(tsi148_bridge, i, vec);
 236
 237                         serviced |= (1 << i);
 238                 }
 239         }
 240
 241         return serviced;
 242 }
 243
 244 /*
 245  * Top level interrupt handler.  Clears appropriate interrupt status bits and
 246  * then calls appropriate sub handler(s).
 247  */
 248 static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
 249 {
 250         u32 stat, enable, serviced = 0;
 251         struct vme_bridge *tsi148_bridge;
 252         struct tsi148_driver *bridge;
 253
 254         tsi148_bridge = ptr;
 255
 256         bridge = tsi148_bridge->driver_priv;
 257
 258         /* Determine which interrupts are unmasked and set */
 259         enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 260         stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
 261
 262         /* Only look at unmasked interrupts */
 263         stat &= enable;
 264
 265         if (unlikely(!stat))
 266                 return IRQ_NONE;
 267
 268         /* Call subhandlers as appropriate */
 269         /* DMA irqs */
 270         if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
 271                 serviced |= tsi148_DMA_irqhandler(bridge, stat);
 272
 273         /* Location monitor irqs */
 274         if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
 275                         TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
 276                 serviced |= tsi148_LM_irqhandler(bridge, stat);
 277
 278         /* Mail box irqs */
 279         if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
 280                         TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
 281                 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
 282
 283         /* PCI bus error */
 284         if (stat & TSI148_LCSR_INTS_PERRS)
 285                 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
 286
 287         /* VME bus error */
 288         if (stat & TSI148_LCSR_INTS_VERRS)
 289                 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
 290
 291         /* IACK irq */
 292         if (stat & TSI148_LCSR_INTS_IACKS)
 293                 serviced |= tsi148_IACK_irqhandler(bridge);
 294
 295         /* VME bus irqs */
 296         if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
 297                         TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
 298                         TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
 299                         TSI148_LCSR_INTS_IRQ1S))
 300                 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
 301
 302         /* Clear serviced interrupts */
 303         iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
 304
 305         return IRQ_HANDLED;
 306 }
 307
 308 static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
 309 {
 310         int result;
 311         unsigned int tmp;
 312         struct pci_dev *pdev;
 313         struct tsi148_driver *bridge;
 314
 315         pdev = to_pci_dev(tsi148_bridge->parent);
 316
 317         bridge = tsi148_bridge->driver_priv;
 318
 319         result = request_irq(pdev->irq,
 320                              tsi148_irqhandler,
 321                              IRQF_SHARED,
 322                              driver_name, tsi148_bridge);
 323         if (result) {
 324                 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
 325                         "vector %02X\n", pdev->irq);
 326                 return result;
 327         }
 328
 329         /* Enable and unmask interrupts */
 330         tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
 331                 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
 332                 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
 333                 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
 334                 TSI148_LCSR_INTEO_IACKEO;
 335
 336         /* This leaves the following interrupts masked.
 337          * TSI148_LCSR_INTEO_VIEEO
 338          * TSI148_LCSR_INTEO_SYSFLEO
 339          * TSI148_LCSR_INTEO_ACFLEO
 340          */
 341
 342         /* Don't enable Location Monitor interrupts here - they will be
 343          * enabled when the location monitors are properly configured and
 344          * a callback has been attached.
 345          * TSI148_LCSR_INTEO_LM0EO
 346          * TSI148_LCSR_INTEO_LM1EO
 347          * TSI148_LCSR_INTEO_LM2EO
 348          * TSI148_LCSR_INTEO_LM3EO
 349          */
 350
 351         /* Don't enable VME interrupts until we add a handler, else the board
 352          * will respond to it and we don't want that unless it knows how to
 353          * properly deal with it.
 354          * TSI148_LCSR_INTEO_IRQ7EO
 355          * TSI148_LCSR_INTEO_IRQ6EO
 356          * TSI148_LCSR_INTEO_IRQ5EO
 357          * TSI148_LCSR_INTEO_IRQ4EO
 358          * TSI148_LCSR_INTEO_IRQ3EO
 359          * TSI148_LCSR_INTEO_IRQ2EO
 360          * TSI148_LCSR_INTEO_IRQ1EO
 361          */
 362
 363         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 364         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 365
 366         return 0;
 367 }
 368
 369 static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
 370         struct pci_dev *pdev)
 371 {
 372         struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
 373
 374         /* Turn off interrupts */
 375         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
 376         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
 377
 378         /* Clear all interrupts */
 379         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
 380
 381         /* Detach interrupt handler */
 382         free_irq(pdev->irq, tsi148_bridge);
 383 }
 384
 385 /*
 386  * Check to see if an IACk has been received, return true (1) or false (0).
 387  */
 388 static int tsi148_iack_received(struct tsi148_driver *bridge)
 389 {
 390         u32 tmp;
 391
 392         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 393
 394         if (tmp & TSI148_LCSR_VICR_IRQS)
 395                 return 0;
 396         else
 397                 return 1;
 398 }
 399
 400 /*
 401  * Configure VME interrupt
 402  */
 403 static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
 404         int state, int sync)
 405 {
 406         struct pci_dev *pdev;
 407         u32 tmp;
 408         struct tsi148_driver *bridge;
 409
 410         bridge = tsi148_bridge->driver_priv;
 411
 412         /* We need to do the ordering differently for enabling and disabling */
 413         if (state == 0) {
 414                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 415                 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
 416                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 417
 418                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 419                 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
 420                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 421
 422                 if (sync != 0) {
 423                         pdev = to_pci_dev(tsi148_bridge->parent);
 424                         synchronize_irq(pdev->irq);
 425                 }
 426         } else {
 427                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 428                 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
 429                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 430
 431                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 432                 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
 433                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 434         }
 435 }
 436
 437 /*
 438  * Generate a VME bus interrupt at the requested level & vector. Wait for
 439  * interrupt to be acked.
 440  */
 441 static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
 442         int statid)
 443 {
 444         u32 tmp;
 445         struct tsi148_driver *bridge;
 446
 447         bridge = tsi148_bridge->driver_priv;
 448
 449         mutex_lock(&bridge->vme_int);
 450
 451         /* Read VICR register */
 452         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 453
 454         /* Set Status/ID */
 455         tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
 456                 (statid & TSI148_LCSR_VICR_STID_M);
 457         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 458
 459         /* Assert VMEbus IRQ */
 460         tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
 461         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 462
 463         /* XXX Consider implementing a timeout? */
 464         wait_event_interruptible(bridge->iack_queue,
 465                 tsi148_iack_received(bridge));
 466
 467         mutex_unlock(&bridge->vme_int);
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * Initialize a slave window with the requested attributes.
 474  */
 475 static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
 476         unsigned long long vme_base, unsigned long long size,
 477         dma_addr_t pci_base, u32 aspace, u32 cycle)
 478 {
 479         unsigned int i, addr = 0, granularity = 0;
 480         unsigned int temp_ctl = 0;
 481         unsigned int vme_base_low, vme_base_high;
 482         unsigned int vme_bound_low, vme_bound_high;
 483         unsigned int pci_offset_low, pci_offset_high;
 484         unsigned long long vme_bound, pci_offset;
 485         struct vme_bridge *tsi148_bridge;
 486         struct tsi148_driver *bridge;
 487
 488         tsi148_bridge = image->parent;
 489         bridge = tsi148_bridge->driver_priv;
 490
 491         i = image->number;
 492
 493         switch (aspace) {
 494         case VME_A16:
 495                 granularity = 0x10;
 496                 addr |= TSI148_LCSR_ITAT_AS_A16;
 497                 break;
 498         case VME_A24:
 499                 granularity = 0x1000;
 500                 addr |= TSI148_LCSR_ITAT_AS_A24;
 501                 break;
 502         case VME_A32:
 503                 granularity = 0x10000;
 504                 addr |= TSI148_LCSR_ITAT_AS_A32;
 505                 break;
 506         case VME_A64:
 507                 granularity = 0x10000;
 508                 addr |= TSI148_LCSR_ITAT_AS_A64;
 509                 break;
 510         default:
 511                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
 512                 return -EINVAL;
 513                 break;
 514         }
 515
 516         /* Convert 64-bit variables to 2x 32-bit variables */
 517         reg_split(vme_base, &vme_base_high, &vme_base_low);
 518
 519         /*
 520          * Bound address is a valid address for the window, adjust
 521          * accordingly
 522          */
 523         vme_bound = vme_base + size - granularity;
 524         reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
 525         pci_offset = (unsigned long long)pci_base - vme_base;
 526         reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
 527
 528         if (vme_base_low & (granularity - 1)) {
 529                 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
 530                 return -EINVAL;
 531         }
 532         if (vme_bound_low & (granularity - 1)) {
 533                 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
 534                 return -EINVAL;
 535         }
 536         if (pci_offset_low & (granularity - 1)) {
 537                 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
 538                         "alignment\n");
 539                 return -EINVAL;
 540         }
 541
 542         /*  Disable while we are mucking around */
 543         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 544                 TSI148_LCSR_OFFSET_ITAT);
 545         temp_ctl &= ~TSI148_LCSR_ITAT_EN;
 546         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 547                 TSI148_LCSR_OFFSET_ITAT);
 548
 549         /* Setup mapping */
 550         iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
 551                 TSI148_LCSR_OFFSET_ITSAU);
 552         iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
 553                 TSI148_LCSR_OFFSET_ITSAL);
 554         iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
 555                 TSI148_LCSR_OFFSET_ITEAU);
 556         iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
 557                 TSI148_LCSR_OFFSET_ITEAL);
 558         iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
 559                 TSI148_LCSR_OFFSET_ITOFU);
 560         iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
 561                 TSI148_LCSR_OFFSET_ITOFL);
 562
 563         /* Setup 2eSST speeds */
 564         temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
 565         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 566         case VME_2eSST160:
 567                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
 568                 break;
 569         case VME_2eSST267:
 570                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
 571                 break;
 572         case VME_2eSST320:
 573                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
 574                 break;
 575         }
 576
 577         /* Setup cycle types */
 578         temp_ctl &= ~(0x1F << 7);
 579         if (cycle & VME_BLT)
 580                 temp_ctl |= TSI148_LCSR_ITAT_BLT;
 581         if (cycle & VME_MBLT)
 582                 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
 583         if (cycle & VME_2eVME)
 584                 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
 585         if (cycle & VME_2eSST)
 586                 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
 587         if (cycle & VME_2eSSTB)
 588                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
 589
 590         /* Setup address space */
 591         temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
 592         temp_ctl |= addr;
 593
 594         temp_ctl &= ~0xF;
 595         if (cycle & VME_SUPER)
 596                 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
 597         if (cycle & VME_USER)
 598                 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
 599         if (cycle & VME_PROG)
 600                 temp_ctl |= TSI148_LCSR_ITAT_PGM;
 601         if (cycle & VME_DATA)
 602                 temp_ctl |= TSI148_LCSR_ITAT_DATA;
 603
 604         /* Write ctl reg without enable */
 605         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 606                 TSI148_LCSR_OFFSET_ITAT);
 607
 608         if (enabled)
 609                 temp_ctl |= TSI148_LCSR_ITAT_EN;
 610
 611         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 612                 TSI148_LCSR_OFFSET_ITAT);
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * Get slave window configuration.
 619  */
 620 static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
 621         unsigned long long *vme_base, unsigned long long *size,
 622         dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
 623 {
 624         unsigned int i, granularity = 0, ctl = 0;
 625         unsigned int vme_base_low, vme_base_high;
 626         unsigned int vme_bound_low, vme_bound_high;
 627         unsigned int pci_offset_low, pci_offset_high;
 628         unsigned long long vme_bound, pci_offset;
 629         struct tsi148_driver *bridge;
 630
 631         bridge = image->parent->driver_priv;
 632
 633         i = image->number;
 634
 635         /* Read registers */
 636         ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 637                 TSI148_LCSR_OFFSET_ITAT);
 638
 639         vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 640                 TSI148_LCSR_OFFSET_ITSAU);
 641         vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 642                 TSI148_LCSR_OFFSET_ITSAL);
 643         vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 644                 TSI148_LCSR_OFFSET_ITEAU);
 645         vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 646                 TSI148_LCSR_OFFSET_ITEAL);
 647         pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 648                 TSI148_LCSR_OFFSET_ITOFU);
 649         pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 650                 TSI148_LCSR_OFFSET_ITOFL);
 651
 652         /* Convert 64-bit variables to 2x 32-bit variables */
 653         reg_join(vme_base_high, vme_base_low, vme_base);
 654         reg_join(vme_bound_high, vme_bound_low, &vme_bound);
 655         reg_join(pci_offset_high, pci_offset_low, &pci_offset);
 656
 657         *pci_base = (dma_addr_t)(*vme_base + pci_offset);
 658
 659         *enabled = 0;
 660         *aspace = 0;
 661         *cycle = 0;
 662
 663         if (ctl & TSI148_LCSR_ITAT_EN)
 664                 *enabled = 1;
 665
 666         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
 667                 granularity = 0x10;
 668                 *aspace |= VME_A16;
 669         }
 670         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
 671                 granularity = 0x1000;
 672                 *aspace |= VME_A24;
 673         }
 674         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
 675                 granularity = 0x10000;
 676                 *aspace |= VME_A32;
 677         }
 678         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
 679                 granularity = 0x10000;
 680                 *aspace |= VME_A64;
 681         }
 682
 683         /* Need granularity before we set the size */
 684         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 685
 686
 687         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
 688                 *cycle |= VME_2eSST160;
 689         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
 690                 *cycle |= VME_2eSST267;
 691         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
 692                 *cycle |= VME_2eSST320;
 693
 694         if (ctl & TSI148_LCSR_ITAT_BLT)
 695                 *cycle |= VME_BLT;
 696         if (ctl & TSI148_LCSR_ITAT_MBLT)
 697                 *cycle |= VME_MBLT;
 698         if (ctl & TSI148_LCSR_ITAT_2eVME)
 699                 *cycle |= VME_2eVME;
 700         if (ctl & TSI148_LCSR_ITAT_2eSST)
 701                 *cycle |= VME_2eSST;
 702         if (ctl & TSI148_LCSR_ITAT_2eSSTB)
 703                 *cycle |= VME_2eSSTB;
 704
 705         if (ctl & TSI148_LCSR_ITAT_SUPR)
 706                 *cycle |= VME_SUPER;
 707         if (ctl & TSI148_LCSR_ITAT_NPRIV)
 708                 *cycle |= VME_USER;
 709         if (ctl & TSI148_LCSR_ITAT_PGM)
 710                 *cycle |= VME_PROG;
 711         if (ctl & TSI148_LCSR_ITAT_DATA)
 712                 *cycle |= VME_DATA;
 713
 714         return 0;
 715 }
 716
 717 /*
 718  * Allocate and map PCI Resource
 719  */
 720 static int tsi148_alloc_resource(struct vme_master_resource *image,
 721         unsigned long long size)
 722 {
 723         unsigned long long existing_size;
 724         int retval = 0;
 725         struct pci_dev *pdev;
 726         struct vme_bridge *tsi148_bridge;
 727
 728         tsi148_bridge = image->parent;
 729
 730         pdev = to_pci_dev(tsi148_bridge->parent);
 731
 732         existing_size = (unsigned long long)(image->bus_resource.end -
 733                 image->bus_resource.start);
 734
 735         /* If the existing size is OK, return */
 736         if ((size != 0) && (existing_size == (size - 1)))
 737                 return 0;
 738
 739         if (existing_size != 0) {
 740                 iounmap(image->kern_base);
 741                 image->kern_base = NULL;
 742                 kfree(image->bus_resource.name);
 743                 release_resource(&image->bus_resource);
 744                 memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 745         }
 746
 747         /* Exit here if size is zero */
 748         if (size == 0)
 749                 return 0;
 750
 751         if (!image->bus_resource.name) {
 752                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
 753                 if (!image->bus_resource.name) {
 754                         retval = -ENOMEM;
 755                         goto err_name;
 756                 }
 757         }
 758
 759         sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
 760                 image->number);
 761
 762         image->bus_resource.start = 0;
 763         image->bus_resource.end = (unsigned long)size;
 764         image->bus_resource.flags = IORESOURCE_MEM;
 765
 766         retval = pci_bus_alloc_resource(pdev->bus,
 767                 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
 768                 0, NULL, NULL);
 769         if (retval) {
 770                 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
 771                         "resource for window %d size 0x%lx start 0x%lx\n",
 772                         image->number, (unsigned long)size,
 773                         (unsigned long)image->bus_resource.start);
 774                 goto err_resource;
 775         }
 776
 777         image->kern_base = ioremap_nocache(
 778                 image->bus_resource.start, size);
 779         if (!image->kern_base) {
 780                 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
 781                 retval = -ENOMEM;
 782                 goto err_remap;
 783         }
 784
 785         return 0;
 786
 787 err_remap:
 788         release_resource(&image->bus_resource);
 789 err_resource:
 790         kfree(image->bus_resource.name);
 791         memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 792 err_name:
 793         return retval;
 794 }
 795
 796 /*
 797  * Free and unmap PCI Resource
 798  */
 799 static void tsi148_free_resource(struct vme_master_resource *image)
 800 {
 801         iounmap(image->kern_base);
 802         image->kern_base = NULL;
 803         release_resource(&image->bus_resource);
 804         kfree(image->bus_resource.name);
 805         memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 806 }
 807
 808 /*
 809  * Set the attributes of an outbound window.
 810  */
 811 static int tsi148_master_set(struct vme_master_resource *image, int enabled,
 812         unsigned long long vme_base, unsigned long long size, u32 aspace,
 813         u32 cycle, u32 dwidth)
 814 {
 815         int retval = 0;
 816         unsigned int i;
 817         unsigned int temp_ctl = 0;
 818         unsigned int pci_base_low, pci_base_high;
 819         unsigned int pci_bound_low, pci_bound_high;
 820         unsigned int vme_offset_low, vme_offset_high;
 821         unsigned long long pci_bound, vme_offset, pci_base;
 822         struct vme_bridge *tsi148_bridge;
 823         struct tsi148_driver *bridge;
 824         struct pci_bus_region region;
 825         struct pci_dev *pdev;
 826
 827         tsi148_bridge = image->parent;
 828
 829         bridge = tsi148_bridge->driver_priv;
 830
 831         pdev = to_pci_dev(tsi148_bridge->parent);
 832
 833         /* Verify input data */
 834         if (vme_base & 0xFFFF) {
 835                 dev_err(tsi148_bridge->parent, "Invalid VME Window "
 836                         "alignment\n");
 837                 retval = -EINVAL;
 838                 goto err_window;
 839         }
 840
 841         if ((size == 0) && (enabled != 0)) {
 842                 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
 843                         "enabled windows\n");
 844                 retval = -EINVAL;
 845                 goto err_window;
 846         }
 847
 848         spin_lock(&image->lock);
 849
 850         /* Let's allocate the resource here rather than further up the stack as
 851          * it avoids pushing loads of bus dependent stuff up the stack. If size
 852          * is zero, any existing resource will be freed.
 853          */
 854         retval = tsi148_alloc_resource(image, size);
 855         if (retval) {
 856                 spin_unlock(&image->lock);
 857                 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
 858                         "resource\n");
 859                 goto err_res;
 860         }
 861
 862         if (size == 0) {
 863                 pci_base = 0;
 864                 pci_bound = 0;
 865                 vme_offset = 0;
 866         } else {
 867                 pcibios_resource_to_bus(pdev->bus, &region,
 868                                         &image->bus_resource);
 869                 pci_base = region.start;
 870
 871                 /*
 872                  * Bound address is a valid address for the window, adjust
 873                  * according to window granularity.
 874                  */
 875                 pci_bound = pci_base + (size - 0x10000);
 876                 vme_offset = vme_base - pci_base;
 877         }
 878
 879         /* Convert 64-bit variables to 2x 32-bit variables */
 880         reg_split(pci_base, &pci_base_high, &pci_base_low);
 881         reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
 882         reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
 883
 884         if (pci_base_low & 0xFFFF) {
 885                 spin_unlock(&image->lock);
 886                 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
 887                 retval = -EINVAL;
 888                 goto err_gran;
 889         }
 890         if (pci_bound_low & 0xFFFF) {
 891                 spin_unlock(&image->lock);
 892                 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
 893                 retval = -EINVAL;
 894                 goto err_gran;
 895         }
 896         if (vme_offset_low & 0xFFFF) {
 897                 spin_unlock(&image->lock);
 898                 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
 899                         "alignment\n");
 900                 retval = -EINVAL;
 901                 goto err_gran;
 902         }
 903
 904         i = image->number;
 905
 906         /* Disable while we are mucking around */
 907         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
 908                 TSI148_LCSR_OFFSET_OTAT);
 909         temp_ctl &= ~TSI148_LCSR_OTAT_EN;
 910         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
 911                 TSI148_LCSR_OFFSET_OTAT);
 912
 913         /* Setup 2eSST speeds */
 914         temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
 915         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 916         case VME_2eSST160:
 917                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
 918                 break;
 919         case VME_2eSST267:
 920                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
 921                 break;
 922         case VME_2eSST320:
 923                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
 924                 break;
 925         }
 926
 927         /* Setup cycle types */
 928         if (cycle & VME_BLT) {
 929                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
 930                 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
 931         }
 932         if (cycle & VME_MBLT) {
 933                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
 934                 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
 935         }
 936         if (cycle & VME_2eVME) {
 937                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
 938                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
 939         }
 940         if (cycle & VME_2eSST) {
 941                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
 942                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
 943         }
 944         if (cycle & VME_2eSSTB) {
 945                 dev_warn(tsi148_bridge->parent, "Currently not setting "
 946                         "Broadcast Select Registers\n");
 947                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
 948                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
 949         }
 950
 951         /* Setup data width */
 952         temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
 953         switch (dwidth) {
 954         case VME_D16:
 955                 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
 956                 break;
 957         case VME_D32:
 958                 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
 959                 break;
 960         default:
 961                 spin_unlock(&image->lock);
 962                 dev_err(tsi148_bridge->parent, "Invalid data width\n");
 963                 retval = -EINVAL;
 964                 goto err_dwidth;
 965         }
 966
 967         /* Setup address space */
 968         temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
 969         switch (aspace) {
 970         case VME_A16:
 971                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
 972                 break;
 973         case VME_A24:
 974                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
 975                 break;
 976         case VME_A32:
 977                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
 978                 break;
 979         case VME_A64:
 980                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
 981                 break;
 982         case VME_CRCSR:
 983                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
 984                 break;
 985         case VME_USER1:
 986                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
 987                 break;
 988         case VME_USER2:
 989                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
 990                 break;
 991         case VME_USER3:
 992                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
 993                 break;
 994         case VME_USER4:
 995                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
 996                 break;
 997         default:
 998                 spin_unlock(&image->lock);
 999                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1000                 retval = -EINVAL;
1001                 goto err_aspace;
1002                 break;
1003         }
1004
1005         temp_ctl &= ~(3<<4);
1006         if (cycle & VME_SUPER)
1007                 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1008         if (cycle & VME_PROG)
1009                 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1010
1011         /* Setup mapping */
1012         iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1013                 TSI148_LCSR_OFFSET_OTSAU);
1014         iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1015                 TSI148_LCSR_OFFSET_OTSAL);
1016         iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1017                 TSI148_LCSR_OFFSET_OTEAU);
1018         iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1019                 TSI148_LCSR_OFFSET_OTEAL);
1020         iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1021                 TSI148_LCSR_OFFSET_OTOFU);
1022         iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1023                 TSI148_LCSR_OFFSET_OTOFL);
1024
1025         /* Write ctl reg without enable */
1026         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1027                 TSI148_LCSR_OFFSET_OTAT);
1028
1029         if (enabled)
1030                 temp_ctl |= TSI148_LCSR_OTAT_EN;
1031
1032         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1033                 TSI148_LCSR_OFFSET_OTAT);
1034
1035         spin_unlock(&image->lock);
1036         return 0;
1037
1038 err_aspace:
1039 err_dwidth:
1040 err_gran:
1041         tsi148_free_resource(image);
1042 err_res:
1043 err_window:
1044         return retval;
1045
1046 }
1047
1048 /*
1049  * Set the attributes of an outbound window.
1050  *
1051  * XXX Not parsing prefetch information.
1052  */
1053 static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1054         unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1055         u32 *cycle, u32 *dwidth)
1056 {
1057         unsigned int i, ctl;
1058         unsigned int pci_base_low, pci_base_high;
1059         unsigned int pci_bound_low, pci_bound_high;
1060         unsigned int vme_offset_low, vme_offset_high;
1061
1062         unsigned long long pci_base, pci_bound, vme_offset;
1063         struct tsi148_driver *bridge;
1064
1065         bridge = image->parent->driver_priv;
1066
1067         i = image->number;
1068
1069         ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1070                 TSI148_LCSR_OFFSET_OTAT);
1071
1072         pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1073                 TSI148_LCSR_OFFSET_OTSAU);
1074         pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1075                 TSI148_LCSR_OFFSET_OTSAL);
1076         pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1077                 TSI148_LCSR_OFFSET_OTEAU);
1078         pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1079                 TSI148_LCSR_OFFSET_OTEAL);
1080         vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1081                 TSI148_LCSR_OFFSET_OTOFU);
1082         vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1083                 TSI148_LCSR_OFFSET_OTOFL);
1084
1085         /* Convert 64-bit variables to 2x 32-bit variables */
1086         reg_join(pci_base_high, pci_base_low, &pci_base);
1087         reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1088         reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1089
1090         *vme_base = pci_base + vme_offset;
1091         *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1092
1093         *enabled = 0;
1094         *aspace = 0;
1095         *cycle = 0;
1096         *dwidth = 0;
1097
1098         if (ctl & TSI148_LCSR_OTAT_EN)
1099                 *enabled = 1;
1100
1101         /* Setup address space */
1102         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1103                 *aspace |= VME_A16;
1104         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1105                 *aspace |= VME_A24;
1106         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1107                 *aspace |= VME_A32;
1108         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1109                 *aspace |= VME_A64;
1110         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1111                 *aspace |= VME_CRCSR;
1112         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1113                 *aspace |= VME_USER1;
1114         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1115                 *aspace |= VME_USER2;
1116         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1117                 *aspace |= VME_USER3;
1118         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1119                 *aspace |= VME_USER4;
1120
1121         /* Setup 2eSST speeds */
1122         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1123                 *cycle |= VME_2eSST160;
1124         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1125                 *cycle |= VME_2eSST267;
1126         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1127                 *cycle |= VME_2eSST320;
1128
1129         /* Setup cycle types */
1130         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1131                 *cycle |= VME_SCT;
1132         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1133                 *cycle |= VME_BLT;
1134         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1135                 *cycle |= VME_MBLT;
1136         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1137                 *cycle |= VME_2eVME;
1138         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1139                 *cycle |= VME_2eSST;
1140         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1141                 *cycle |= VME_2eSSTB;
1142
1143         if (ctl & TSI148_LCSR_OTAT_SUP)
1144                 *cycle |= VME_SUPER;
1145         else
1146                 *cycle |= VME_USER;
1147
1148         if (ctl & TSI148_LCSR_OTAT_PGM)
1149                 *cycle |= VME_PROG;
1150         else
1151                 *cycle |= VME_DATA;
1152
1153         /* Setup data width */
1154         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1155                 *dwidth = VME_D16;
1156         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1157                 *dwidth = VME_D32;
1158
1159         return 0;
1160 }
1161
1162
1163 static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1164         unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1165         u32 *cycle, u32 *dwidth)
1166 {
1167         int retval;
1168
1169         spin_lock(&image->lock);
1170
1171         retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1172                 cycle, dwidth);
1173
1174         spin_unlock(&image->lock);
1175
1176         return retval;
1177 }
1178
1179 static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1180         size_t count, loff_t offset)
1181 {
1182         int retval, enabled;
1183         unsigned long long vme_base, size;
1184         u32 aspace, cycle, dwidth;
1185         struct vme_error_handler *handler = NULL;
1186         struct vme_bridge *tsi148_bridge;
1187         void __iomem *addr = image->kern_base + offset;
1188         unsigned int done = 0;
1189         unsigned int count32;
1190
1191         tsi148_bridge = image->parent;
1192
1193         spin_lock(&image->lock);
1194
1195         if (err_chk) {
1196                 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1197                                     &cycle, &dwidth);
1198                 handler = vme_register_error_handler(tsi148_bridge, aspace,
1199                                                      vme_base + offset, count);
1200                 if (!handler) {
1201                         spin_unlock(&image->lock);
1202                         return -ENOMEM;
1203                 }
1204         }
1205
1206         /* The following code handles VME address alignment. We cannot use
1207          * memcpy_xxx here because it may cut data transfers in to 8-bit
1208          * cycles when D16 or D32 cycles are required on the VME bus.
1209          * On the other hand, the bridge itself assures that the maximum data
1210          * cycle configured for the transfer is used and splits it
1211          * automatically for non-aligned addresses, so we don't want the
1212          * overhead of needlessly forcing small transfers for the entire cycle.
1213          */
1214         if ((uintptr_t)addr & 0x1) {
1215                 *(u8 *)buf = ioread8(addr);
1216                 done += 1;
1217                 if (done == count)
1218                         goto out;
1219         }
1220         if ((uintptr_t)(addr + done) & 0x2) {
1221                 if ((count - done) < 2) {
1222                         *(u8 *)(buf + done) = ioread8(addr + done);
1223                         done += 1;
1224                         goto out;
1225                 } else {
1226                         *(u16 *)(buf + done) = ioread16(addr + done);
1227                         done += 2;
1228                 }
1229         }
1230
1231         count32 = (count - done) & ~0x3;
1232         while (done < count32) {
1233                 *(u32 *)(buf + done) = ioread32(addr + done);
1234                 done += 4;
1235         }
1236
1237         if ((count - done) & 0x2) {
1238                 *(u16 *)(buf + done) = ioread16(addr + done);
1239                 done += 2;
1240         }
1241         if ((count - done) & 0x1) {
1242                 *(u8 *)(buf + done) = ioread8(addr + done);
1243                 done += 1;
1244         }
1245
1246 out:
1247         retval = count;
1248
1249         if (err_chk) {
1250                 if (handler->num_errors) {
1251                         dev_err(image->parent->parent,
1252                                 "First VME read error detected an at address 0x%llx\n",
1253                                 handler->first_error);
1254                         retval = handler->first_error - (vme_base + offset);
1255                 }
1256                 vme_unregister_error_handler(handler);
1257         }
1258
1259         spin_unlock(&image->lock);
1260
1261         return retval;
1262 }
1263
1264
1265 static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1266         size_t count, loff_t offset)
1267 {
1268         int retval = 0, enabled;
1269         unsigned long long vme_base, size;
1270         u32 aspace, cycle, dwidth;
1271         void __iomem *addr = image->kern_base + offset;
1272         unsigned int done = 0;
1273         unsigned int count32;
1274
1275         struct vme_error_handler *handler = NULL;
1276         struct vme_bridge *tsi148_bridge;
1277         struct tsi148_driver *bridge;
1278
1279         tsi148_bridge = image->parent;
1280
1281         bridge = tsi148_bridge->driver_priv;
1282
1283         spin_lock(&image->lock);
1284
1285         if (err_chk) {
1286                 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1287                                     &cycle, &dwidth);
1288                 handler = vme_register_error_handler(tsi148_bridge, aspace,
1289                                                      vme_base + offset, count);
1290                 if (!handler) {
1291                         spin_unlock(&image->lock);
1292                         return -ENOMEM;
1293                 }
1294         }
1295
1296         /* Here we apply for the same strategy we do in master_read
1297          * function in order to assure the correct cycles.
1298          */
1299         if ((uintptr_t)addr & 0x1) {
1300                 iowrite8(*(u8 *)buf, addr);
1301                 done += 1;
1302                 if (done == count)
1303                         goto out;
1304         }
1305         if ((uintptr_t)(addr + done) & 0x2) {
1306                 if ((count - done) < 2) {
1307                         iowrite8(*(u8 *)(buf + done), addr + done);
1308                         done += 1;
1309                         goto out;
1310                 } else {
1311                         iowrite16(*(u16 *)(buf + done), addr + done);
1312                         done += 2;
1313                 }
1314         }
1315
1316         count32 = (count - done) & ~0x3;
1317         while (done < count32) {
1318                 iowrite32(*(u32 *)(buf + done), addr + done);
1319                 done += 4;
1320         }
1321
1322         if ((count - done) & 0x2) {
1323                 iowrite16(*(u16 *)(buf + done), addr + done);
1324                 done += 2;
1325         }
1326         if ((count - done) & 0x1) {
1327                 iowrite8(*(u8 *)(buf + done), addr + done);
1328                 done += 1;
1329         }
1330
1331 out:
1332         retval = count;
1333
1334         /*
1335          * Writes are posted. We need to do a read on the VME bus to flush out
1336          * all of the writes before we check for errors. We can't guarantee
1337          * that reading the data we have just written is safe. It is believed
1338          * that there isn't any read, write re-ordering, so we can read any
1339          * location in VME space, so lets read the Device ID from the tsi148's
1340          * own registers as mapped into CR/CSR space.
1341          *
1342          * We check for saved errors in the written address range/space.
1343          */
1344
1345         if (err_chk) {
1346                 ioread16(bridge->flush_image->kern_base + 0x7F000);
1347
1348                 if (handler->num_errors) {
1349                         dev_warn(tsi148_bridge->parent,
1350                                  "First VME write error detected an at address 0x%llx\n",
1351                                  handler->first_error);
1352                         retval = handler->first_error - (vme_base + offset);
1353                 }
1354                 vme_unregister_error_handler(handler);
1355         }
1356
1357         spin_unlock(&image->lock);
1358
1359         return retval;
1360 }
1361
1362 /*
1363  * Perform an RMW cycle on the VME bus.
1364  *
1365  * Requires a previously configured master window, returns final value.
1366  */
1367 static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1368         unsigned int mask, unsigned int compare, unsigned int swap,
1369         loff_t offset)
1370 {
1371         unsigned long long pci_addr;
1372         unsigned int pci_addr_high, pci_addr_low;
1373         u32 tmp, result;
1374         int i;
1375         struct tsi148_driver *bridge;
1376
1377         bridge = image->parent->driver_priv;
1378
1379         /* Find the PCI address that maps to the desired VME address */
1380         i = image->number;
1381
1382         /* Locking as we can only do one of these at a time */
1383         mutex_lock(&bridge->vme_rmw);
1384
1385         /* Lock image */
1386         spin_lock(&image->lock);
1387
1388         pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1389                 TSI148_LCSR_OFFSET_OTSAU);
1390         pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1391                 TSI148_LCSR_OFFSET_OTSAL);
1392
1393         reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1394         reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1395
1396         /* Configure registers */
1397         iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1398         iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1399         iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1400         iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1401         iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1402
1403         /* Enable RMW */
1404         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1405         tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1406         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1407
1408         /* Kick process off with a read to the required address. */
1409         result = ioread32be(image->kern_base + offset);
1410
1411         /* Disable RMW */
1412         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1413         tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1414         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1415
1416         spin_unlock(&image->lock);
1417
1418         mutex_unlock(&bridge->vme_rmw);
1419
1420         return result;
1421 }
1422
1423 static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
1424         u32 aspace, u32 cycle, u32 dwidth)
1425 {
1426         u32 val;
1427
1428         val = be32_to_cpu(*attr);
1429
1430         /* Setup 2eSST speeds */
1431         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1432         case VME_2eSST160:
1433                 val |= TSI148_LCSR_DSAT_2eSSTM_160;
1434                 break;
1435         case VME_2eSST267:
1436                 val |= TSI148_LCSR_DSAT_2eSSTM_267;
1437                 break;
1438         case VME_2eSST320:
1439                 val |= TSI148_LCSR_DSAT_2eSSTM_320;
1440                 break;
1441         }
1442
1443         /* Setup cycle types */
1444         if (cycle & VME_SCT)
1445                 val |= TSI148_LCSR_DSAT_TM_SCT;
1446
1447         if (cycle & VME_BLT)
1448                 val |= TSI148_LCSR_DSAT_TM_BLT;
1449
1450         if (cycle & VME_MBLT)
1451                 val |= TSI148_LCSR_DSAT_TM_MBLT;
1452
1453         if (cycle & VME_2eVME)
1454                 val |= TSI148_LCSR_DSAT_TM_2eVME;
1455
1456         if (cycle & VME_2eSST)
1457                 val |= TSI148_LCSR_DSAT_TM_2eSST;
1458
1459         if (cycle & VME_2eSSTB) {
1460                 dev_err(dev, "Currently not setting Broadcast Select "
1461                         "Registers\n");
1462                 val |= TSI148_LCSR_DSAT_TM_2eSSTB;
1463         }
1464
1465         /* Setup data width */
1466         switch (dwidth) {
1467         case VME_D16:
1468                 val |= TSI148_LCSR_DSAT_DBW_16;
1469                 break;
1470         case VME_D32:
1471                 val |= TSI148_LCSR_DSAT_DBW_32;
1472                 break;
1473         default:
1474                 dev_err(dev, "Invalid data width\n");
1475                 return -EINVAL;
1476         }
1477
1478         /* Setup address space */
1479         switch (aspace) {
1480         case VME_A16:
1481                 val |= TSI148_LCSR_DSAT_AMODE_A16;
1482                 break;
1483         case VME_A24:
1484                 val |= TSI148_LCSR_DSAT_AMODE_A24;
1485                 break;
1486         case VME_A32:
1487                 val |= TSI148_LCSR_DSAT_AMODE_A32;
1488                 break;
1489         case VME_A64:
1490                 val |= TSI148_LCSR_DSAT_AMODE_A64;
1491                 break;
1492         case VME_CRCSR:
1493                 val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1494                 break;
1495         case VME_USER1:
1496                 val |= TSI148_LCSR_DSAT_AMODE_USER1;
1497                 break;
1498         case VME_USER2:
1499                 val |= TSI148_LCSR_DSAT_AMODE_USER2;
1500                 break;
1501         case VME_USER3:
1502                 val |= TSI148_LCSR_DSAT_AMODE_USER3;
1503                 break;
1504         case VME_USER4:
1505                 val |= TSI148_LCSR_DSAT_AMODE_USER4;
1506                 break;
1507         default:
1508                 dev_err(dev, "Invalid address space\n");
1509                 return -EINVAL;
1510                 break;
1511         }
1512
1513         if (cycle & VME_SUPER)
1514                 val |= TSI148_LCSR_DSAT_SUP;
1515         if (cycle & VME_PROG)
1516                 val |= TSI148_LCSR_DSAT_PGM;
1517
1518         *attr = cpu_to_be32(val);
1519
1520         return 0;
1521 }
1522
1523 static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
1524         u32 aspace, u32 cycle, u32 dwidth)
1525 {
1526         u32 val;
1527
1528         val = be32_to_cpu(*attr);
1529
1530         /* Setup 2eSST speeds */
1531         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1532         case VME_2eSST160:
1533                 val |= TSI148_LCSR_DDAT_2eSSTM_160;
1534                 break;
1535         case VME_2eSST267:
1536                 val |= TSI148_LCSR_DDAT_2eSSTM_267;
1537                 break;
1538         case VME_2eSST320:
1539                 val |= TSI148_LCSR_DDAT_2eSSTM_320;
1540                 break;
1541         }
1542
1543         /* Setup cycle types */
1544         if (cycle & VME_SCT)
1545                 val |= TSI148_LCSR_DDAT_TM_SCT;
1546
1547         if (cycle & VME_BLT)
1548                 val |= TSI148_LCSR_DDAT_TM_BLT;
1549
1550         if (cycle & VME_MBLT)
1551                 val |= TSI148_LCSR_DDAT_TM_MBLT;
1552
1553         if (cycle & VME_2eVME)
1554                 val |= TSI148_LCSR_DDAT_TM_2eVME;
1555
1556         if (cycle & VME_2eSST)
1557                 val |= TSI148_LCSR_DDAT_TM_2eSST;
1558
1559         if (cycle & VME_2eSSTB) {
1560                 dev_err(dev, "Currently not setting Broadcast Select "
1561                         "Registers\n");
1562                 val |= TSI148_LCSR_DDAT_TM_2eSSTB;
1563         }
1564
1565         /* Setup data width */
1566         switch (dwidth) {
1567         case VME_D16:
1568                 val |= TSI148_LCSR_DDAT_DBW_16;
1569                 break;
1570         case VME_D32:
1571                 val |= TSI148_LCSR_DDAT_DBW_32;
1572                 break;
1573         default:
1574                 dev_err(dev, "Invalid data width\n");
1575                 return -EINVAL;
1576         }
1577
1578         /* Setup address space */
1579         switch (aspace) {
1580         case VME_A16:
1581                 val |= TSI148_LCSR_DDAT_AMODE_A16;
1582                 break;
1583         case VME_A24:
1584                 val |= TSI148_LCSR_DDAT_AMODE_A24;
1585                 break;
1586         case VME_A32:
1587                 val |= TSI148_LCSR_DDAT_AMODE_A32;
1588                 break;
1589         case VME_A64:
1590                 val |= TSI148_LCSR_DDAT_AMODE_A64;
1591                 break;
1592         case VME_CRCSR:
1593                 val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1594                 break;
1595         case VME_USER1:
1596                 val |= TSI148_LCSR_DDAT_AMODE_USER1;
1597                 break;
1598         case VME_USER2:
1599                 val |= TSI148_LCSR_DDAT_AMODE_USER2;
1600                 break;
1601         case VME_USER3:
1602                 val |= TSI148_LCSR_DDAT_AMODE_USER3;
1603                 break;
1604         case VME_USER4:
1605                 val |= TSI148_LCSR_DDAT_AMODE_USER4;
1606                 break;
1607         default:
1608                 dev_err(dev, "Invalid address space\n");
1609                 return -EINVAL;
1610                 break;
1611         }
1612
1613         if (cycle & VME_SUPER)
1614                 val |= TSI148_LCSR_DDAT_SUP;
1615         if (cycle & VME_PROG)
1616                 val |= TSI148_LCSR_DDAT_PGM;
1617
1618         *attr = cpu_to_be32(val);
1619
1620         return 0;
1621 }
1622
1623 /*
1624  * Add a link list descriptor to the list
1625  *
1626  * Note: DMA engine expects the DMA descriptor to be big endian.
1627  */
1628 static int tsi148_dma_list_add(struct vme_dma_list *list,
1629         struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1630 {
1631         struct tsi148_dma_entry *entry, *prev;
1632         u32 address_high, address_low, val;
1633         struct vme_dma_pattern *pattern_attr;
1634         struct vme_dma_pci *pci_attr;
1635         struct vme_dma_vme *vme_attr;
1636         int retval = 0;
1637         struct vme_bridge *tsi148_bridge;
1638
1639         tsi148_bridge = list->parent->parent;
1640
1641         /* Descriptor must be aligned on 64-bit boundaries */
1642         entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1643         if (!entry) {
1644                 retval = -ENOMEM;
1645                 goto err_mem;
1646         }
1647
1648         /* Test descriptor alignment */
1649         if ((unsigned long)&entry->descriptor & 0x7) {
1650                 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1651                         "byte boundary as required: %p\n",
1652                         &entry->descriptor);
1653                 retval = -EINVAL;
1654                 goto err_align;
1655         }
1656
1657         /* Given we are going to fill out the structure, we probably don't
1658          * need to zero it, but better safe than sorry for now.
1659          */
1660         memset(&entry->descriptor, 0, sizeof(entry->descriptor));
1661
1662         /* Fill out source part */
1663         switch (src->type) {
1664         case VME_DMA_PATTERN:
1665                 pattern_attr = src->private;
1666
1667                 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
1668
1669                 val = TSI148_LCSR_DSAT_TYP_PAT;
1670
1671                 /* Default behaviour is 32 bit pattern */
1672                 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1673                         val |= TSI148_LCSR_DSAT_PSZ;
1674
1675                 /* It seems that the default behaviour is to increment */
1676                 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1677                         val |= TSI148_LCSR_DSAT_NIN;
1678                 entry->descriptor.dsat = cpu_to_be32(val);
1679                 break;
1680         case VME_DMA_PCI:
1681                 pci_attr = src->private;
1682
1683                 reg_split((unsigned long long)pci_attr->address, &address_high,
1684                         &address_low);
1685                 entry->descriptor.dsau = cpu_to_be32(address_high);
1686                 entry->descriptor.dsal = cpu_to_be32(address_low);
1687                 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
1688                 break;
1689         case VME_DMA_VME:
1690                 vme_attr = src->private;
1691
1692                 reg_split((unsigned long long)vme_attr->address, &address_high,
1693                         &address_low);
1694                 entry->descriptor.dsau = cpu_to_be32(address_high);
1695                 entry->descriptor.dsal = cpu_to_be32(address_low);
1696                 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
1697
1698                 retval = tsi148_dma_set_vme_src_attributes(
1699                         tsi148_bridge->parent, &entry->descriptor.dsat,
1700                         vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1701                 if (retval < 0)
1702                         goto err_source;
1703                 break;
1704         default:
1705                 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1706                 retval = -EINVAL;
1707                 goto err_source;
1708                 break;
1709         }
1710
1711         /* Assume last link - this will be over-written by adding another */
1712         entry->descriptor.dnlau = cpu_to_be32(0);
1713         entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
1714
1715         /* Fill out destination part */
1716         switch (dest->type) {
1717         case VME_DMA_PCI:
1718                 pci_attr = dest->private;
1719
1720                 reg_split((unsigned long long)pci_attr->address, &address_high,
1721                         &address_low);
1722                 entry->descriptor.ddau = cpu_to_be32(address_high);
1723                 entry->descriptor.ddal = cpu_to_be32(address_low);
1724                 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
1725                 break;
1726         case VME_DMA_VME:
1727                 vme_attr = dest->private;
1728
1729                 reg_split((unsigned long long)vme_attr->address, &address_high,
1730                         &address_low);
1731                 entry->descriptor.ddau = cpu_to_be32(address_high);
1732                 entry->descriptor.ddal = cpu_to_be32(address_low);
1733                 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
1734
1735                 retval = tsi148_dma_set_vme_dest_attributes(
1736                         tsi148_bridge->parent, &entry->descriptor.ddat,
1737                         vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1738                 if (retval < 0)
1739                         goto err_dest;
1740                 break;
1741         default:
1742                 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1743                 retval = -EINVAL;
1744                 goto err_dest;
1745                 break;
1746         }
1747
1748         /* Fill out count */
1749         entry->descriptor.dcnt = cpu_to_be32((u32)count);
1750
1751         /* Add to list */
1752         list_add_tail(&entry->list, &list->entries);
1753
1754         entry->dma_handle = dma_map_single(tsi148_bridge->parent,
1755                                            &entry->descriptor,
1756                                            sizeof(entry->descriptor),
1757                                            DMA_TO_DEVICE);
1758         if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) {
1759                 dev_err(tsi148_bridge->parent, "DMA mapping error\n");
1760                 retval = -EINVAL;
1761                 goto err_dma;
1762         }
1763
1764         /* Fill out previous descriptors "Next Address" */
1765         if (entry->list.prev != &list->entries) {
1766                 reg_split((unsigned long long)entry->dma_handle, &address_high,
1767                         &address_low);
1768                 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1769                                   list);
1770                 prev->descriptor.dnlau = cpu_to_be32(address_high);
1771                 prev->descriptor.dnlal = cpu_to_be32(address_low);
1772
1773         }
1774
1775         return 0;
1776
1777 err_dma:
1778         list_del(&entry->list);
1779 err_dest:
1780 err_source:
1781 err_align:
1782                 kfree(entry);
1783 err_mem:
1784         return retval;
1785 }
1786
1787 /*
1788  * Check to see if the provided DMA channel is busy.
1789  */
1790 static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1791 {
1792         u32 tmp;
1793         struct tsi148_driver *bridge;
1794
1795         bridge = tsi148_bridge->driver_priv;
1796
1797         tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1798                 TSI148_LCSR_OFFSET_DSTA);
1799
1800         if (tmp & TSI148_LCSR_DSTA_BSY)
1801                 return 0;
1802         else
1803                 return 1;
1804
1805 }
1806
1807 /*
1808  * Execute a previously generated link list
1809  *
1810  * XXX Need to provide control register configuration.
1811  */
1812 static int tsi148_dma_list_exec(struct vme_dma_list *list)
1813 {
1814         struct vme_dma_resource *ctrlr;
1815         int channel, retval;
1816         struct tsi148_dma_entry *entry;
1817         u32 bus_addr_high, bus_addr_low;
1818         u32 val, dctlreg = 0;
1819         struct vme_bridge *tsi148_bridge;
1820         struct tsi148_driver *bridge;
1821
1822         ctrlr = list->parent;
1823
1824         tsi148_bridge = ctrlr->parent;
1825
1826         bridge = tsi148_bridge->driver_priv;
1827
1828         mutex_lock(&ctrlr->mtx);
1829
1830         channel = ctrlr->number;
1831
1832         if (!list_empty(&ctrlr->running)) {
1833                 /*
1834                  * XXX We have an active DMA transfer and currently haven't
1835                  *     sorted out the mechanism for "pending" DMA transfers.
1836                  *     Return busy.
1837                  */
1838                 /* Need to add to pending here */
1839                 mutex_unlock(&ctrlr->mtx);
1840                 return -EBUSY;
1841         } else {
1842                 list_add(&list->list, &ctrlr->running);
1843         }
1844
1845         /* Get first bus address and write into registers */
1846         entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1847                 list);
1848
1849         mutex_unlock(&ctrlr->mtx);
1850
1851         reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
1852
1853         iowrite32be(bus_addr_high, bridge->base +
1854                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1855         iowrite32be(bus_addr_low, bridge->base +
1856                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1857
1858         dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1859                 TSI148_LCSR_OFFSET_DCTL);
1860
1861         /* Start the operation */
1862         iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1863                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1864
1865         retval = wait_event_interruptible(bridge->dma_queue[channel],
1866                 tsi148_dma_busy(ctrlr->parent, channel));
1867
1868         if (retval) {
1869                 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +
1870                         TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1871                 /* Wait for the operation to abort */
1872                 wait_event(bridge->dma_queue[channel],
1873                            tsi148_dma_busy(ctrlr->parent, channel));
1874                 retval = -EINTR;
1875                 goto exit;
1876         }
1877
1878         /*
1879          * Read status register, this register is valid until we kick off a
1880          * new transfer.
1881          */
1882         val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1883                 TSI148_LCSR_OFFSET_DSTA);
1884
1885         if (val & TSI148_LCSR_DSTA_VBE) {
1886                 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1887                 retval = -EIO;
1888         }
1889
1890 exit:
1891         /* Remove list from running list */
1892         mutex_lock(&ctrlr->mtx);
1893         list_del(&list->list);
1894         mutex_unlock(&ctrlr->mtx);
1895
1896         return retval;
1897 }
1898
1899 /*
1900  * Clean up a previously generated link list
1901  *
1902  * We have a separate function, don't assume that the chain can't be reused.
1903  */
1904 static int tsi148_dma_list_empty(struct vme_dma_list *list)
1905 {
1906         struct list_head *pos, *temp;
1907         struct tsi148_dma_entry *entry;
1908
1909         struct vme_bridge *tsi148_bridge = list->parent->parent;
1910
1911         /* detach and free each entry */
1912         list_for_each_safe(pos, temp, &list->entries) {
1913                 list_del(pos);
1914                 entry = list_entry(pos, struct tsi148_dma_entry, list);
1915
1916                 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
1917                         sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1918                 kfree(entry);
1919         }
1920
1921         return 0;
1922 }
1923
1924 /*
1925  * All 4 location monitors reside at the same base - this is therefore a
1926  * system wide configuration.
1927  *
1928  * This does not enable the LM monitor - that should be done when the first
1929  * callback is attached and disabled when the last callback is removed.
1930  */
1931 static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1932         u32 aspace, u32 cycle)
1933 {
1934         u32 lm_base_high, lm_base_low, lm_ctl = 0;
1935         int i;
1936         struct vme_bridge *tsi148_bridge;
1937         struct tsi148_driver *bridge;
1938
1939         tsi148_bridge = lm->parent;
1940
1941         bridge = tsi148_bridge->driver_priv;
1942
1943         mutex_lock(&lm->mtx);
1944
1945         /* If we already have a callback attached, we can't move it! */
1946         for (i = 0; i < lm->monitors; i++) {
1947                 if (bridge->lm_callback[i]) {
1948                         mutex_unlock(&lm->mtx);
1949                         dev_err(tsi148_bridge->parent, "Location monitor "
1950                                 "callback attached, can't reset\n");
1951                         return -EBUSY;
1952                 }
1953         }
1954
1955         switch (aspace) {
1956         case VME_A16:
1957                 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1958                 break;
1959         case VME_A24:
1960                 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1961                 break;
1962         case VME_A32:
1963                 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1964                 break;
1965         case VME_A64:
1966                 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1967                 break;
1968         default:
1969                 mutex_unlock(&lm->mtx);
1970                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1971                 return -EINVAL;
1972                 break;
1973         }
1974
1975         if (cycle & VME_SUPER)
1976                 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1977         if (cycle & VME_USER)
1978                 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1979         if (cycle & VME_PROG)
1980                 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1981         if (cycle & VME_DATA)
1982                 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1983
1984         reg_split(lm_base, &lm_base_high, &lm_base_low);
1985
1986         iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1987         iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1988         iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
1989
1990         mutex_unlock(&lm->mtx);
1991
1992         return 0;
1993 }
1994
1995 /* Get configuration of the callback monitor and return whether it is enabled
1996  * or disabled.
1997  */
1998 static int tsi148_lm_get(struct vme_lm_resource *lm,
1999         unsigned long long *lm_base, u32 *aspace, u32 *cycle)
2000 {
2001         u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2002         struct tsi148_driver *bridge;
2003
2004         bridge = lm->parent->driver_priv;
2005
2006         mutex_lock(&lm->mtx);
2007
2008         lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2009         lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2010         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2011
2012         reg_join(lm_base_high, lm_base_low, lm_base);
2013
2014         if (lm_ctl & TSI148_LCSR_LMAT_EN)
2015                 enabled = 1;
2016
2017         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
2018                 *aspace |= VME_A16;
2019
2020         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
2021                 *aspace |= VME_A24;
2022
2023         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
2024                 *aspace |= VME_A32;
2025
2026         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
2027                 *aspace |= VME_A64;
2028
2029
2030         if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2031                 *cycle |= VME_SUPER;
2032         if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2033                 *cycle |= VME_USER;
2034         if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2035                 *cycle |= VME_PROG;
2036         if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2037                 *cycle |= VME_DATA;
2038
2039         mutex_unlock(&lm->mtx);
2040
2041         return enabled;
2042 }
2043
2044 /*
2045  * Attach a callback to a specific location monitor.
2046  *
2047  * Callback will be passed the monitor triggered.
2048  */
2049 static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2050         void (*callback)(void *), void *data)
2051 {
2052         u32 lm_ctl, tmp;
2053         struct vme_bridge *tsi148_bridge;
2054         struct tsi148_driver *bridge;
2055
2056         tsi148_bridge = lm->parent;
2057
2058         bridge = tsi148_bridge->driver_priv;
2059
2060         mutex_lock(&lm->mtx);
2061
2062         /* Ensure that the location monitor is configured - need PGM or DATA */
2063         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2064         if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2065                 mutex_unlock(&lm->mtx);
2066                 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2067                         "configured\n");
2068                 return -EINVAL;
2069         }
2070
2071         /* Check that a callback isn't already attached */
2072         if (bridge->lm_callback[monitor]) {
2073                 mutex_unlock(&lm->mtx);
2074                 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2075                 return -EBUSY;
2076         }
2077
2078         /* Attach callback */
2079         bridge->lm_callback[monitor] = callback;
2080         bridge->lm_data[monitor] = data;
2081
2082         /* Enable Location Monitor interrupt */
2083         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2084         tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2085         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2086
2087         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2088         tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2089         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2090
2091         /* Ensure that global Location Monitor Enable set */
2092         if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2093                 lm_ctl |= TSI148_LCSR_LMAT_EN;
2094                 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2095         }
2096
2097         mutex_unlock(&lm->mtx);
2098
2099         return 0;
2100 }
2101
2102 /*
2103  * Detach a callback function forn a specific location monitor.
2104  */
2105 static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2106 {
2107         u32 lm_en, tmp;
2108         struct tsi148_driver *bridge;
2109
2110         bridge = lm->parent->driver_priv;
2111
2112         mutex_lock(&lm->mtx);
2113
2114         /* Disable Location Monitor and ensure previous interrupts are clear */
2115         lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2116         lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2117         iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2118
2119         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2120         tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2121         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2122
2123         iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2124                  bridge->base + TSI148_LCSR_INTC);
2125
2126         /* Detach callback */
2127         bridge->lm_callback[monitor] = NULL;
2128         bridge->lm_data[monitor] = NULL;
2129
2130         /* If all location monitors disabled, disable global Location Monitor */
2131         if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2132                         TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2133                 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2134                 tmp &= ~TSI148_LCSR_LMAT_EN;
2135                 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2136         }
2137
2138         mutex_unlock(&lm->mtx);
2139
2140         return 0;
2141 }
2142
2143 /*
2144  * Determine Geographical Addressing
2145  */
2146 static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2147 {
2148         u32 slot = 0;
2149         struct tsi148_driver *bridge;
2150
2151         bridge = tsi148_bridge->driver_priv;
2152
2153         if (!geoid) {
2154                 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2155                 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2156         } else
2157                 slot = geoid;
2158
2159         return (int)slot;
2160 }
2161
2162 static void *tsi148_alloc_consistent(struct device *parent, size_t size,
2163         dma_addr_t *dma)
2164 {
2165         struct pci_dev *pdev;
2166
2167         /* Find pci_dev container of dev */
2168         pdev = to_pci_dev(parent);
2169
2170         return pci_alloc_consistent(pdev, size, dma);
2171 }
2172
2173 static void tsi148_free_consistent(struct device *parent, size_t size,
2174         void *vaddr, dma_addr_t dma)
2175 {
2176         struct pci_dev *pdev;
2177
2178         /* Find pci_dev container of dev */
2179         pdev = to_pci_dev(parent);
2180
2181         pci_free_consistent(pdev, size, vaddr, dma);
2182 }
2183
2184 /*
2185  * Configure CR/CSR space
2186  *
2187  * Access to the CR/CSR can be configured at power-up. The location of the
2188  * CR/CSR registers in the CR/CSR address space is determined by the boards
2189  * Auto-ID or Geographic address. This function ensures that the window is
2190  * enabled at an offset consistent with the boards geopgraphic address.
2191  *
2192  * Each board has a 512kB window, with the highest 4kB being used for the
2193  * boards registers, this means there is a fix length 508kB window which must
2194  * be mapped onto PCI memory.
2195  */
2196 static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2197         struct pci_dev *pdev)
2198 {
2199         u32 cbar, crat, vstat;
2200         u32 crcsr_bus_high, crcsr_bus_low;
2201         int retval;
2202         struct tsi148_driver *bridge;
2203
2204         bridge = tsi148_bridge->driver_priv;
2205
2206         /* Allocate mem for CR/CSR image */
2207         bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2208                                                      &bridge->crcsr_bus);
2209         if (!bridge->crcsr_kernel) {
2210                 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2211                         "CR/CSR image\n");
2212                 return -ENOMEM;
2213         }
2214
2215         reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2216
2217         iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2218         iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2219
2220         /* Ensure that the CR/CSR is configured at the correct offset */
2221         cbar = ioread32be(bridge->base + TSI148_CBAR);
2222         cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2223
2224         vstat = tsi148_slot_get(tsi148_bridge);
2225
2226         if (cbar != vstat) {
2227                 cbar = vstat;
2228                 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2229                 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2230         }
2231         dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2232
2233         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2234         if (crat & TSI148_LCSR_CRAT_EN)
2235                 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2236         else {
2237                 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2238                 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2239                         bridge->base + TSI148_LCSR_CRAT);
2240         }
2241
2242         /* If we want flushed, error-checked writes, set up a window
2243          * over the CR/CSR registers. We read from here to safely flush
2244          * through VME writes.
2245          */
2246         if (err_chk) {
2247                 retval = tsi148_master_set(bridge->flush_image, 1,
2248                         (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2249                         VME_D16);
2250                 if (retval)
2251                         dev_err(tsi148_bridge->parent, "Configuring flush image"
2252                                 " failed\n");
2253         }
2254
2255         return 0;
2256
2257 }
2258
2259 static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2260         struct pci_dev *pdev)
2261 {
2262         u32 crat;
2263         struct tsi148_driver *bridge;
2264
2265         bridge = tsi148_bridge->driver_priv;
2266
2267         /* Turn off CR/CSR space */
2268         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2269         iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2270                 bridge->base + TSI148_LCSR_CRAT);
2271
2272         /* Free image */
2273         iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2274         iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2275
2276         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2277                 bridge->crcsr_bus);
2278 }
2279
2280 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2281 {
2282         int retval, i, master_num;
2283         u32 data;
2284         struct list_head *pos = NULL, *n;
2285         struct vme_bridge *tsi148_bridge;
2286         struct tsi148_driver *tsi148_device;
2287         struct vme_master_resource *master_image;
2288         struct vme_slave_resource *slave_image;
2289         struct vme_dma_resource *dma_ctrlr;
2290         struct vme_lm_resource *lm;
2291
2292         /* If we want to support more than one of each bridge, we need to
2293          * dynamically generate this so we get one per device
2294          */
2295         tsi148_bridge = kzalloc(sizeof(*tsi148_bridge), GFP_KERNEL);
2296         if (!tsi148_bridge) {
2297                 retval = -ENOMEM;
2298                 goto err_struct;
2299         }
2300         vme_init_bridge(tsi148_bridge);
2301
2302         tsi148_device = kzalloc(sizeof(*tsi148_device), GFP_KERNEL);
2303         if (!tsi148_device) {
2304                 retval = -ENOMEM;
2305                 goto err_driver;
2306         }
2307
2308         tsi148_bridge->driver_priv = tsi148_device;
2309
2310         /* Enable the device */
2311         retval = pci_enable_device(pdev);
2312         if (retval) {
2313                 dev_err(&pdev->dev, "Unable to enable device\n");
2314                 goto err_enable;
2315         }
2316
2317         /* Map Registers */
2318         retval = pci_request_regions(pdev, driver_name);
2319         if (retval) {
2320                 dev_err(&pdev->dev, "Unable to reserve resources\n");
2321                 goto err_resource;
2322         }
2323
2324         /* map registers in BAR 0 */
2325         tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2326                 4096);
2327         if (!tsi148_device->base) {
2328                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2329                 retval = -EIO;
2330                 goto err_remap;
2331         }
2332
2333         /* Check to see if the mapping worked out */
2334         data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2335         if (data != PCI_VENDOR_ID_TUNDRA) {
2336                 dev_err(&pdev->dev, "CRG region check failed\n");
2337                 retval = -EIO;
2338                 goto err_test;
2339         }
2340
2341         /* Initialize wait queues & mutual exclusion flags */
2342         init_waitqueue_head(&tsi148_device->dma_queue[0]);
2343         init_waitqueue_head(&tsi148_device->dma_queue[1]);
2344         init_waitqueue_head(&tsi148_device->iack_queue);
2345         mutex_init(&tsi148_device->vme_int);
2346         mutex_init(&tsi148_device->vme_rmw);
2347
2348         tsi148_bridge->parent = &pdev->dev;
2349         strcpy(tsi148_bridge->name, driver_name);
2350
2351         /* Setup IRQ */
2352         retval = tsi148_irq_init(tsi148_bridge);
2353         if (retval != 0) {
2354                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2355                 goto err_irq;
2356         }
2357
2358         /* If we are going to flush writes, we need to read from the VME bus.
2359          * We need to do this safely, thus we read the devices own CR/CSR
2360          * register. To do this we must set up a window in CR/CSR space and
2361          * hence have one less master window resource available.
2362          */
2363         master_num = TSI148_MAX_MASTER;
2364         if (err_chk) {
2365                 master_num--;
2366
2367                 tsi148_device->flush_image =
2368                         kmalloc(sizeof(*tsi148_device->flush_image),
2369                                 GFP_KERNEL);
2370                 if (!tsi148_device->flush_image) {
2371                         retval = -ENOMEM;
2372                         goto err_master;
2373                 }
2374                 tsi148_device->flush_image->parent = tsi148_bridge;
2375                 spin_lock_init(&tsi148_device->flush_image->lock);
2376                 tsi148_device->flush_image->locked = 1;
2377                 tsi148_device->flush_image->number = master_num;
2378                 memset(&tsi148_device->flush_image->bus_resource, 0,
2379                        sizeof(tsi148_device->flush_image->bus_resource));
2380                 tsi148_device->flush_image->kern_base  = NULL;
2381         }
2382
2383         /* Add master windows to list */
2384         for (i = 0; i < master_num; i++) {
2385                 master_image = kmalloc(sizeof(*master_image), GFP_KERNEL);
2386                 if (!master_image) {
2387                         retval = -ENOMEM;
2388                         goto err_master;
2389                 }
2390                 master_image->parent = tsi148_bridge;
2391                 spin_lock_init(&master_image->lock);
2392                 master_image->locked = 0;
2393                 master_image->number = i;
2394                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2395                         VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2396                         VME_USER3 | VME_USER4;
2397                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2398                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2399                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2400                         VME_PROG | VME_DATA;
2401                 master_image->width_attr = VME_D16 | VME_D32;
2402                 memset(&master_image->bus_resource, 0,
2403                        sizeof(master_image->bus_resource));
2404                 master_image->kern_base  = NULL;
2405                 list_add_tail(&master_image->list,
2406                         &tsi148_bridge->master_resources);
2407         }
2408
2409         /* Add slave windows to list */
2410         for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2411                 slave_image = kmalloc(sizeof(*slave_image), GFP_KERNEL);
2412                 if (!slave_image) {
2413                         retval = -ENOMEM;
2414                         goto err_slave;
2415                 }
2416                 slave_image->parent = tsi148_bridge;
2417                 mutex_init(&slave_image->mtx);
2418                 slave_image->locked = 0;
2419                 slave_image->number = i;
2420                 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2421                         VME_A64;
2422                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2423                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2424                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2425                         VME_PROG | VME_DATA;
2426                 list_add_tail(&slave_image->list,
2427                         &tsi148_bridge->slave_resources);
2428         }
2429
2430         /* Add dma engines to list */
2431         for (i = 0; i < TSI148_MAX_DMA; i++) {
2432                 dma_ctrlr = kmalloc(sizeof(*dma_ctrlr), GFP_KERNEL);
2433                 if (!dma_ctrlr) {
2434                         retval = -ENOMEM;
2435                         goto err_dma;
2436                 }
2437                 dma_ctrlr->parent = tsi148_bridge;
2438                 mutex_init(&dma_ctrlr->mtx);
2439                 dma_ctrlr->locked = 0;
2440                 dma_ctrlr->number = i;
2441                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2442                         VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2443                         VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2444                         VME_DMA_PATTERN_TO_MEM;
2445                 INIT_LIST_HEAD(&dma_ctrlr->pending);
2446                 INIT_LIST_HEAD(&dma_ctrlr->running);
2447                 list_add_tail(&dma_ctrlr->list,
2448                         &tsi148_bridge->dma_resources);
2449         }
2450
2451         /* Add location monitor to list */
2452         lm = kmalloc(sizeof(*lm), GFP_KERNEL);
2453         if (!lm) {
2454                 retval = -ENOMEM;
2455                 goto err_lm;
2456         }
2457         lm->parent = tsi148_bridge;
2458         mutex_init(&lm->mtx);
2459         lm->locked = 0;
2460         lm->number = 1;
2461         lm->monitors = 4;
2462         list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
2463
2464         tsi148_bridge->slave_get = tsi148_slave_get;
2465         tsi148_bridge->slave_set = tsi148_slave_set;
2466         tsi148_bridge->master_get = tsi148_master_get;
2467         tsi148_bridge->master_set = tsi148_master_set;
2468         tsi148_bridge->master_read = tsi148_master_read;
2469         tsi148_bridge->master_write = tsi148_master_write;
2470         tsi148_bridge->master_rmw = tsi148_master_rmw;
2471         tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2472         tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2473         tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2474         tsi148_bridge->irq_set = tsi148_irq_set;
2475         tsi148_bridge->irq_generate = tsi148_irq_generate;
2476         tsi148_bridge->lm_set = tsi148_lm_set;
2477         tsi148_bridge->lm_get = tsi148_lm_get;
2478         tsi148_bridge->lm_attach = tsi148_lm_attach;
2479         tsi148_bridge->lm_detach = tsi148_lm_detach;
2480         tsi148_bridge->slot_get = tsi148_slot_get;
2481         tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2482         tsi148_bridge->free_consistent = tsi148_free_consistent;
2483
2484         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2485         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2486                 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2487         if (!geoid)
2488                 dev_info(&pdev->dev, "VME geographical address is %d\n",
2489                         data & TSI148_LCSR_VSTAT_GA_M);
2490         else
2491                 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2492                         geoid);
2493
2494         dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2495                 err_chk ? "enabled" : "disabled");
2496
2497         retval = tsi148_crcsr_init(tsi148_bridge, pdev);
2498         if (retval) {
2499                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2500                 goto err_crcsr;
2501         }
2502
2503         retval = vme_register_bridge(tsi148_bridge);
2504         if (retval != 0) {
2505                 dev_err(&pdev->dev, "Chip Registration failed.\n");
2506                 goto err_reg;
2507         }
2508
2509         pci_set_drvdata(pdev, tsi148_bridge);
2510
2511         /* Clear VME bus "board fail", and "power-up reset" lines */
2512         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2513         data &= ~TSI148_LCSR_VSTAT_BRDFL;
2514         data |= TSI148_LCSR_VSTAT_CPURST;
2515         iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2516
2517         return 0;
2518
2519 err_reg:
2520         tsi148_crcsr_exit(tsi148_bridge, pdev);
2521 err_crcsr:
2522 err_lm:
2523         /* resources are stored in link list */
2524         list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) {
2525                 lm = list_entry(pos, struct vme_lm_resource, list);
2526                 list_del(pos);
2527                 kfree(lm);
2528         }
2529 err_dma:
2530         /* resources are stored in link list */
2531         list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) {
2532                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2533                 list_del(pos);
2534                 kfree(dma_ctrlr);
2535         }
2536 err_slave:
2537         /* resources are stored in link list */
2538         list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) {
2539                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2540                 list_del(pos);
2541                 kfree(slave_image);
2542         }
2543 err_master:
2544         /* resources are stored in link list */
2545         list_for_each_safe(pos, n, &tsi148_bridge->master_resources) {
2546                 master_image = list_entry(pos, struct vme_master_resource,
2547                         list);
2548                 list_del(pos);
2549                 kfree(master_image);
2550         }
2551
2552         tsi148_irq_exit(tsi148_bridge, pdev);
2553 err_irq:
2554 err_test:
2555         iounmap(tsi148_device->base);
2556 err_remap:
2557         pci_release_regions(pdev);
2558 err_resource:
2559         pci_disable_device(pdev);
2560 err_enable:
2561         kfree(tsi148_device);
2562 err_driver:
2563         kfree(tsi148_bridge);
2564 err_struct:
2565         return retval;
2566
2567 }
2568
2569 static void tsi148_remove(struct pci_dev *pdev)
2570 {
2571         struct list_head *pos = NULL;
2572         struct list_head *tmplist;
2573         struct vme_master_resource *master_image;
2574         struct vme_slave_resource *slave_image;
2575         struct vme_dma_resource *dma_ctrlr;
2576         int i;
2577         struct tsi148_driver *bridge;
2578         struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2579
2580         bridge = tsi148_bridge->driver_priv;
2581
2582
2583         dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2584
2585         /*
2586          *  Shutdown all inbound and outbound windows.
2587          */
2588         for (i = 0; i < 8; i++) {
2589                 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2590                         TSI148_LCSR_OFFSET_ITAT);
2591                 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2592                         TSI148_LCSR_OFFSET_OTAT);
2593         }
2594
2595         /*
2596          *  Shutdown Location monitor.
2597          */
2598         iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2599
2600         /*
2601          *  Shutdown CRG map.
2602          */
2603         iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2604
2605         /*
2606          *  Clear error status.
2607          */
2608         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2609         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2610         iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2611
2612         /*
2613          *  Remove VIRQ interrupt (if any)
2614          */
2615         if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2616                 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2617
2618         /*
2619          *  Map all Interrupts to PCI INTA
2620          */
2621         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2622         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2623
2624         tsi148_irq_exit(tsi148_bridge, pdev);
2625
2626         vme_unregister_bridge(tsi148_bridge);
2627
2628         tsi148_crcsr_exit(tsi148_bridge, pdev);
2629
2630         /* resources are stored in link list */
2631         list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
2632                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2633                 list_del(pos);
2634                 kfree(dma_ctrlr);
2635         }
2636
2637         /* resources are stored in link list */
2638         list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
2639                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2640                 list_del(pos);
2641                 kfree(slave_image);
2642         }
2643
2644         /* resources are stored in link list */
2645         list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
2646                 master_image = list_entry(pos, struct vme_master_resource,
2647                         list);
2648                 list_del(pos);
2649                 kfree(master_image);
2650         }
2651
2652         iounmap(bridge->base);
2653
2654         pci_release_regions(pdev);
2655
2656         pci_disable_device(pdev);
2657
2658         kfree(tsi148_bridge->driver_priv);
2659
2660         kfree(tsi148_bridge);
2661 }
2662
2663 module_pci_driver(tsi148_driver);
2664
2665 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2666 module_param(err_chk, bool, 0);
2667
2668 MODULE_PARM_DESC(geoid, "Override geographical addressing");
2669 module_param(geoid, int, 0);
2670
2671 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2672 MODULE_LICENSE("GPL");