drivers/vme/bridges/vme_ca91cx42.c

   1 /*
   2  * Support for the Tundra Universe I/II VME-PCI Bridge Chips
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Derived from ca91c042.c by Michael Wyrick
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/pci.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/poll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/time.h>
  30 #include <linux/io.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/vme.h>
  33
  34 #include "../vme_bridge.h"
  35 #include "vme_ca91cx42.h"
  36
  37 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
  38 static void ca91cx42_remove(struct pci_dev *);
  39
  40 /* Module parameters */
  41 static int geoid;
  42
  43 static const char driver_name[] = "vme_ca91cx42";
  44
  45 static const struct pci_device_id ca91cx42_ids[] = {
  46         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
  47         { },
  48 };
  49
  50 MODULE_DEVICE_TABLE(pci, ca91cx42_ids);
  51
  52 static struct pci_driver ca91cx42_driver = {
  53         .name = driver_name,
  54         .id_table = ca91cx42_ids,
  55         .probe = ca91cx42_probe,
  56         .remove = ca91cx42_remove,
  57 };
  58
  59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
  60 {
  61         wake_up(&bridge->dma_queue);
  62
  63         return CA91CX42_LINT_DMA;
  64 }
  65
  66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
  67 {
  68         int i;
  69         u32 serviced = 0;
  70
  71         for (i = 0; i < 4; i++) {
  72                 if (stat & CA91CX42_LINT_LM[i]) {
  73                         /* We only enable interrupts if the callback is set */
  74                         bridge->lm_callback[i](bridge->lm_data[i]);
  75                         serviced |= CA91CX42_LINT_LM[i];
  76                 }
  77         }
  78
  79         return serviced;
  80 }
  81
  82 /* XXX This needs to be split into 4 queues */
  83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
  84 {
  85         wake_up(&bridge->mbox_queue);
  86
  87         return CA91CX42_LINT_MBOX;
  88 }
  89
  90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
  91 {
  92         wake_up(&bridge->iack_queue);
  93
  94         return CA91CX42_LINT_SW_IACK;
  95 }
  96
  97 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
  98 {
  99         int val;
 100         struct ca91cx42_driver *bridge;
 101
 102         bridge = ca91cx42_bridge->driver_priv;
 103
 104         val = ioread32(bridge->base + DGCS);
 105
 106         if (!(val & 0x00000800)) {
 107                 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
 108                         "Read Error DGCS=%08X\n", val);
 109         }
 110
 111         return CA91CX42_LINT_VERR;
 112 }
 113
 114 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
 115 {
 116         int val;
 117         struct ca91cx42_driver *bridge;
 118
 119         bridge = ca91cx42_bridge->driver_priv;
 120
 121         val = ioread32(bridge->base + DGCS);
 122
 123         if (!(val & 0x00000800))
 124                 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
 125                         "Read Error DGCS=%08X\n", val);
 126
 127         return CA91CX42_LINT_LERR;
 128 }
 129
 130
 131 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
 132         int stat)
 133 {
 134         int vec, i, serviced = 0;
 135         struct ca91cx42_driver *bridge;
 136
 137         bridge = ca91cx42_bridge->driver_priv;
 138
 139
 140         for (i = 7; i > 0; i--) {
 141                 if (stat & (1 << i)) {
 142                         vec = ioread32(bridge->base +
 143                                 CA91CX42_V_STATID[i]) & 0xff;
 144
 145                         vme_irq_handler(ca91cx42_bridge, i, vec);
 146
 147                         serviced |= (1 << i);
 148                 }
 149         }
 150
 151         return serviced;
 152 }
 153
 154 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
 155 {
 156         u32 stat, enable, serviced = 0;
 157         struct vme_bridge *ca91cx42_bridge;
 158         struct ca91cx42_driver *bridge;
 159
 160         ca91cx42_bridge = ptr;
 161
 162         bridge = ca91cx42_bridge->driver_priv;
 163
 164         enable = ioread32(bridge->base + LINT_EN);
 165         stat = ioread32(bridge->base + LINT_STAT);
 166
 167         /* Only look at unmasked interrupts */
 168         stat &= enable;
 169
 170         if (unlikely(!stat))
 171                 return IRQ_NONE;
 172
 173         if (stat & CA91CX42_LINT_DMA)
 174                 serviced |= ca91cx42_DMA_irqhandler(bridge);
 175         if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
 176                         CA91CX42_LINT_LM3))
 177                 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
 178         if (stat & CA91CX42_LINT_MBOX)
 179                 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
 180         if (stat & CA91CX42_LINT_SW_IACK)
 181                 serviced |= ca91cx42_IACK_irqhandler(bridge);
 182         if (stat & CA91CX42_LINT_VERR)
 183                 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
 184         if (stat & CA91CX42_LINT_LERR)
 185                 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
 186         if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
 187                         CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
 188                         CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
 189                         CA91CX42_LINT_VIRQ7))
 190                 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
 191
 192         /* Clear serviced interrupts */
 193         iowrite32(serviced, bridge->base + LINT_STAT);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
 199 {
 200         int result, tmp;
 201         struct pci_dev *pdev;
 202         struct ca91cx42_driver *bridge;
 203
 204         bridge = ca91cx42_bridge->driver_priv;
 205
 206         /* Need pdev */
 207         pdev = to_pci_dev(ca91cx42_bridge->parent);
 208
 209         /* Disable interrupts from PCI to VME */
 210         iowrite32(0, bridge->base + VINT_EN);
 211
 212         /* Disable PCI interrupts */
 213         iowrite32(0, bridge->base + LINT_EN);
 214         /* Clear Any Pending PCI Interrupts */
 215         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 216
 217         result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
 218                         driver_name, ca91cx42_bridge);
 219         if (result) {
 220                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 221                        pdev->irq);
 222                 return result;
 223         }
 224
 225         /* Ensure all interrupts are mapped to PCI Interrupt 0 */
 226         iowrite32(0, bridge->base + LINT_MAP0);
 227         iowrite32(0, bridge->base + LINT_MAP1);
 228         iowrite32(0, bridge->base + LINT_MAP2);
 229
 230         /* Enable DMA, mailbox & LM Interrupts */
 231         tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
 232                 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
 233                 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
 234
 235         iowrite32(tmp, bridge->base + LINT_EN);
 236
 237         return 0;
 238 }
 239
 240 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
 241         struct pci_dev *pdev)
 242 {
 243         struct vme_bridge *ca91cx42_bridge;
 244
 245         /* Disable interrupts from PCI to VME */
 246         iowrite32(0, bridge->base + VINT_EN);
 247
 248         /* Disable PCI interrupts */
 249         iowrite32(0, bridge->base + LINT_EN);
 250         /* Clear Any Pending PCI Interrupts */
 251         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 252
 253         ca91cx42_bridge = container_of((void *)bridge, struct vme_bridge,
 254                                        driver_priv);
 255         free_irq(pdev->irq, ca91cx42_bridge);
 256 }
 257
 258 static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
 259 {
 260         u32 tmp;
 261
 262         tmp = ioread32(bridge->base + LINT_STAT);
 263
 264         if (tmp & (1 << level))
 265                 return 0;
 266         else
 267                 return 1;
 268 }
 269
 270 /*
 271  * Set up an VME interrupt
 272  */
 273 static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
 274         int state, int sync)
 275
 276 {
 277         struct pci_dev *pdev;
 278         u32 tmp;
 279         struct ca91cx42_driver *bridge;
 280
 281         bridge = ca91cx42_bridge->driver_priv;
 282
 283         /* Enable IRQ level */
 284         tmp = ioread32(bridge->base + LINT_EN);
 285
 286         if (state == 0)
 287                 tmp &= ~CA91CX42_LINT_VIRQ[level];
 288         else
 289                 tmp |= CA91CX42_LINT_VIRQ[level];
 290
 291         iowrite32(tmp, bridge->base + LINT_EN);
 292
 293         if ((state == 0) && (sync != 0)) {
 294                 pdev = to_pci_dev(ca91cx42_bridge->parent);
 295
 296                 synchronize_irq(pdev->irq);
 297         }
 298 }
 299
 300 static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
 301         int statid)
 302 {
 303         u32 tmp;
 304         struct ca91cx42_driver *bridge;
 305
 306         bridge = ca91cx42_bridge->driver_priv;
 307
 308         /* Universe can only generate even vectors */
 309         if (statid & 1)
 310                 return -EINVAL;
 311
 312         mutex_lock(&bridge->vme_int);
 313
 314         tmp = ioread32(bridge->base + VINT_EN);
 315
 316         /* Set Status/ID */
 317         iowrite32(statid << 24, bridge->base + STATID);
 318
 319         /* Assert VMEbus IRQ */
 320         tmp = tmp | (1 << (level + 24));
 321         iowrite32(tmp, bridge->base + VINT_EN);
 322
 323         /* Wait for IACK */
 324         wait_event_interruptible(bridge->iack_queue,
 325                                  ca91cx42_iack_received(bridge, level));
 326
 327         /* Return interrupt to low state */
 328         tmp = ioread32(bridge->base + VINT_EN);
 329         tmp = tmp & ~(1 << (level + 24));
 330         iowrite32(tmp, bridge->base + VINT_EN);
 331
 332         mutex_unlock(&bridge->vme_int);
 333
 334         return 0;
 335 }
 336
 337 static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
 338         unsigned long long vme_base, unsigned long long size,
 339         dma_addr_t pci_base, u32 aspace, u32 cycle)
 340 {
 341         unsigned int i, addr = 0, granularity;
 342         unsigned int temp_ctl = 0;
 343         unsigned int vme_bound, pci_offset;
 344         struct vme_bridge *ca91cx42_bridge;
 345         struct ca91cx42_driver *bridge;
 346
 347         ca91cx42_bridge = image->parent;
 348
 349         bridge = ca91cx42_bridge->driver_priv;
 350
 351         i = image->number;
 352
 353         switch (aspace) {
 354         case VME_A16:
 355                 addr |= CA91CX42_VSI_CTL_VAS_A16;
 356                 break;
 357         case VME_A24:
 358                 addr |= CA91CX42_VSI_CTL_VAS_A24;
 359                 break;
 360         case VME_A32:
 361                 addr |= CA91CX42_VSI_CTL_VAS_A32;
 362                 break;
 363         case VME_USER1:
 364                 addr |= CA91CX42_VSI_CTL_VAS_USER1;
 365                 break;
 366         case VME_USER2:
 367                 addr |= CA91CX42_VSI_CTL_VAS_USER2;
 368                 break;
 369         case VME_A64:
 370         case VME_CRCSR:
 371         case VME_USER3:
 372         case VME_USER4:
 373         default:
 374                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 375                 return -EINVAL;
 376                 break;
 377         }
 378
 379         /*
 380          * Bound address is a valid address for the window, adjust
 381          * accordingly
 382          */
 383         vme_bound = vme_base + size;
 384         pci_offset = pci_base - vme_base;
 385
 386         if ((i == 0) || (i == 4))
 387                 granularity = 0x1000;
 388         else
 389                 granularity = 0x10000;
 390
 391         if (vme_base & (granularity - 1)) {
 392                 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
 393                         "alignment\n");
 394                 return -EINVAL;
 395         }
 396         if (vme_bound & (granularity - 1)) {
 397                 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
 398                         "alignment\n");
 399                 return -EINVAL;
 400         }
 401         if (pci_offset & (granularity - 1)) {
 402                 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
 403                         "alignment\n");
 404                 return -EINVAL;
 405         }
 406
 407         /* Disable while we are mucking around */
 408         temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 409         temp_ctl &= ~CA91CX42_VSI_CTL_EN;
 410         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 411
 412         /* Setup mapping */
 413         iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
 414         iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
 415         iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
 416
 417         /* Setup address space */
 418         temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
 419         temp_ctl |= addr;
 420
 421         /* Setup cycle types */
 422         temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
 423         if (cycle & VME_SUPER)
 424                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
 425         if (cycle & VME_USER)
 426                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
 427         if (cycle & VME_PROG)
 428                 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
 429         if (cycle & VME_DATA)
 430                 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
 431
 432         /* Write ctl reg without enable */
 433         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 434
 435         if (enabled)
 436                 temp_ctl |= CA91CX42_VSI_CTL_EN;
 437
 438         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 439
 440         return 0;
 441 }
 442
 443 static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
 444         unsigned long long *vme_base, unsigned long long *size,
 445         dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
 446 {
 447         unsigned int i, granularity = 0, ctl = 0;
 448         unsigned long long vme_bound, pci_offset;
 449         struct ca91cx42_driver *bridge;
 450
 451         bridge = image->parent->driver_priv;
 452
 453         i = image->number;
 454
 455         if ((i == 0) || (i == 4))
 456                 granularity = 0x1000;
 457         else
 458                 granularity = 0x10000;
 459
 460         /* Read Registers */
 461         ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 462
 463         *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
 464         vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
 465         pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
 466
 467         *pci_base = (dma_addr_t)*vme_base + pci_offset;
 468         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 469
 470         *enabled = 0;
 471         *aspace = 0;
 472         *cycle = 0;
 473
 474         if (ctl & CA91CX42_VSI_CTL_EN)
 475                 *enabled = 1;
 476
 477         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
 478                 *aspace = VME_A16;
 479         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
 480                 *aspace = VME_A24;
 481         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
 482                 *aspace = VME_A32;
 483         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
 484                 *aspace = VME_USER1;
 485         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
 486                 *aspace = VME_USER2;
 487
 488         if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
 489                 *cycle |= VME_SUPER;
 490         if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
 491                 *cycle |= VME_USER;
 492         if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
 493                 *cycle |= VME_PROG;
 494         if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
 495                 *cycle |= VME_DATA;
 496
 497         return 0;
 498 }
 499
 500 /*
 501  * Allocate and map PCI Resource
 502  */
 503 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
 504         unsigned long long size)
 505 {
 506         unsigned long long existing_size;
 507         int retval = 0;
 508         struct pci_dev *pdev;
 509         struct vme_bridge *ca91cx42_bridge;
 510
 511         ca91cx42_bridge = image->parent;
 512
 513         /* Find pci_dev container of dev */
 514         if (!ca91cx42_bridge->parent) {
 515                 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
 516                 return -EINVAL;
 517         }
 518         pdev = to_pci_dev(ca91cx42_bridge->parent);
 519
 520         existing_size = (unsigned long long)(image->bus_resource.end -
 521                 image->bus_resource.start);
 522
 523         /* If the existing size is OK, return */
 524         if (existing_size == (size - 1))
 525                 return 0;
 526
 527         if (existing_size != 0) {
 528                 iounmap(image->kern_base);
 529                 image->kern_base = NULL;
 530                 kfree(image->bus_resource.name);
 531                 release_resource(&image->bus_resource);
 532                 memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 533         }
 534
 535         if (!image->bus_resource.name) {
 536                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
 537                 if (!image->bus_resource.name) {
 538                         retval = -ENOMEM;
 539                         goto err_name;
 540                 }
 541         }
 542
 543         sprintf((char *)image->bus_resource.name, "%s.%d",
 544                 ca91cx42_bridge->name, image->number);
 545
 546         image->bus_resource.start = 0;
 547         image->bus_resource.end = (unsigned long)size;
 548         image->bus_resource.flags = IORESOURCE_MEM;
 549
 550         retval = pci_bus_alloc_resource(pdev->bus,
 551                 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
 552                 0, NULL, NULL);
 553         if (retval) {
 554                 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
 555                         "resource for window %d size 0x%lx start 0x%lx\n",
 556                         image->number, (unsigned long)size,
 557                         (unsigned long)image->bus_resource.start);
 558                 goto err_resource;
 559         }
 560
 561         image->kern_base = ioremap_nocache(
 562                 image->bus_resource.start, size);
 563         if (!image->kern_base) {
 564                 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
 565                 retval = -ENOMEM;
 566                 goto err_remap;
 567         }
 568
 569         return 0;
 570
 571 err_remap:
 572         release_resource(&image->bus_resource);
 573 err_resource:
 574         kfree(image->bus_resource.name);
 575         memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 576 err_name:
 577         return retval;
 578 }
 579
 580 /*
 581  * Free and unmap PCI Resource
 582  */
 583 static void ca91cx42_free_resource(struct vme_master_resource *image)
 584 {
 585         iounmap(image->kern_base);
 586         image->kern_base = NULL;
 587         release_resource(&image->bus_resource);
 588         kfree(image->bus_resource.name);
 589         memset(&image->bus_resource, 0, sizeof(image->bus_resource));
 590 }
 591
 592
 593 static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
 594         unsigned long long vme_base, unsigned long long size, u32 aspace,
 595         u32 cycle, u32 dwidth)
 596 {
 597         int retval = 0;
 598         unsigned int i, granularity = 0;
 599         unsigned int temp_ctl = 0;
 600         unsigned long long pci_bound, vme_offset, pci_base;
 601         struct vme_bridge *ca91cx42_bridge;
 602         struct ca91cx42_driver *bridge;
 603
 604         ca91cx42_bridge = image->parent;
 605
 606         bridge = ca91cx42_bridge->driver_priv;
 607
 608         i = image->number;
 609
 610         if ((i == 0) || (i == 4))
 611                 granularity = 0x1000;
 612         else
 613                 granularity = 0x10000;
 614
 615         /* Verify input data */
 616         if (vme_base & (granularity - 1)) {
 617                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 618                         "alignment\n");
 619                 retval = -EINVAL;
 620                 goto err_window;
 621         }
 622         if (size & (granularity - 1)) {
 623                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 624                         "alignment\n");
 625                 retval = -EINVAL;
 626                 goto err_window;
 627         }
 628
 629         spin_lock(&image->lock);
 630
 631         /*
 632          * Let's allocate the resource here rather than further up the stack as
 633          * it avoids pushing loads of bus dependent stuff up the stack
 634          */
 635         retval = ca91cx42_alloc_resource(image, size);
 636         if (retval) {
 637                 spin_unlock(&image->lock);
 638                 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
 639                         "for resource name\n");
 640                 retval = -ENOMEM;
 641                 goto err_res;
 642         }
 643
 644         pci_base = (unsigned long long)image->bus_resource.start;
 645
 646         /*
 647          * Bound address is a valid address for the window, adjust
 648          * according to window granularity.
 649          */
 650         pci_bound = pci_base + size;
 651         vme_offset = vme_base - pci_base;
 652
 653         /* Disable while we are mucking around */
 654         temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 655         temp_ctl &= ~CA91CX42_LSI_CTL_EN;
 656         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 657
 658         /* Setup cycle types */
 659         temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
 660         if (cycle & VME_BLT)
 661                 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
 662         if (cycle & VME_MBLT)
 663                 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
 664
 665         /* Setup data width */
 666         temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
 667         switch (dwidth) {
 668         case VME_D8:
 669                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
 670                 break;
 671         case VME_D16:
 672                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
 673                 break;
 674         case VME_D32:
 675                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
 676                 break;
 677         case VME_D64:
 678                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
 679                 break;
 680         default:
 681                 spin_unlock(&image->lock);
 682                 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
 683                 retval = -EINVAL;
 684                 goto err_dwidth;
 685                 break;
 686         }
 687
 688         /* Setup address space */
 689         temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
 690         switch (aspace) {
 691         case VME_A16:
 692                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
 693                 break;
 694         case VME_A24:
 695                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
 696                 break;
 697         case VME_A32:
 698                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
 699                 break;
 700         case VME_CRCSR:
 701                 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
 702                 break;
 703         case VME_USER1:
 704                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
 705                 break;
 706         case VME_USER2:
 707                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
 708                 break;
 709         case VME_A64:
 710         case VME_USER3:
 711         case VME_USER4:
 712         default:
 713                 spin_unlock(&image->lock);
 714                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 715                 retval = -EINVAL;
 716                 goto err_aspace;
 717                 break;
 718         }
 719
 720         temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
 721         if (cycle & VME_SUPER)
 722                 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
 723         if (cycle & VME_PROG)
 724                 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
 725
 726         /* Setup mapping */
 727         iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
 728         iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
 729         iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
 730
 731         /* Write ctl reg without enable */
 732         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 733
 734         if (enabled)
 735                 temp_ctl |= CA91CX42_LSI_CTL_EN;
 736
 737         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 738
 739         spin_unlock(&image->lock);
 740         return 0;
 741
 742 err_aspace:
 743 err_dwidth:
 744         ca91cx42_free_resource(image);
 745 err_res:
 746 err_window:
 747         return retval;
 748 }
 749
 750 static int __ca91cx42_master_get(struct vme_master_resource *image,
 751         int *enabled, unsigned long long *vme_base, unsigned long long *size,
 752         u32 *aspace, u32 *cycle, u32 *dwidth)
 753 {
 754         unsigned int i, ctl;
 755         unsigned long long pci_base, pci_bound, vme_offset;
 756         struct ca91cx42_driver *bridge;
 757
 758         bridge = image->parent->driver_priv;
 759
 760         i = image->number;
 761
 762         ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 763
 764         pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
 765         vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
 766         pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
 767
 768         *vme_base = pci_base + vme_offset;
 769         *size = (unsigned long long)(pci_bound - pci_base);
 770
 771         *enabled = 0;
 772         *aspace = 0;
 773         *cycle = 0;
 774         *dwidth = 0;
 775
 776         if (ctl & CA91CX42_LSI_CTL_EN)
 777                 *enabled = 1;
 778
 779         /* Setup address space */
 780         switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
 781         case CA91CX42_LSI_CTL_VAS_A16:
 782                 *aspace = VME_A16;
 783                 break;
 784         case CA91CX42_LSI_CTL_VAS_A24:
 785                 *aspace = VME_A24;
 786                 break;
 787         case CA91CX42_LSI_CTL_VAS_A32:
 788                 *aspace = VME_A32;
 789                 break;
 790         case CA91CX42_LSI_CTL_VAS_CRCSR:
 791                 *aspace = VME_CRCSR;
 792                 break;
 793         case CA91CX42_LSI_CTL_VAS_USER1:
 794                 *aspace = VME_USER1;
 795                 break;
 796         case CA91CX42_LSI_CTL_VAS_USER2:
 797                 *aspace = VME_USER2;
 798                 break;
 799         }
 800
 801         /* XXX Not sure howto check for MBLT */
 802         /* Setup cycle types */
 803         if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
 804                 *cycle |= VME_BLT;
 805         else
 806                 *cycle |= VME_SCT;
 807
 808         if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
 809                 *cycle |= VME_SUPER;
 810         else
 811                 *cycle |= VME_USER;
 812
 813         if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
 814                 *cycle = VME_PROG;
 815         else
 816                 *cycle = VME_DATA;
 817
 818         /* Setup data width */
 819         switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
 820         case CA91CX42_LSI_CTL_VDW_D8:
 821                 *dwidth = VME_D8;
 822                 break;
 823         case CA91CX42_LSI_CTL_VDW_D16:
 824                 *dwidth = VME_D16;
 825                 break;
 826         case CA91CX42_LSI_CTL_VDW_D32:
 827                 *dwidth = VME_D32;
 828                 break;
 829         case CA91CX42_LSI_CTL_VDW_D64:
 830                 *dwidth = VME_D64;
 831                 break;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 838         unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
 839         u32 *cycle, u32 *dwidth)
 840 {
 841         int retval;
 842
 843         spin_lock(&image->lock);
 844
 845         retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
 846                 cycle, dwidth);
 847
 848         spin_unlock(&image->lock);
 849
 850         return retval;
 851 }
 852
 853 static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
 854         void *buf, size_t count, loff_t offset)
 855 {
 856         ssize_t retval;
 857         void __iomem *addr = image->kern_base + offset;
 858         unsigned int done = 0;
 859         unsigned int count32;
 860
 861         if (count == 0)
 862                 return 0;
 863
 864         spin_lock(&image->lock);
 865
 866         /* The following code handles VME address alignment. We cannot use
 867          * memcpy_xxx here because it may cut data transfers in to 8-bit
 868          * cycles when D16 or D32 cycles are required on the VME bus.
 869          * On the other hand, the bridge itself assures that the maximum data
 870          * cycle configured for the transfer is used and splits it
 871          * automatically for non-aligned addresses, so we don't want the
 872          * overhead of needlessly forcing small transfers for the entire cycle.
 873          */
 874         if ((uintptr_t)addr & 0x1) {
 875                 *(u8 *)buf = ioread8(addr);
 876                 done += 1;
 877                 if (done == count)
 878                         goto out;
 879         }
 880         if ((uintptr_t)(addr + done) & 0x2) {
 881                 if ((count - done) < 2) {
 882                         *(u8 *)(buf + done) = ioread8(addr + done);
 883                         done += 1;
 884                         goto out;
 885                 } else {
 886                         *(u16 *)(buf + done) = ioread16(addr + done);
 887                         done += 2;
 888                 }
 889         }
 890
 891         count32 = (count - done) & ~0x3;
 892         while (done < count32) {
 893                 *(u32 *)(buf + done) = ioread32(addr + done);
 894                 done += 4;
 895         }
 896
 897         if ((count - done) & 0x2) {
 898                 *(u16 *)(buf + done) = ioread16(addr + done);
 899                 done += 2;
 900         }
 901         if ((count - done) & 0x1) {
 902                 *(u8 *)(buf + done) = ioread8(addr + done);
 903                 done += 1;
 904         }
 905 out:
 906         retval = count;
 907         spin_unlock(&image->lock);
 908
 909         return retval;
 910 }
 911
 912 static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
 913         void *buf, size_t count, loff_t offset)
 914 {
 915         ssize_t retval;
 916         void __iomem *addr = image->kern_base + offset;
 917         unsigned int done = 0;
 918         unsigned int count32;
 919
 920         if (count == 0)
 921                 return 0;
 922
 923         spin_lock(&image->lock);
 924
 925         /* Here we apply for the same strategy we do in master_read
 926          * function in order to assure the correct cycles.
 927          */
 928         if ((uintptr_t)addr & 0x1) {
 929                 iowrite8(*(u8 *)buf, addr);
 930                 done += 1;
 931                 if (done == count)
 932                         goto out;
 933         }
 934         if ((uintptr_t)(addr + done) & 0x2) {
 935                 if ((count - done) < 2) {
 936                         iowrite8(*(u8 *)(buf + done), addr + done);
 937                         done += 1;
 938                         goto out;
 939                 } else {
 940                         iowrite16(*(u16 *)(buf + done), addr + done);
 941                         done += 2;
 942                 }
 943         }
 944
 945         count32 = (count - done) & ~0x3;
 946         while (done < count32) {
 947                 iowrite32(*(u32 *)(buf + done), addr + done);
 948                 done += 4;
 949         }
 950
 951         if ((count - done) & 0x2) {
 952                 iowrite16(*(u16 *)(buf + done), addr + done);
 953                 done += 2;
 954         }
 955         if ((count - done) & 0x1) {
 956                 iowrite8(*(u8 *)(buf + done), addr + done);
 957                 done += 1;
 958         }
 959 out:
 960         retval = count;
 961
 962         spin_unlock(&image->lock);
 963
 964         return retval;
 965 }
 966
 967 static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
 968         unsigned int mask, unsigned int compare, unsigned int swap,
 969         loff_t offset)
 970 {
 971         u32 result;
 972         uintptr_t pci_addr;
 973         struct ca91cx42_driver *bridge;
 974         struct device *dev;
 975
 976         bridge = image->parent->driver_priv;
 977         dev = image->parent->parent;
 978
 979         /* Find the PCI address that maps to the desired VME address */
 980
 981         /* Locking as we can only do one of these at a time */
 982         mutex_lock(&bridge->vme_rmw);
 983
 984         /* Lock image */
 985         spin_lock(&image->lock);
 986
 987         pci_addr = (uintptr_t)image->kern_base + offset;
 988
 989         /* Address must be 4-byte aligned */
 990         if (pci_addr & 0x3) {
 991                 dev_err(dev, "RMW Address not 4-byte aligned\n");
 992                 result = -EINVAL;
 993                 goto out;
 994         }
 995
 996         /* Ensure RMW Disabled whilst configuring */
 997         iowrite32(0, bridge->base + SCYC_CTL);
 998
 999         /* Configure registers */
1000         iowrite32(mask, bridge->base + SCYC_EN);
1001         iowrite32(compare, bridge->base + SCYC_CMP);
1002         iowrite32(swap, bridge->base + SCYC_SWP);
1003         iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1004
1005         /* Enable RMW */
1006         iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1007
1008         /* Kick process off with a read to the required address. */
1009         result = ioread32(image->kern_base + offset);
1010
1011         /* Disable RMW */
1012         iowrite32(0, bridge->base + SCYC_CTL);
1013
1014 out:
1015         spin_unlock(&image->lock);
1016
1017         mutex_unlock(&bridge->vme_rmw);
1018
1019         return result;
1020 }
1021
1022 static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1023         struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1024 {
1025         struct ca91cx42_dma_entry *entry, *prev;
1026         struct vme_dma_pci *pci_attr;
1027         struct vme_dma_vme *vme_attr;
1028         dma_addr_t desc_ptr;
1029         int retval = 0;
1030         struct device *dev;
1031
1032         dev = list->parent->parent->parent;
1033
1034         /* XXX descriptor must be aligned on 64-bit boundaries */
1035         entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1036         if (!entry) {
1037                 retval = -ENOMEM;
1038                 goto err_mem;
1039         }
1040
1041         /* Test descriptor alignment */
1042         if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1043                 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1044                         "required: %p\n", &entry->descriptor);
1045                 retval = -EINVAL;
1046                 goto err_align;
1047         }
1048
1049         memset(&entry->descriptor, 0, sizeof(entry->descriptor));
1050
1051         if (dest->type == VME_DMA_VME) {
1052                 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1053                 vme_attr = dest->private;
1054                 pci_attr = src->private;
1055         } else {
1056                 vme_attr = src->private;
1057                 pci_attr = dest->private;
1058         }
1059
1060         /* Check we can do fulfill required attributes */
1061         if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1062                 VME_USER2)) != 0) {
1063
1064                 dev_err(dev, "Unsupported cycle type\n");
1065                 retval = -EINVAL;
1066                 goto err_aspace;
1067         }
1068
1069         if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1070                 VME_PROG | VME_DATA)) != 0) {
1071
1072                 dev_err(dev, "Unsupported cycle type\n");
1073                 retval = -EINVAL;
1074                 goto err_cycle;
1075         }
1076
1077         /* Check to see if we can fulfill source and destination */
1078         if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1079                 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1080
1081                 dev_err(dev, "Cannot perform transfer with this "
1082                         "source-destination combination\n");
1083                 retval = -EINVAL;
1084                 goto err_direct;
1085         }
1086
1087         /* Setup cycle types */
1088         if (vme_attr->cycle & VME_BLT)
1089                 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1090
1091         /* Setup data width */
1092         switch (vme_attr->dwidth) {
1093         case VME_D8:
1094                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1095                 break;
1096         case VME_D16:
1097                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1098                 break;
1099         case VME_D32:
1100                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1101                 break;
1102         case VME_D64:
1103                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1104                 break;
1105         default:
1106                 dev_err(dev, "Invalid data width\n");
1107                 return -EINVAL;
1108         }
1109
1110         /* Setup address space */
1111         switch (vme_attr->aspace) {
1112         case VME_A16:
1113                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1114                 break;
1115         case VME_A24:
1116                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1117                 break;
1118         case VME_A32:
1119                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1120                 break;
1121         case VME_USER1:
1122                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1123                 break;
1124         case VME_USER2:
1125                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1126                 break;
1127         default:
1128                 dev_err(dev, "Invalid address space\n");
1129                 return -EINVAL;
1130                 break;
1131         }
1132
1133         if (vme_attr->cycle & VME_SUPER)
1134                 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1135         if (vme_attr->cycle & VME_PROG)
1136                 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1137
1138         entry->descriptor.dtbc = count;
1139         entry->descriptor.dla = pci_attr->address;
1140         entry->descriptor.dva = vme_attr->address;
1141         entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1142
1143         /* Add to list */
1144         list_add_tail(&entry->list, &list->entries);
1145
1146         /* Fill out previous descriptors "Next Address" */
1147         if (entry->list.prev != &list->entries) {
1148                 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1149                         list);
1150                 /* We need the bus address for the pointer */
1151                 desc_ptr = virt_to_bus(&entry->descriptor);
1152                 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1153         }
1154
1155         return 0;
1156
1157 err_cycle:
1158 err_aspace:
1159 err_direct:
1160 err_align:
1161         kfree(entry);
1162 err_mem:
1163         return retval;
1164 }
1165
1166 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1167 {
1168         u32 tmp;
1169         struct ca91cx42_driver *bridge;
1170
1171         bridge = ca91cx42_bridge->driver_priv;
1172
1173         tmp = ioread32(bridge->base + DGCS);
1174
1175         if (tmp & CA91CX42_DGCS_ACT)
1176                 return 0;
1177         else
1178                 return 1;
1179 }
1180
1181 static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1182 {
1183         struct vme_dma_resource *ctrlr;
1184         struct ca91cx42_dma_entry *entry;
1185         int retval;
1186         dma_addr_t bus_addr;
1187         u32 val;
1188         struct device *dev;
1189         struct ca91cx42_driver *bridge;
1190
1191         ctrlr = list->parent;
1192
1193         bridge = ctrlr->parent->driver_priv;
1194         dev = ctrlr->parent->parent;
1195
1196         mutex_lock(&ctrlr->mtx);
1197
1198         if (!(list_empty(&ctrlr->running))) {
1199                 /*
1200                  * XXX We have an active DMA transfer and currently haven't
1201                  *     sorted out the mechanism for "pending" DMA transfers.
1202                  *     Return busy.
1203                  */
1204                 /* Need to add to pending here */
1205                 mutex_unlock(&ctrlr->mtx);
1206                 return -EBUSY;
1207         } else {
1208                 list_add(&list->list, &ctrlr->running);
1209         }
1210
1211         /* Get first bus address and write into registers */
1212         entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1213                 list);
1214
1215         bus_addr = virt_to_bus(&entry->descriptor);
1216
1217         mutex_unlock(&ctrlr->mtx);
1218
1219         iowrite32(0, bridge->base + DTBC);
1220         iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1221
1222         /* Start the operation */
1223         val = ioread32(bridge->base + DGCS);
1224
1225         /* XXX Could set VMEbus On and Off Counters here */
1226         val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1227
1228         val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1229                 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1230                 CA91CX42_DGCS_PERR);
1231
1232         iowrite32(val, bridge->base + DGCS);
1233
1234         val |= CA91CX42_DGCS_GO;
1235
1236         iowrite32(val, bridge->base + DGCS);
1237
1238         retval = wait_event_interruptible(bridge->dma_queue,
1239                                           ca91cx42_dma_busy(ctrlr->parent));
1240
1241         if (retval) {
1242                 val = ioread32(bridge->base + DGCS);
1243                 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS);
1244                 /* Wait for the operation to abort */
1245                 wait_event(bridge->dma_queue,
1246                            ca91cx42_dma_busy(ctrlr->parent));
1247                 retval = -EINTR;
1248                 goto exit;
1249         }
1250
1251         /*
1252          * Read status register, this register is valid until we kick off a
1253          * new transfer.
1254          */
1255         val = ioread32(bridge->base + DGCS);
1256
1257         if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1258                 CA91CX42_DGCS_PERR)) {
1259
1260                 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1261                 val = ioread32(bridge->base + DCTL);
1262                 retval = -EIO;
1263         }
1264
1265 exit:
1266         /* Remove list from running list */
1267         mutex_lock(&ctrlr->mtx);
1268         list_del(&list->list);
1269         mutex_unlock(&ctrlr->mtx);
1270
1271         return retval;
1272
1273 }
1274
1275 static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1276 {
1277         struct list_head *pos, *temp;
1278         struct ca91cx42_dma_entry *entry;
1279
1280         /* detach and free each entry */
1281         list_for_each_safe(pos, temp, &list->entries) {
1282                 list_del(pos);
1283                 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1284                 kfree(entry);
1285         }
1286
1287         return 0;
1288 }
1289
1290 /*
1291  * All 4 location monitors reside at the same base - this is therefore a
1292  * system wide configuration.
1293  *
1294  * This does not enable the LM monitor - that should be done when the first
1295  * callback is attached and disabled when the last callback is removed.
1296  */
1297 static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1298         unsigned long long lm_base, u32 aspace, u32 cycle)
1299 {
1300         u32 temp_base, lm_ctl = 0;
1301         int i;
1302         struct ca91cx42_driver *bridge;
1303         struct device *dev;
1304
1305         bridge = lm->parent->driver_priv;
1306         dev = lm->parent->parent;
1307
1308         /* Check the alignment of the location monitor */
1309         temp_base = (u32)lm_base;
1310         if (temp_base & 0xffff) {
1311                 dev_err(dev, "Location monitor must be aligned to 64KB "
1312                         "boundary");
1313                 return -EINVAL;
1314         }
1315
1316         mutex_lock(&lm->mtx);
1317
1318         /* If we already have a callback attached, we can't move it! */
1319         for (i = 0; i < lm->monitors; i++) {
1320                 if (bridge->lm_callback[i]) {
1321                         mutex_unlock(&lm->mtx);
1322                         dev_err(dev, "Location monitor callback attached, "
1323                                 "can't reset\n");
1324                         return -EBUSY;
1325                 }
1326         }
1327
1328         switch (aspace) {
1329         case VME_A16:
1330                 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1331                 break;
1332         case VME_A24:
1333                 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1334                 break;
1335         case VME_A32:
1336                 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1337                 break;
1338         default:
1339                 mutex_unlock(&lm->mtx);
1340                 dev_err(dev, "Invalid address space\n");
1341                 return -EINVAL;
1342                 break;
1343         }
1344
1345         if (cycle & VME_SUPER)
1346                 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1347         if (cycle & VME_USER)
1348                 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1349         if (cycle & VME_PROG)
1350                 lm_ctl |= CA91CX42_LM_CTL_PGM;
1351         if (cycle & VME_DATA)
1352                 lm_ctl |= CA91CX42_LM_CTL_DATA;
1353
1354         iowrite32(lm_base, bridge->base + LM_BS);
1355         iowrite32(lm_ctl, bridge->base + LM_CTL);
1356
1357         mutex_unlock(&lm->mtx);
1358
1359         return 0;
1360 }
1361
1362 /* Get configuration of the callback monitor and return whether it is enabled
1363  * or disabled.
1364  */
1365 static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1366         unsigned long long *lm_base, u32 *aspace, u32 *cycle)
1367 {
1368         u32 lm_ctl, enabled = 0;
1369         struct ca91cx42_driver *bridge;
1370
1371         bridge = lm->parent->driver_priv;
1372
1373         mutex_lock(&lm->mtx);
1374
1375         *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1376         lm_ctl = ioread32(bridge->base + LM_CTL);
1377
1378         if (lm_ctl & CA91CX42_LM_CTL_EN)
1379                 enabled = 1;
1380
1381         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1382                 *aspace = VME_A16;
1383         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1384                 *aspace = VME_A24;
1385         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1386                 *aspace = VME_A32;
1387
1388         *cycle = 0;
1389         if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1390                 *cycle |= VME_SUPER;
1391         if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1392                 *cycle |= VME_USER;
1393         if (lm_ctl & CA91CX42_LM_CTL_PGM)
1394                 *cycle |= VME_PROG;
1395         if (lm_ctl & CA91CX42_LM_CTL_DATA)
1396                 *cycle |= VME_DATA;
1397
1398         mutex_unlock(&lm->mtx);
1399
1400         return enabled;
1401 }
1402
1403 /*
1404  * Attach a callback to a specific location monitor.
1405  *
1406  * Callback will be passed the monitor triggered.
1407  */
1408 static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1409         void (*callback)(void *), void *data)
1410 {
1411         u32 lm_ctl, tmp;
1412         struct ca91cx42_driver *bridge;
1413         struct device *dev;
1414
1415         bridge = lm->parent->driver_priv;
1416         dev = lm->parent->parent;
1417
1418         mutex_lock(&lm->mtx);
1419
1420         /* Ensure that the location monitor is configured - need PGM or DATA */
1421         lm_ctl = ioread32(bridge->base + LM_CTL);
1422         if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1423                 mutex_unlock(&lm->mtx);
1424                 dev_err(dev, "Location monitor not properly configured\n");
1425                 return -EINVAL;
1426         }
1427
1428         /* Check that a callback isn't already attached */
1429         if (bridge->lm_callback[monitor]) {
1430                 mutex_unlock(&lm->mtx);
1431                 dev_err(dev, "Existing callback attached\n");
1432                 return -EBUSY;
1433         }
1434
1435         /* Attach callback */
1436         bridge->lm_callback[monitor] = callback;
1437         bridge->lm_data[monitor] = data;
1438
1439         /* Enable Location Monitor interrupt */
1440         tmp = ioread32(bridge->base + LINT_EN);
1441         tmp |= CA91CX42_LINT_LM[monitor];
1442         iowrite32(tmp, bridge->base + LINT_EN);
1443
1444         /* Ensure that global Location Monitor Enable set */
1445         if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1446                 lm_ctl |= CA91CX42_LM_CTL_EN;
1447                 iowrite32(lm_ctl, bridge->base + LM_CTL);
1448         }
1449
1450         mutex_unlock(&lm->mtx);
1451
1452         return 0;
1453 }
1454
1455 /*
1456  * Detach a callback function forn a specific location monitor.
1457  */
1458 static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1459 {
1460         u32 tmp;
1461         struct ca91cx42_driver *bridge;
1462
1463         bridge = lm->parent->driver_priv;
1464
1465         mutex_lock(&lm->mtx);
1466
1467         /* Disable Location Monitor and ensure previous interrupts are clear */
1468         tmp = ioread32(bridge->base + LINT_EN);
1469         tmp &= ~CA91CX42_LINT_LM[monitor];
1470         iowrite32(tmp, bridge->base + LINT_EN);
1471
1472         iowrite32(CA91CX42_LINT_LM[monitor],
1473                  bridge->base + LINT_STAT);
1474
1475         /* Detach callback */
1476         bridge->lm_callback[monitor] = NULL;
1477         bridge->lm_data[monitor] = NULL;
1478
1479         /* If all location monitors disabled, disable global Location Monitor */
1480         if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1481                         CA91CX42_LINT_LM3)) == 0) {
1482                 tmp = ioread32(bridge->base + LM_CTL);
1483                 tmp &= ~CA91CX42_LM_CTL_EN;
1484                 iowrite32(tmp, bridge->base + LM_CTL);
1485         }
1486
1487         mutex_unlock(&lm->mtx);
1488
1489         return 0;
1490 }
1491
1492 static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1493 {
1494         u32 slot = 0;
1495         struct ca91cx42_driver *bridge;
1496
1497         bridge = ca91cx42_bridge->driver_priv;
1498
1499         if (!geoid) {
1500                 slot = ioread32(bridge->base + VCSR_BS);
1501                 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1502         } else
1503                 slot = geoid;
1504
1505         return (int)slot;
1506
1507 }
1508
1509 static void *ca91cx42_alloc_consistent(struct device *parent, size_t size,
1510         dma_addr_t *dma)
1511 {
1512         struct pci_dev *pdev;
1513
1514         /* Find pci_dev container of dev */
1515         pdev = to_pci_dev(parent);
1516
1517         return pci_alloc_consistent(pdev, size, dma);
1518 }
1519
1520 static void ca91cx42_free_consistent(struct device *parent, size_t size,
1521         void *vaddr, dma_addr_t dma)
1522 {
1523         struct pci_dev *pdev;
1524
1525         /* Find pci_dev container of dev */
1526         pdev = to_pci_dev(parent);
1527
1528         pci_free_consistent(pdev, size, vaddr, dma);
1529 }
1530
1531 /*
1532  * Configure CR/CSR space
1533  *
1534  * Access to the CR/CSR can be configured at power-up. The location of the
1535  * CR/CSR registers in the CR/CSR address space is determined by the boards
1536  * Auto-ID or Geographic address. This function ensures that the window is
1537  * enabled at an offset consistent with the boards geopgraphic address.
1538  */
1539 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1540         struct pci_dev *pdev)
1541 {
1542         unsigned int crcsr_addr;
1543         int tmp, slot;
1544         struct ca91cx42_driver *bridge;
1545
1546         bridge = ca91cx42_bridge->driver_priv;
1547
1548         slot = ca91cx42_slot_get(ca91cx42_bridge);
1549
1550         /* Write CSR Base Address if slot ID is supplied as a module param */
1551         if (geoid)
1552                 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1553
1554         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1555         if (slot == 0) {
1556                 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1557                         "CR/CSR space\n");
1558                 return -EINVAL;
1559         }
1560
1561         /* Allocate mem for CR/CSR image */
1562         bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1563                                                      &bridge->crcsr_bus);
1564         if (!bridge->crcsr_kernel) {
1565                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1566                         "image\n");
1567                 return -ENOMEM;
1568         }
1569
1570         crcsr_addr = slot * (512 * 1024);
1571         iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1572
1573         tmp = ioread32(bridge->base + VCSR_CTL);
1574         tmp |= CA91CX42_VCSR_CTL_EN;
1575         iowrite32(tmp, bridge->base + VCSR_CTL);
1576
1577         return 0;
1578 }
1579
1580 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1581         struct pci_dev *pdev)
1582 {
1583         u32 tmp;
1584         struct ca91cx42_driver *bridge;
1585
1586         bridge = ca91cx42_bridge->driver_priv;
1587
1588         /* Turn off CR/CSR space */
1589         tmp = ioread32(bridge->base + VCSR_CTL);
1590         tmp &= ~CA91CX42_VCSR_CTL_EN;
1591         iowrite32(tmp, bridge->base + VCSR_CTL);
1592
1593         /* Free image */
1594         iowrite32(0, bridge->base + VCSR_TO);
1595
1596         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1597                 bridge->crcsr_bus);
1598 }
1599
1600 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1601 {
1602         int retval, i;
1603         u32 data;
1604         struct list_head *pos = NULL, *n;
1605         struct vme_bridge *ca91cx42_bridge;
1606         struct ca91cx42_driver *ca91cx42_device;
1607         struct vme_master_resource *master_image;
1608         struct vme_slave_resource *slave_image;
1609         struct vme_dma_resource *dma_ctrlr;
1610         struct vme_lm_resource *lm;
1611
1612         /* We want to support more than one of each bridge so we need to
1613          * dynamically allocate the bridge structure
1614          */
1615         ca91cx42_bridge = kzalloc(sizeof(*ca91cx42_bridge), GFP_KERNEL);
1616         if (!ca91cx42_bridge) {
1617                 retval = -ENOMEM;
1618                 goto err_struct;
1619         }
1620         vme_init_bridge(ca91cx42_bridge);
1621
1622         ca91cx42_device = kzalloc(sizeof(*ca91cx42_device), GFP_KERNEL);
1623         if (!ca91cx42_device) {
1624                 retval = -ENOMEM;
1625                 goto err_driver;
1626         }
1627
1628         ca91cx42_bridge->driver_priv = ca91cx42_device;
1629
1630         /* Enable the device */
1631         retval = pci_enable_device(pdev);
1632         if (retval) {
1633                 dev_err(&pdev->dev, "Unable to enable device\n");
1634                 goto err_enable;
1635         }
1636
1637         /* Map Registers */
1638         retval = pci_request_regions(pdev, driver_name);
1639         if (retval) {
1640                 dev_err(&pdev->dev, "Unable to reserve resources\n");
1641                 goto err_resource;
1642         }
1643
1644         /* map registers in BAR 0 */
1645         ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1646                 4096);
1647         if (!ca91cx42_device->base) {
1648                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1649                 retval = -EIO;
1650                 goto err_remap;
1651         }
1652
1653         /* Check to see if the mapping worked out */
1654         data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1655         if (data != PCI_VENDOR_ID_TUNDRA) {
1656                 dev_err(&pdev->dev, "PCI_ID check failed\n");
1657                 retval = -EIO;
1658                 goto err_test;
1659         }
1660
1661         /* Initialize wait queues & mutual exclusion flags */
1662         init_waitqueue_head(&ca91cx42_device->dma_queue);
1663         init_waitqueue_head(&ca91cx42_device->iack_queue);
1664         mutex_init(&ca91cx42_device->vme_int);
1665         mutex_init(&ca91cx42_device->vme_rmw);
1666
1667         ca91cx42_bridge->parent = &pdev->dev;
1668         strcpy(ca91cx42_bridge->name, driver_name);
1669
1670         /* Setup IRQ */
1671         retval = ca91cx42_irq_init(ca91cx42_bridge);
1672         if (retval != 0) {
1673                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1674                 goto err_irq;
1675         }
1676
1677         /* Add master windows to list */
1678         for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1679                 master_image = kmalloc(sizeof(*master_image), GFP_KERNEL);
1680                 if (!master_image) {
1681                         retval = -ENOMEM;
1682                         goto err_master;
1683                 }
1684                 master_image->parent = ca91cx42_bridge;
1685                 spin_lock_init(&master_image->lock);
1686                 master_image->locked = 0;
1687                 master_image->number = i;
1688                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1689                         VME_CRCSR | VME_USER1 | VME_USER2;
1690                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1691                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1692                 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1693                 memset(&master_image->bus_resource, 0,
1694                        sizeof(master_image->bus_resource));
1695                 master_image->kern_base  = NULL;
1696                 list_add_tail(&master_image->list,
1697                         &ca91cx42_bridge->master_resources);
1698         }
1699
1700         /* Add slave windows to list */
1701         for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1702                 slave_image = kmalloc(sizeof(*slave_image), GFP_KERNEL);
1703                 if (!slave_image) {
1704                         retval = -ENOMEM;
1705                         goto err_slave;
1706                 }
1707                 slave_image->parent = ca91cx42_bridge;
1708                 mutex_init(&slave_image->mtx);
1709                 slave_image->locked = 0;
1710                 slave_image->number = i;
1711                 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1712                         VME_USER2;
1713
1714                 /* Only windows 0 and 4 support A16 */
1715                 if (i == 0 || i == 4)
1716                         slave_image->address_attr |= VME_A16;
1717
1718                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1719                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1720                 list_add_tail(&slave_image->list,
1721                         &ca91cx42_bridge->slave_resources);
1722         }
1723
1724         /* Add dma engines to list */
1725         for (i = 0; i < CA91C142_MAX_DMA; i++) {
1726                 dma_ctrlr = kmalloc(sizeof(*dma_ctrlr), GFP_KERNEL);
1727                 if (!dma_ctrlr) {
1728                         retval = -ENOMEM;
1729                         goto err_dma;
1730                 }
1731                 dma_ctrlr->parent = ca91cx42_bridge;
1732                 mutex_init(&dma_ctrlr->mtx);
1733                 dma_ctrlr->locked = 0;
1734                 dma_ctrlr->number = i;
1735                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1736                         VME_DMA_MEM_TO_VME;
1737                 INIT_LIST_HEAD(&dma_ctrlr->pending);
1738                 INIT_LIST_HEAD(&dma_ctrlr->running);
1739                 list_add_tail(&dma_ctrlr->list,
1740                         &ca91cx42_bridge->dma_resources);
1741         }
1742
1743         /* Add location monitor to list */
1744         lm = kmalloc(sizeof(*lm), GFP_KERNEL);
1745         if (!lm) {
1746                 retval = -ENOMEM;
1747                 goto err_lm;
1748         }
1749         lm->parent = ca91cx42_bridge;
1750         mutex_init(&lm->mtx);
1751         lm->locked = 0;
1752         lm->number = 1;
1753         lm->monitors = 4;
1754         list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1755
1756         ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1757         ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1758         ca91cx42_bridge->master_get = ca91cx42_master_get;
1759         ca91cx42_bridge->master_set = ca91cx42_master_set;
1760         ca91cx42_bridge->master_read = ca91cx42_master_read;
1761         ca91cx42_bridge->master_write = ca91cx42_master_write;
1762         ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1763         ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1764         ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1765         ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1766         ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1767         ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1768         ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1769         ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1770         ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1771         ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1772         ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1773         ca91cx42_bridge->alloc_consistent = ca91cx42_alloc_consistent;
1774         ca91cx42_bridge->free_consistent = ca91cx42_free_consistent;
1775
1776         data = ioread32(ca91cx42_device->base + MISC_CTL);
1777         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1778                 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1779         dev_info(&pdev->dev, "Slot ID is %d\n",
1780                 ca91cx42_slot_get(ca91cx42_bridge));
1781
1782         if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1783                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1784
1785         /* Need to save ca91cx42_bridge pointer locally in link list for use in
1786          * ca91cx42_remove()
1787          */
1788         retval = vme_register_bridge(ca91cx42_bridge);
1789         if (retval != 0) {
1790                 dev_err(&pdev->dev, "Chip Registration failed.\n");
1791                 goto err_reg;
1792         }
1793
1794         pci_set_drvdata(pdev, ca91cx42_bridge);
1795
1796         return 0;
1797
1798 err_reg:
1799         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1800 err_lm:
1801         /* resources are stored in link list */
1802         list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1803                 lm = list_entry(pos, struct vme_lm_resource, list);
1804                 list_del(pos);
1805                 kfree(lm);
1806         }
1807 err_dma:
1808         /* resources are stored in link list */
1809         list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1810                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1811                 list_del(pos);
1812                 kfree(dma_ctrlr);
1813         }
1814 err_slave:
1815         /* resources are stored in link list */
1816         list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1817                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1818                 list_del(pos);
1819                 kfree(slave_image);
1820         }
1821 err_master:
1822         /* resources are stored in link list */
1823         list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1824                 master_image = list_entry(pos, struct vme_master_resource,
1825                         list);
1826                 list_del(pos);
1827                 kfree(master_image);
1828         }
1829
1830         ca91cx42_irq_exit(ca91cx42_device, pdev);
1831 err_irq:
1832 err_test:
1833         iounmap(ca91cx42_device->base);
1834 err_remap:
1835         pci_release_regions(pdev);
1836 err_resource:
1837         pci_disable_device(pdev);
1838 err_enable:
1839         kfree(ca91cx42_device);
1840 err_driver:
1841         kfree(ca91cx42_bridge);
1842 err_struct:
1843         return retval;
1844
1845 }
1846
1847 static void ca91cx42_remove(struct pci_dev *pdev)
1848 {
1849         struct list_head *pos = NULL, *n;
1850         struct vme_master_resource *master_image;
1851         struct vme_slave_resource *slave_image;
1852         struct vme_dma_resource *dma_ctrlr;
1853         struct vme_lm_resource *lm;
1854         struct ca91cx42_driver *bridge;
1855         struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1856
1857         bridge = ca91cx42_bridge->driver_priv;
1858
1859
1860         /* Turn off Ints */
1861         iowrite32(0, bridge->base + LINT_EN);
1862
1863         /* Turn off the windows */
1864         iowrite32(0x00800000, bridge->base + LSI0_CTL);
1865         iowrite32(0x00800000, bridge->base + LSI1_CTL);
1866         iowrite32(0x00800000, bridge->base + LSI2_CTL);
1867         iowrite32(0x00800000, bridge->base + LSI3_CTL);
1868         iowrite32(0x00800000, bridge->base + LSI4_CTL);
1869         iowrite32(0x00800000, bridge->base + LSI5_CTL);
1870         iowrite32(0x00800000, bridge->base + LSI6_CTL);
1871         iowrite32(0x00800000, bridge->base + LSI7_CTL);
1872         iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1873         iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1874         iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1875         iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1876         iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1877         iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1878         iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1879         iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1880
1881         vme_unregister_bridge(ca91cx42_bridge);
1882
1883         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1884
1885         /* resources are stored in link list */
1886         list_for_each_safe(pos, n, &ca91cx42_bridge->lm_resources) {
1887                 lm = list_entry(pos, struct vme_lm_resource, list);
1888                 list_del(pos);
1889                 kfree(lm);
1890         }
1891
1892         /* resources are stored in link list */
1893         list_for_each_safe(pos, n, &ca91cx42_bridge->dma_resources) {
1894                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1895                 list_del(pos);
1896                 kfree(dma_ctrlr);
1897         }
1898
1899         /* resources are stored in link list */
1900         list_for_each_safe(pos, n, &ca91cx42_bridge->slave_resources) {
1901                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1902                 list_del(pos);
1903                 kfree(slave_image);
1904         }
1905
1906         /* resources are stored in link list */
1907         list_for_each_safe(pos, n, &ca91cx42_bridge->master_resources) {
1908                 master_image = list_entry(pos, struct vme_master_resource,
1909                         list);
1910                 list_del(pos);
1911                 kfree(master_image);
1912         }
1913
1914         ca91cx42_irq_exit(bridge, pdev);
1915
1916         iounmap(bridge->base);
1917
1918         pci_release_regions(pdev);
1919
1920         pci_disable_device(pdev);
1921
1922         kfree(ca91cx42_bridge);
1923 }
1924
1925 module_pci_driver(ca91cx42_driver);
1926
1927 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1928 module_param(geoid, int, 0);
1929
1930 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1931 MODULE_LICENSE("GPL");