2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
13 * the implied warranty of MERCHANTABILITY or FITNESS FOR
14 * A PARTICULAR PURPOSE.See the GNU General Public License
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 * clock and PLL management functions
26 #include <linux/kernel.h>
27 #include <linux/via-core.h>
29 #include "via_clock.h"
33 static const char *via_slap = "Please slap VIA Technologies to motivate them "
34 "releasing full documentation for your platform!\n";
36 static inline u32 cle266_encode_pll(struct via_pll_config pll)
38 return (pll.multiplier << 8)
43 static inline u32 k800_encode_pll(struct via_pll_config pll)
45 return ((pll.divisor - 2) << 16)
47 | (pll.multiplier - 2);
50 static inline u32 vx855_encode_pll(struct via_pll_config pll)
52 return (pll.divisor << 16)
57 static inline void cle266_set_primary_pll_encoded(u32 data)
59 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
60 via_write_reg(VIASR, 0x46, data & 0xFF);
61 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
62 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
65 static inline void k800_set_primary_pll_encoded(u32 data)
67 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
68 via_write_reg(VIASR, 0x44, data & 0xFF);
69 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
70 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
71 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
74 static inline void cle266_set_secondary_pll_encoded(u32 data)
76 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
77 via_write_reg(VIASR, 0x44, data & 0xFF);
78 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
79 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
82 static inline void k800_set_secondary_pll_encoded(u32 data)
84 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
85 via_write_reg(VIASR, 0x4A, data & 0xFF);
86 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
87 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
88 via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
91 static inline void set_engine_pll_encoded(u32 data)
93 via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
94 via_write_reg(VIASR, 0x47, data & 0xFF);
95 via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
96 via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
97 via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
100 static void cle266_set_primary_pll(struct via_pll_config config)
102 cle266_set_primary_pll_encoded(cle266_encode_pll(config));
105 static void k800_set_primary_pll(struct via_pll_config config)
107 k800_set_primary_pll_encoded(k800_encode_pll(config));
110 static void vx855_set_primary_pll(struct via_pll_config config)
112 k800_set_primary_pll_encoded(vx855_encode_pll(config));
115 static void cle266_set_secondary_pll(struct via_pll_config config)
117 cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
120 static void k800_set_secondary_pll(struct via_pll_config config)
122 k800_set_secondary_pll_encoded(k800_encode_pll(config));
125 static void vx855_set_secondary_pll(struct via_pll_config config)
127 k800_set_secondary_pll_encoded(vx855_encode_pll(config));
130 static void k800_set_engine_pll(struct via_pll_config config)
132 set_engine_pll_encoded(k800_encode_pll(config));
135 static void vx855_set_engine_pll(struct via_pll_config config)
137 set_engine_pll_encoded(vx855_encode_pll(config));
140 static void set_primary_pll_state(u8 state)
155 via_write_reg_mask(VIASR, 0x2D, value, 0x30);
158 static void set_secondary_pll_state(u8 state)
173 via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
176 static void set_engine_pll_state(u8 state)
191 via_write_reg_mask(VIASR, 0x2D, value, 0x03);
194 static void set_primary_clock_state(u8 state)
209 via_write_reg_mask(VIASR, 0x1B, value, 0x30);
212 static void set_secondary_clock_state(u8 state)
227 via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
230 static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
238 case VIA_CLKSRC_TVX1:
241 case VIA_CLKSRC_TVPLL:
242 data = 0x04; /* 0x06 should be the same */
244 case VIA_CLKSRC_DVP1TVCLKR:
247 case VIA_CLKSRC_CAP0:
250 case VIA_CLKSRC_CAP1:
261 static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
263 u8 data = set_clock_source_common(source, use_pll) << 4;
264 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
267 static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
269 u8 data = set_clock_source_common(source, use_pll);
270 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
273 static void dummy_set_clock_state(u8 state)
275 printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
278 static void dummy_set_clock_source(enum via_clksrc source, bool use_pll)
280 printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
283 static void dummy_set_pll_state(u8 state)
285 printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);
288 static void dummy_set_pll(struct via_pll_config config)
290 printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);
293 static void noop_set_clock_state(u8 state)
297 void via_clock_init(struct via_clock *clock, int gfx_chip)
300 case UNICHROME_CLE266:
302 clock->set_primary_clock_state = dummy_set_clock_state;
303 clock->set_primary_clock_source = dummy_set_clock_source;
304 clock->set_primary_pll_state = dummy_set_pll_state;
305 clock->set_primary_pll = cle266_set_primary_pll;
307 clock->set_secondary_clock_state = dummy_set_clock_state;
308 clock->set_secondary_clock_source = dummy_set_clock_source;
309 clock->set_secondary_pll_state = dummy_set_pll_state;
310 clock->set_secondary_pll = cle266_set_secondary_pll;
312 clock->set_engine_pll_state = dummy_set_pll_state;
313 clock->set_engine_pll = dummy_set_pll;
316 case UNICHROME_PM800:
317 case UNICHROME_CN700:
318 case UNICHROME_CX700:
319 case UNICHROME_CN750:
320 case UNICHROME_K8M890:
321 case UNICHROME_P4M890:
322 case UNICHROME_P4M900:
323 case UNICHROME_VX800:
324 clock->set_primary_clock_state = set_primary_clock_state;
325 clock->set_primary_clock_source = set_primary_clock_source;
326 clock->set_primary_pll_state = set_primary_pll_state;
327 clock->set_primary_pll = k800_set_primary_pll;
329 clock->set_secondary_clock_state = set_secondary_clock_state;
330 clock->set_secondary_clock_source = set_secondary_clock_source;
331 clock->set_secondary_pll_state = set_secondary_pll_state;
332 clock->set_secondary_pll = k800_set_secondary_pll;
334 clock->set_engine_pll_state = set_engine_pll_state;
335 clock->set_engine_pll = k800_set_engine_pll;
337 case UNICHROME_VX855:
338 case UNICHROME_VX900:
339 clock->set_primary_clock_state = set_primary_clock_state;
340 clock->set_primary_clock_source = set_primary_clock_source;
341 clock->set_primary_pll_state = set_primary_pll_state;
342 clock->set_primary_pll = vx855_set_primary_pll;
344 clock->set_secondary_clock_state = set_secondary_clock_state;
345 clock->set_secondary_clock_source = set_secondary_clock_source;
346 clock->set_secondary_pll_state = set_secondary_pll_state;
347 clock->set_secondary_pll = vx855_set_secondary_pll;
349 clock->set_engine_pll_state = set_engine_pll_state;
350 clock->set_engine_pll = vx855_set_engine_pll;
355 if (machine_is_olpc()) {
356 /* The OLPC XO-1.5 cannot suspend/resume reliably if the
357 * IGA1/IGA2 clocks are set as on or off (memory rot
358 * occasionally happens during suspend under such
361 * The only known stable scenario is to leave this bits as-is,
362 * which in their default states are documented to enable the
363 * clock only when it is needed.
365 clock->set_primary_clock_state = noop_set_clock_state;
366 clock->set_secondary_clock_state = noop_set_clock_state;