1 // SPDX-License-Identifier: GPL-2.0-only
3 * Frame buffer driver for Trident TGUI, Blade and Image series
5 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
6 * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
8 * CREDITS:(in order of appearance)
9 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
10 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
11 * much inspired by the XFree86 4.x Trident driver sources
12 * by Alan Hourihane the FreeVGA project
13 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
16 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <video/vga.h>
27 #include <video/trident.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
32 struct tridentfb_par {
33 void __iomem *io_virt; /* iospace virtual memory address */
37 void (*init_accel) (struct tridentfb_par *, int, int);
38 void (*wait_engine) (struct tridentfb_par *);
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
44 (struct tridentfb_par *par, const char*,
45 u32, u32, u32, u32, u32, u32);
46 unsigned char eng_oper; /* engine operation... */
48 struct i2c_adapter ddc_adapter;
49 struct i2c_algo_bit_data ddc_algo;
52 static struct fb_fix_screeninfo tridentfb_fix = {
54 .type = FB_TYPE_PACKED_PIXELS,
56 .visual = FB_VISUAL_PSEUDOCOLOR,
57 .accel = FB_ACCEL_NONE,
60 /* defaults which are normally overriden by user values */
63 static char *mode_option;
78 module_param(mode_option, charp, 0);
79 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
80 module_param_named(mode, mode_option, charp, 0);
81 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
82 module_param(bpp, int, 0);
83 module_param(center, int, 0);
84 module_param(stretch, int, 0);
85 module_param(noaccel, int, 0);
86 module_param(memsize, int, 0);
87 module_param(memdiff, int, 0);
88 module_param(nativex, int, 0);
89 module_param(fp, int, 0);
90 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
91 module_param(crt, int, 0);
92 MODULE_PARM_DESC(crt, "Define if CRT is connected");
94 static inline int is_oldclock(int id)
96 return (id == TGUI9440) ||
101 static inline int is_oldprotect(int id)
103 return is_oldclock(id) ||
104 (id == PROVIDIA9685) ||
109 static inline int is_blade(int id)
111 return (id == BLADE3D) ||
112 (id == CYBERBLADEE4) ||
113 (id == CYBERBLADEi7) ||
114 (id == CYBERBLADEi7D) ||
115 (id == CYBERBLADEi1) ||
116 (id == CYBERBLADEi1D) ||
117 (id == CYBERBLADEAi1) ||
118 (id == CYBERBLADEAi1D);
121 static inline int is_xp(int id)
123 return (id == CYBERBLADEXPAi1) ||
124 (id == CYBERBLADEXPm8) ||
125 (id == CYBERBLADEXPm16);
128 static inline int is3Dchip(int id)
130 return is_blade(id) || is_xp(id) ||
131 (id == CYBER9397) || (id == CYBER9397DVD) ||
132 (id == CYBER9520) || (id == CYBER9525DVD) ||
133 (id == IMAGE975) || (id == IMAGE985);
136 static inline int iscyber(int id)
152 case CYBERBLADEXPAi1:
156 case CYBERBLADEi7: /* VIA MPV4 integrated version */
158 /* case CYBERBLDAEXPm8: Strange */
159 /* case CYBERBLDAEXPm16: Strange */
164 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
166 fb_writeb(val, p->io_virt + reg);
169 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
171 return fb_readb(p->io_virt + reg);
174 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
176 fb_writel(v, par->io_virt + r);
179 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
181 return fb_readl(par->io_virt + r);
184 #define DDC_SDA_TGUI BIT(0)
185 #define DDC_SCL_TGUI BIT(1)
186 #define DDC_SCL_DRIVE_TGUI BIT(2)
187 #define DDC_SDA_DRIVE_TGUI BIT(3)
188 #define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
190 static void tridentfb_ddc_setscl_tgui(void *data, int val)
192 struct tridentfb_par *par = data;
193 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
196 reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
198 reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
200 vga_mm_wcrt(par->io_virt, I2C, reg);
203 static void tridentfb_ddc_setsda_tgui(void *data, int val)
205 struct tridentfb_par *par = data;
206 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
209 reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
211 reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
213 vga_mm_wcrt(par->io_virt, I2C, reg);
216 static int tridentfb_ddc_getsda_tgui(void *data)
218 struct tridentfb_par *par = data;
220 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
223 #define DDC_SDA_IN BIT(0)
224 #define DDC_SCL_OUT BIT(1)
225 #define DDC_SDA_OUT BIT(3)
226 #define DDC_SCL_IN BIT(6)
227 #define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT)
229 static void tridentfb_ddc_setscl(void *data, int val)
231 struct tridentfb_par *par = data;
234 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
239 vga_mm_wcrt(par->io_virt, I2C, reg);
242 static void tridentfb_ddc_setsda(void *data, int val)
244 struct tridentfb_par *par = data;
247 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
252 vga_mm_wcrt(par->io_virt, I2C, reg);
255 static int tridentfb_ddc_getscl(void *data)
257 struct tridentfb_par *par = data;
259 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
262 static int tridentfb_ddc_getsda(void *data)
264 struct tridentfb_par *par = data;
266 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
269 static int tridentfb_setup_ddc_bus(struct fb_info *info)
271 struct tridentfb_par *par = info->par;
273 strlcpy(par->ddc_adapter.name, info->fix.id,
274 sizeof(par->ddc_adapter.name));
275 par->ddc_adapter.owner = THIS_MODULE;
276 par->ddc_adapter.class = I2C_CLASS_DDC;
277 par->ddc_adapter.algo_data = &par->ddc_algo;
278 par->ddc_adapter.dev.parent = info->device;
279 if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
280 par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
281 par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
282 par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
285 par->ddc_algo.setsda = tridentfb_ddc_setsda;
286 par->ddc_algo.setscl = tridentfb_ddc_setscl;
287 par->ddc_algo.getsda = tridentfb_ddc_getsda;
288 par->ddc_algo.getscl = tridentfb_ddc_getscl;
290 par->ddc_algo.udelay = 10;
291 par->ddc_algo.timeout = 20;
292 par->ddc_algo.data = par;
294 i2c_set_adapdata(&par->ddc_adapter, par);
296 return i2c_bit_add_bus(&par->ddc_adapter);
300 * Blade specific acceleration.
303 #define point(x, y) ((y) << 16 | (x))
305 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
307 int v1 = (pitch >> 3) << 20;
308 int tmp = bpp == 24 ? 2 : (bpp >> 4);
309 int v2 = v1 | (tmp << 29);
311 writemmr(par, 0x21C0, v2);
312 writemmr(par, 0x21C4, v2);
313 writemmr(par, 0x21B8, v2);
314 writemmr(par, 0x21BC, v2);
315 writemmr(par, 0x21D0, v1);
316 writemmr(par, 0x21D4, v1);
317 writemmr(par, 0x21C8, v1);
318 writemmr(par, 0x21CC, v1);
319 writemmr(par, 0x216C, 0);
322 static void blade_wait_engine(struct tridentfb_par *par)
324 while (readmmr(par, STATUS) & 0xFA800000)
328 static void blade_fill_rect(struct tridentfb_par *par,
329 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
331 writemmr(par, COLOR, c);
332 writemmr(par, ROP, rop ? ROP_X : ROP_S);
333 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
335 writemmr(par, DST1, point(x, y));
336 writemmr(par, DST2, point(x + w - 1, y + h - 1));
339 static void blade_image_blit(struct tridentfb_par *par, const char *data,
340 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
342 unsigned size = ((w + 31) >> 5) * h;
344 writemmr(par, COLOR, c);
345 writemmr(par, BGCOLOR, b);
346 writemmr(par, CMD, 0xa0000000 | 3 << 19);
348 writemmr(par, DST1, point(x, y));
349 writemmr(par, DST2, point(x + w - 1, y + h - 1));
351 iowrite32_rep(par->io_virt + 0x10000, data, size);
354 static void blade_copy_rect(struct tridentfb_par *par,
355 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
358 u32 s1 = point(x1, y1);
359 u32 s2 = point(x1 + w - 1, y1 + h - 1);
360 u32 d1 = point(x2, y2);
361 u32 d2 = point(x2 + w - 1, y2 + h - 1);
363 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
366 writemmr(par, ROP, ROP_S);
367 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
369 writemmr(par, SRC1, direction ? s2 : s1);
370 writemmr(par, SRC2, direction ? s1 : s2);
371 writemmr(par, DST1, direction ? d2 : d1);
372 writemmr(par, DST2, direction ? d1 : d2);
376 * BladeXP specific acceleration functions
379 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
381 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
382 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
384 switch (pitch << (bpp >> 3)) {
400 t_outb(par, x, 0x2125);
402 par->eng_oper = x | 0x40;
404 writemmr(par, 0x2154, v1);
405 writemmr(par, 0x2150, v1);
406 t_outb(par, 3, 0x2126);
409 static void xp_wait_engine(struct tridentfb_par *par)
414 while (t_inb(par, STATUS) & 0x80) {
416 if (count == 10000000) {
422 t_outb(par, 0x00, STATUS);
430 static void xp_fill_rect(struct tridentfb_par *par,
431 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
433 writemmr(par, 0x2127, ROP_P);
434 writemmr(par, 0x2158, c);
435 writemmr(par, DRAWFL, 0x4000);
436 writemmr(par, OLDDIM, point(h, w));
437 writemmr(par, OLDDST, point(y, x));
438 t_outb(par, 0x01, OLDCMD);
439 t_outb(par, par->eng_oper, 0x2125);
442 static void xp_copy_rect(struct tridentfb_par *par,
443 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
445 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
446 int direction = 0x0004;
448 if ((x1 < x2) && (y1 == y2)) {
466 writemmr(par, DRAWFL, direction);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
469 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
470 writemmr(par, OLDDIM, point(h, w));
471 t_outb(par, 0x01, OLDCMD);
475 * Image specific acceleration functions
477 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
479 int tmp = bpp == 24 ? 2: (bpp >> 4);
481 writemmr(par, 0x2120, 0xF0000000);
482 writemmr(par, 0x2120, 0x40000000 | tmp);
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2144, 0x00000000);
485 writemmr(par, 0x2148, 0x00000000);
486 writemmr(par, 0x2150, 0x00000000);
487 writemmr(par, 0x2154, 0x00000000);
488 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
489 writemmr(par, 0x216C, 0x00000000);
490 writemmr(par, 0x2170, 0x00000000);
491 writemmr(par, 0x217C, 0x00000000);
492 writemmr(par, 0x2120, 0x10000000);
493 writemmr(par, 0x2130, (2047 << 16) | 2047);
496 static void image_wait_engine(struct tridentfb_par *par)
498 while (readmmr(par, 0x2164) & 0xF0000000)
502 static void image_fill_rect(struct tridentfb_par *par,
503 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
505 writemmr(par, 0x2120, 0x80000000);
506 writemmr(par, 0x2120, 0x90000000 | ROP_S);
508 writemmr(par, 0x2144, c);
510 writemmr(par, DST1, point(x, y));
511 writemmr(par, DST2, point(x + w - 1, y + h - 1));
513 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
516 static void image_copy_rect(struct tridentfb_par *par,
517 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
520 u32 s1 = point(x1, y1);
521 u32 s2 = point(x1 + w - 1, y1 + h - 1);
522 u32 d1 = point(x2, y2);
523 u32 d2 = point(x2 + w - 1, y2 + h - 1);
525 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
528 writemmr(par, 0x2120, 0x80000000);
529 writemmr(par, 0x2120, 0x90000000 | ROP_S);
531 writemmr(par, SRC1, direction ? s2 : s1);
532 writemmr(par, SRC2, direction ? s1 : s2);
533 writemmr(par, DST1, direction ? d2 : d1);
534 writemmr(par, DST2, direction ? d1 : d2);
535 writemmr(par, 0x2124,
536 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
540 * TGUI 9440/96XX acceleration
543 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
545 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
547 /* disable clipping */
548 writemmr(par, 0x2148, 0);
549 writemmr(par, 0x214C, point(4095, 2047));
551 switch ((pitch * bpp) / 8) {
567 fb_writew(x, par->io_virt + 0x2122);
570 static void tgui_fill_rect(struct tridentfb_par *par,
571 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
573 t_outb(par, ROP_P, 0x2127);
574 writemmr(par, OLDCLR, c);
575 writemmr(par, DRAWFL, 0x4020);
576 writemmr(par, OLDDIM, point(w - 1, h - 1));
577 writemmr(par, OLDDST, point(x, y));
578 t_outb(par, 1, OLDCMD);
581 static void tgui_copy_rect(struct tridentfb_par *par,
582 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
585 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
587 if ((x1 < x2) && (y1 == y2)) {
605 writemmr(par, DRAWFL, 0x4 | flags);
606 t_outb(par, ROP_S, 0x2127);
607 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
608 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
609 writemmr(par, OLDDIM, point(w - 1, h - 1));
610 t_outb(par, 1, OLDCMD);
614 * Accel functions called by the upper layers
616 static void tridentfb_fillrect(struct fb_info *info,
617 const struct fb_fillrect *fr)
619 struct tridentfb_par *par = info->par;
622 if (info->flags & FBINFO_HWACCEL_DISABLED) {
623 cfb_fillrect(info, fr);
626 if (info->var.bits_per_pixel == 8) {
631 col = ((u32 *)(info->pseudo_palette))[fr->color];
633 par->wait_engine(par);
634 par->fill_rect(par, fr->dx, fr->dy, fr->width,
635 fr->height, col, fr->rop);
638 static void tridentfb_imageblit(struct fb_info *info,
639 const struct fb_image *img)
641 struct tridentfb_par *par = info->par;
644 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
645 cfb_imageblit(info, img);
648 if (info->var.bits_per_pixel == 8) {
652 bgcol = img->bg_color;
654 bgcol |= bgcol << 16;
656 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
657 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
660 par->wait_engine(par);
662 par->image_blit(par, img->data, img->dx, img->dy,
663 img->width, img->height, col, bgcol);
665 cfb_imageblit(info, img);
668 static void tridentfb_copyarea(struct fb_info *info,
669 const struct fb_copyarea *ca)
671 struct tridentfb_par *par = info->par;
673 if (info->flags & FBINFO_HWACCEL_DISABLED) {
674 cfb_copyarea(info, ca);
677 par->wait_engine(par);
678 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
679 ca->width, ca->height);
682 static int tridentfb_sync(struct fb_info *info)
684 struct tridentfb_par *par = info->par;
686 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
687 par->wait_engine(par);
692 * Hardware access functions
695 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
697 return vga_mm_rcrt(par->io_virt, reg);
700 static inline void write3X4(struct tridentfb_par *par, int reg,
703 vga_mm_wcrt(par->io_virt, reg, val);
706 static inline unsigned char read3CE(struct tridentfb_par *par,
709 return vga_mm_rgfx(par->io_virt, reg);
712 static inline void writeAttr(struct tridentfb_par *par, int reg,
715 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
716 vga_mm_wattr(par->io_virt, reg, val);
719 static inline void write3CE(struct tridentfb_par *par, int reg,
722 vga_mm_wgfx(par->io_virt, reg, val);
725 static void enable_mmio(struct tridentfb_par *par)
730 /* Unprotect registers */
731 vga_io_wseq(NewMode1, 0x80);
732 if (!is_oldprotect(par->chip_id))
733 vga_io_wseq(Protection, 0x92);
737 outb(inb(0x3D5) | 0x01, 0x3D5);
740 static void disable_mmio(struct tridentfb_par *par)
743 vga_mm_rseq(par->io_virt, 0x0B);
745 /* Unprotect registers */
746 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
747 if (!is_oldprotect(par->chip_id))
748 vga_mm_wseq(par->io_virt, Protection, 0x92);
751 t_outb(par, PCIReg, 0x3D4);
752 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
755 static inline void crtc_unlock(struct tridentfb_par *par)
757 write3X4(par, VGA_CRTC_V_SYNC_END,
758 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
761 /* Return flat panel's maximum x resolution */
762 static int get_nativex(struct tridentfb_par *par)
769 tmp = (read3CE(par, VertStretch) >> 4) & 3;
787 output("%dx%d flat panel found\n", x, y);
792 static inline void set_lwidth(struct tridentfb_par *par, int width)
794 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
795 /* chips older than TGUI9660 have only 1 width bit in AddColReg */
796 /* touching the other one breaks I2C/DDC */
797 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
798 write3X4(par, AddColReg,
799 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
801 write3X4(par, AddColReg,
802 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
805 /* For resolutions smaller than FP resolution stretch */
806 static void screen_stretch(struct tridentfb_par *par)
808 if (par->chip_id != CYBERBLADEXPAi1)
809 write3CE(par, BiosReg, 0);
811 write3CE(par, BiosReg, 8);
812 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
813 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
816 /* For resolutions smaller than FP resolution center */
817 static inline void screen_center(struct tridentfb_par *par)
819 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
820 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
823 /* Address of first shown pixel in display memory */
824 static void set_screen_start(struct tridentfb_par *par, int base)
827 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
828 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
829 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
830 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
831 tmp = read3X4(par, CRTHiOrd) & 0xF8;
832 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
835 /* Set dotclock frequency */
836 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
839 unsigned long fi, d, di;
840 unsigned char best_m = 0, best_n = 0, best_k = 0;
841 unsigned char hi, lo;
842 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
845 for (k = shift; k >= 0; k--)
846 for (m = 1; m < 32; m++) {
847 n = ((m + 2) << shift) - 8;
848 for (n = (n < 0 ? 0 : n); n < 122; n++) {
849 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
851 if (di < d || (di == d && k == best_k)) {
862 if (is_oldclock(par->chip_id)) {
863 lo = best_n | (best_m << 7);
864 hi = (best_m >> 1) | (best_k << 4);
867 hi = best_m | (best_k << 6);
870 if (is3Dchip(par->chip_id)) {
871 vga_mm_wseq(par->io_virt, ClockHigh, hi);
872 vga_mm_wseq(par->io_virt, ClockLow, lo);
874 t_outb(par, lo, 0x43C8);
875 t_outb(par, hi, 0x43C9);
877 debug("VCLK = %X %X\n", hi, lo);
880 /* Set number of lines for flat panels*/
881 static void set_number_of_lines(struct tridentfb_par *par, int lines)
883 int tmp = read3CE(par, CyberEnhance) & 0x8F;
886 else if (lines > 768)
888 else if (lines > 600)
890 else if (lines > 480)
892 write3CE(par, CyberEnhance, tmp);
896 * If we see that FP is active we assume we have one.
897 * Otherwise we have a CRT display. User can override.
899 static int is_flatpanel(struct tridentfb_par *par)
903 if (crt || !iscyber(par->chip_id))
905 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
908 /* Try detecting the video memory size */
909 static unsigned int get_memsize(struct tridentfb_par *par)
911 unsigned char tmp, tmp2;
914 /* If memory size provided by user */
918 switch (par->chip_id) {
923 tmp = read3X4(par, SPR) & 0x0F;
939 k = 10 * Mb; /* XP */
945 k = 12 * Mb; /* XP */
948 k = 14 * Mb; /* XP */
951 k = 16 * Mb; /* XP */
955 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
985 output("framebuffer size = %d Kb\n", k / Kb);
989 /* See if we can handle the video mode described in var */
990 static int tridentfb_check_var(struct fb_var_screeninfo *var,
991 struct fb_info *info)
993 struct tridentfb_par *par = info->par;
994 int bpp = var->bits_per_pixel;
996 int ramdac = 230000; /* 230MHz for most 3D chips */
1002 /* check color depth */
1004 bpp = var->bits_per_pixel = 32;
1005 if (bpp != 8 && bpp != 16 && bpp != 32)
1007 if (par->chip_id == TGUI9440 && bpp == 32)
1009 /* check whether resolution fits on panel and in memory */
1010 if (par->flatpanel && nativex && var->xres > nativex)
1012 /* various resolution checks */
1013 var->xres = (var->xres + 7) & ~0x7;
1014 if (var->xres > var->xres_virtual)
1015 var->xres_virtual = var->xres;
1016 if (var->yres > var->yres_virtual)
1017 var->yres_virtual = var->yres;
1018 if (var->xres_virtual > 4095 || var->yres > 2048)
1020 /* prevent from position overflow for acceleration */
1021 if (var->yres_virtual > 0xffff)
1023 line_length = var->xres_virtual * bpp / 8;
1025 if (!is3Dchip(par->chip_id) &&
1026 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
1027 /* acceleration requires line length to be power of 2 */
1028 if (line_length <= 512)
1029 var->xres_virtual = 512 * 8 / bpp;
1030 else if (line_length <= 1024)
1031 var->xres_virtual = 1024 * 8 / bpp;
1032 else if (line_length <= 2048)
1033 var->xres_virtual = 2048 * 8 / bpp;
1034 else if (line_length <= 4096)
1035 var->xres_virtual = 4096 * 8 / bpp;
1036 else if (line_length <= 8192)
1037 var->xres_virtual = 8192 * 8 / bpp;
1041 line_length = var->xres_virtual * bpp / 8;
1044 /* datasheet specifies how to set panning only up to 4 MB */
1045 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
1046 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
1048 if (line_length * var->yres_virtual > info->fix.smem_len)
1053 var->red.offset = 0;
1054 var->red.length = 8;
1055 var->green = var->red;
1056 var->blue = var->red;
1059 var->red.offset = 11;
1060 var->green.offset = 5;
1061 var->blue.offset = 0;
1062 var->red.length = 5;
1063 var->green.length = 6;
1064 var->blue.length = 5;
1067 var->red.offset = 16;
1068 var->green.offset = 8;
1069 var->blue.offset = 0;
1070 var->red.length = 8;
1071 var->green.length = 8;
1072 var->blue.length = 8;
1078 if (is_xp(par->chip_id))
1081 switch (par->chip_id) {
1083 ramdac = (bpp >= 16) ? 45000 : 90000;
1097 /* The clock is doubled for 32 bpp */
1101 if (PICOS2KHZ(var->pixclock) > ramdac)
1110 /* Pan the display */
1111 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1112 struct fb_info *info)
1114 struct tridentfb_par *par = info->par;
1115 unsigned int offset;
1118 offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
1119 * info->var.bits_per_pixel / 32;
1120 set_screen_start(par, offset);
1125 static inline void shadowmode_on(struct tridentfb_par *par)
1127 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1130 static inline void shadowmode_off(struct tridentfb_par *par)
1132 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1135 /* Set the hardware to the requested video mode */
1136 static int tridentfb_set_par(struct fb_info *info)
1138 struct tridentfb_par *par = info->par;
1139 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1140 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1141 struct fb_var_screeninfo *var = &info->var;
1142 int bpp = var->bits_per_pixel;
1147 hdispend = var->xres / 8 - 1;
1148 hsyncstart = (var->xres + var->right_margin) / 8;
1149 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1150 htotal = (var->xres + var->left_margin + var->right_margin +
1151 var->hsync_len) / 8 - 5;
1152 hblankstart = hdispend + 1;
1153 hblankend = htotal + 3;
1155 vdispend = var->yres - 1;
1156 vsyncstart = var->yres + var->lower_margin;
1157 vsyncend = vsyncstart + var->vsync_len;
1158 vtotal = var->upper_margin + vsyncend - 2;
1159 vblankstart = vdispend + 1;
1162 if (info->var.vmode & FB_VMODE_INTERLACED) {
1173 write3CE(par, CyberControl, 8);
1175 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1177 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1180 if (par->flatpanel && var->xres < nativex) {
1182 * on flat panels with native size larger
1183 * than requested resolution decide whether
1184 * we stretch or center
1186 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1193 screen_stretch(par);
1196 t_outb(par, tmp, VGA_MIS_W);
1197 write3CE(par, CyberControl, 8);
1200 /* vertical timing values */
1201 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1202 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1203 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1204 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1205 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1206 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1208 /* horizontal timing values */
1209 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1210 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1211 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1212 write3X4(par, VGA_CRTC_H_SYNC_END,
1213 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1214 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1215 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1217 /* higher bits of vertical timing values */
1219 if (vtotal & 0x100) tmp |= 0x01;
1220 if (vdispend & 0x100) tmp |= 0x02;
1221 if (vsyncstart & 0x100) tmp |= 0x04;
1222 if (vblankstart & 0x100) tmp |= 0x08;
1224 if (vtotal & 0x200) tmp |= 0x20;
1225 if (vdispend & 0x200) tmp |= 0x40;
1226 if (vsyncstart & 0x200) tmp |= 0x80;
1227 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1229 tmp = read3X4(par, CRTHiOrd) & 0x07;
1230 tmp |= 0x08; /* line compare bit 10 */
1231 if (vtotal & 0x400) tmp |= 0x80;
1232 if (vblankstart & 0x400) tmp |= 0x40;
1233 if (vsyncstart & 0x400) tmp |= 0x20;
1234 if (vdispend & 0x400) tmp |= 0x10;
1235 write3X4(par, CRTHiOrd, tmp);
1237 tmp = (htotal >> 8) & 0x01;
1238 tmp |= (hdispend >> 7) & 0x02;
1239 tmp |= (hsyncstart >> 5) & 0x08;
1240 tmp |= (hblankstart >> 4) & 0x10;
1241 write3X4(par, HorizOverflow, tmp);
1244 if (vblankstart & 0x200) tmp |= 0x20;
1245 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1246 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1248 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1249 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1250 write3X4(par, VGA_CRTC_MODE, 0xC3);
1252 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1254 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1255 /* enable access extended memory */
1256 write3X4(par, CRTCModuleTest, tmp);
1257 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1258 if (info->var.vmode & FB_VMODE_INTERLACED)
1260 write3CE(par, MiscIntContReg, tmp);
1262 /* enable GE for text acceleration */
1263 write3X4(par, GraphEngReg, 0x80);
1280 write3X4(par, PixelBusReg, tmp);
1282 tmp = read3X4(par, DRAMControl);
1283 if (!is_oldprotect(par->chip_id))
1285 if (iscyber(par->chip_id))
1287 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1289 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1290 if (!is_xp(par->chip_id))
1291 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1292 /* MMIO & PCI read and write burst enable */
1293 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1294 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1296 vga_mm_wseq(par->io_virt, 0, 3);
1297 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1298 /* enable 4 maps because needed in chain4 mode */
1299 vga_mm_wseq(par->io_virt, 2, 0x0F);
1300 vga_mm_wseq(par->io_virt, 3, 0);
1301 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1303 /* convert from picoseconds to kHz */
1304 vclk = PICOS2KHZ(info->var.pixclock);
1306 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1307 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1308 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1312 set_vclk(par, vclk);
1313 write3CE(par, MiscExtFunc, tmp | 0x12);
1314 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1315 write3CE(par, 0x6, 0x05); /* graphics mode */
1316 write3CE(par, 0x7, 0x0F); /* planes? */
1318 /* graphics mode and support 256 color modes */
1319 writeAttr(par, 0x10, 0x41);
1320 writeAttr(par, 0x12, 0x0F); /* planes */
1321 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1324 for (tmp = 0; tmp < 0x10; tmp++)
1325 writeAttr(par, tmp, tmp);
1326 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1327 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1342 t_inb(par, VGA_PEL_IW);
1343 t_inb(par, VGA_PEL_MSK);
1344 t_inb(par, VGA_PEL_MSK);
1345 t_inb(par, VGA_PEL_MSK);
1346 t_inb(par, VGA_PEL_MSK);
1347 t_outb(par, tmp, VGA_PEL_MSK);
1348 t_inb(par, VGA_PEL_IW);
1351 set_number_of_lines(par, info->var.yres);
1352 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1353 set_lwidth(par, info->fix.line_length / 8);
1355 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1356 par->init_accel(par, info->var.xres_virtual, bpp);
1358 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1359 info->cmap.len = (bpp == 8) ? 256 : 16;
1364 /* Set one color register */
1365 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1366 unsigned blue, unsigned transp,
1367 struct fb_info *info)
1369 int bpp = info->var.bits_per_pixel;
1370 struct tridentfb_par *par = info->par;
1372 if (regno >= info->cmap.len)
1376 t_outb(par, 0xFF, VGA_PEL_MSK);
1377 t_outb(par, regno, VGA_PEL_IW);
1379 t_outb(par, red >> 10, VGA_PEL_D);
1380 t_outb(par, green >> 10, VGA_PEL_D);
1381 t_outb(par, blue >> 10, VGA_PEL_D);
1383 } else if (regno < 16) {
1384 if (bpp == 16) { /* RGB 565 */
1387 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1388 ((blue & 0xF800) >> 11);
1390 ((u32 *)(info->pseudo_palette))[regno] = col;
1391 } else if (bpp == 32) /* ARGB 8888 */
1392 ((u32 *)info->pseudo_palette)[regno] =
1393 ((transp & 0xFF00) << 16) |
1394 ((red & 0xFF00) << 8) |
1395 ((green & 0xFF00)) |
1396 ((blue & 0xFF00) >> 8);
1402 /* Try blanking the screen. For flat panels it does nothing */
1403 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1405 unsigned char PMCont, DPMSCont;
1406 struct tridentfb_par *par = info->par;
1411 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1412 PMCont = t_inb(par, 0x83C6) & 0xFC;
1413 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1414 switch (blank_mode) {
1415 case FB_BLANK_UNBLANK:
1416 /* Screen: On, HSync: On, VSync: On */
1417 case FB_BLANK_NORMAL:
1418 /* Screen: Off, HSync: On, VSync: On */
1422 case FB_BLANK_HSYNC_SUSPEND:
1423 /* Screen: Off, HSync: Off, VSync: On */
1427 case FB_BLANK_VSYNC_SUSPEND:
1428 /* Screen: Off, HSync: On, VSync: Off */
1432 case FB_BLANK_POWERDOWN:
1433 /* Screen: Off, HSync: Off, VSync: Off */
1439 write3CE(par, PowerStatus, DPMSCont);
1440 t_outb(par, 4, 0x83C8);
1441 t_outb(par, PMCont, 0x83C6);
1445 /* let fbcon do a softblank for us */
1446 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1449 static const struct fb_ops tridentfb_ops = {
1450 .owner = THIS_MODULE,
1451 .fb_setcolreg = tridentfb_setcolreg,
1452 .fb_pan_display = tridentfb_pan_display,
1453 .fb_blank = tridentfb_blank,
1454 .fb_check_var = tridentfb_check_var,
1455 .fb_set_par = tridentfb_set_par,
1456 .fb_fillrect = tridentfb_fillrect,
1457 .fb_copyarea = tridentfb_copyarea,
1458 .fb_imageblit = tridentfb_imageblit,
1459 .fb_sync = tridentfb_sync,
1462 static int trident_pci_probe(struct pci_dev *dev,
1463 const struct pci_device_id *id)
1466 unsigned char revision;
1467 struct fb_info *info;
1468 struct tridentfb_par *default_par;
1473 err = pci_enable_device(dev);
1477 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1480 default_par = info->par;
1482 chip_id = id->device;
1484 /* If PCI id is 0x9660 then further detect chip type */
1486 if (chip_id == TGUI9660) {
1487 revision = vga_io_rseq(RevisionID);
1491 chip_id = PROVIDIA9685;
1495 chip_id = CYBER9397;
1498 chip_id = CYBER9397DVD;
1507 chip_id = CYBER9385;
1510 chip_id = CYBER9382;
1513 chip_id = CYBER9388;
1520 chip3D = is3Dchip(chip_id);
1522 if (is_xp(chip_id)) {
1523 default_par->init_accel = xp_init_accel;
1524 default_par->wait_engine = xp_wait_engine;
1525 default_par->fill_rect = xp_fill_rect;
1526 default_par->copy_rect = xp_copy_rect;
1527 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1528 } else if (is_blade(chip_id)) {
1529 default_par->init_accel = blade_init_accel;
1530 default_par->wait_engine = blade_wait_engine;
1531 default_par->fill_rect = blade_fill_rect;
1532 default_par->copy_rect = blade_copy_rect;
1533 default_par->image_blit = blade_image_blit;
1534 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1535 } else if (chip3D) { /* 3DImage family left */
1536 default_par->init_accel = image_init_accel;
1537 default_par->wait_engine = image_wait_engine;
1538 default_par->fill_rect = image_fill_rect;
1539 default_par->copy_rect = image_copy_rect;
1540 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1541 } else { /* TGUI 9440/96XX family */
1542 default_par->init_accel = tgui_init_accel;
1543 default_par->wait_engine = xp_wait_engine;
1544 default_par->fill_rect = tgui_fill_rect;
1545 default_par->copy_rect = tgui_copy_rect;
1546 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1549 default_par->chip_id = chip_id;
1551 /* setup MMIO region */
1552 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1553 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1555 if (!request_mem_region(tridentfb_fix.mmio_start,
1556 tridentfb_fix.mmio_len, "tridentfb")) {
1557 debug("request_region failed!\n");
1558 framebuffer_release(info);
1562 default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
1563 tridentfb_fix.mmio_len);
1565 if (!default_par->io_virt) {
1566 debug("ioremap failed\n");
1571 enable_mmio(default_par);
1573 /* setup framebuffer memory */
1574 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1575 tridentfb_fix.smem_len = get_memsize(default_par);
1577 if (!request_mem_region(tridentfb_fix.smem_start,
1578 tridentfb_fix.smem_len, "tridentfb")) {
1579 debug("request_mem_region failed!\n");
1580 disable_mmio(info->par);
1585 info->screen_base = ioremap(tridentfb_fix.smem_start,
1586 tridentfb_fix.smem_len);
1588 if (!info->screen_base) {
1589 debug("ioremap failed\n");
1594 default_par->flatpanel = is_flatpanel(default_par);
1596 if (default_par->flatpanel)
1597 nativex = get_nativex(default_par);
1599 info->fix = tridentfb_fix;
1600 info->fbops = &tridentfb_ops;
1601 info->pseudo_palette = default_par->pseudo_pal;
1603 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1604 if (!noaccel && default_par->init_accel) {
1605 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1606 info->flags |= FBINFO_HWACCEL_COPYAREA;
1607 info->flags |= FBINFO_HWACCEL_FILLRECT;
1609 info->flags |= FBINFO_HWACCEL_DISABLED;
1611 if (is_blade(chip_id) && chip_id != BLADE3D)
1612 info->flags |= FBINFO_READS_FAST;
1614 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1615 if (!info->pixmap.addr) {
1620 info->pixmap.size = 4096;
1621 info->pixmap.buf_align = 4;
1622 info->pixmap.scan_align = 1;
1623 info->pixmap.access_align = 32;
1624 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1625 info->var.bits_per_pixel = 8;
1627 if (default_par->image_blit) {
1628 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1629 info->pixmap.scan_align = 4;
1633 printk(KERN_DEBUG "disabling acceleration\n");
1634 info->flags |= FBINFO_HWACCEL_DISABLED;
1635 info->pixmap.scan_align = 1;
1638 if (tridentfb_setup_ddc_bus(info) == 0) {
1639 u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
1641 default_par->ddc_registered = true;
1643 fb_edid_to_monspecs(edid, &info->monspecs);
1645 if (!info->monspecs.modedb)
1646 dev_err(info->device, "error getting mode database\n");
1648 const struct fb_videomode *m;
1650 fb_videomode_to_modelist(info->monspecs.modedb,
1651 info->monspecs.modedb_len,
1653 m = fb_find_best_display(&info->monspecs,
1656 fb_videomode_to_var(&info->var, m);
1657 /* fill all other info->var's fields */
1658 if (tridentfb_check_var(&info->var,
1666 if (!mode_option && !found)
1667 mode_option = "640x480-8@60";
1669 /* Prepare startup mode */
1671 err = fb_find_mode(&info->var, info, mode_option,
1672 info->monspecs.modedb,
1673 info->monspecs.modedb_len,
1674 NULL, info->var.bits_per_pixel);
1675 if (!err || err == 4) {
1677 dev_err(info->device, "mode %s not found\n",
1679 fb_destroy_modedb(info->monspecs.modedb);
1680 info->monspecs.modedb = NULL;
1685 fb_destroy_modedb(info->monspecs.modedb);
1686 info->monspecs.modedb = NULL;
1688 err = fb_alloc_cmap(&info->cmap, 256, 0);
1692 info->var.activate |= FB_ACTIVATE_NOW;
1693 info->device = &dev->dev;
1694 if (register_framebuffer(info) < 0) {
1695 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1696 fb_dealloc_cmap(&info->cmap);
1700 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1701 info->node, info->fix.id, info->var.xres,
1702 info->var.yres, info->var.bits_per_pixel);
1704 pci_set_drvdata(dev, info);
1708 if (default_par->ddc_registered)
1709 i2c_del_adapter(&default_par->ddc_adapter);
1710 kfree(info->pixmap.addr);
1711 if (info->screen_base)
1712 iounmap(info->screen_base);
1713 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1714 disable_mmio(info->par);
1716 if (default_par->io_virt)
1717 iounmap(default_par->io_virt);
1718 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1719 framebuffer_release(info);
1723 static void trident_pci_remove(struct pci_dev *dev)
1725 struct fb_info *info = pci_get_drvdata(dev);
1726 struct tridentfb_par *par = info->par;
1728 unregister_framebuffer(info);
1729 if (par->ddc_registered)
1730 i2c_del_adapter(&par->ddc_adapter);
1731 iounmap(par->io_virt);
1732 iounmap(info->screen_base);
1733 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1734 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1735 kfree(info->pixmap.addr);
1736 fb_dealloc_cmap(&info->cmap);
1737 framebuffer_release(info);
1740 /* List of boards that we are trying to support */
1741 static const struct pci_device_id trident_devices[] = {
1742 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1743 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1744 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1745 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1746 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1747 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1748 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1749 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1750 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1751 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1752 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1753 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1754 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1755 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1756 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1757 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1758 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1759 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1760 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1761 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1762 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1766 MODULE_DEVICE_TABLE(pci, trident_devices);
1768 static struct pci_driver tridentfb_pci_driver = {
1769 .name = "tridentfb",
1770 .id_table = trident_devices,
1771 .probe = trident_pci_probe,
1772 .remove = trident_pci_remove,
1776 * Parse user specified options (`video=trident:')
1778 * video=trident:800x600,bpp=16,noaccel
1781 static int __init tridentfb_setup(char *options)
1784 if (!options || !*options)
1786 while ((opt = strsep(&options, ",")) != NULL) {
1789 if (!strncmp(opt, "noaccel", 7))
1791 else if (!strncmp(opt, "fp", 2))
1793 else if (!strncmp(opt, "crt", 3))
1795 else if (!strncmp(opt, "bpp=", 4))
1796 bpp = simple_strtoul(opt + 4, NULL, 0);
1797 else if (!strncmp(opt, "center", 6))
1799 else if (!strncmp(opt, "stretch", 7))
1801 else if (!strncmp(opt, "memsize=", 8))
1802 memsize = simple_strtoul(opt + 8, NULL, 0);
1803 else if (!strncmp(opt, "memdiff=", 8))
1804 memdiff = simple_strtoul(opt + 8, NULL, 0);
1805 else if (!strncmp(opt, "nativex=", 8))
1806 nativex = simple_strtoul(opt + 8, NULL, 0);
1814 static int __init tridentfb_init(void)
1817 char *option = NULL;
1819 if (fb_get_options("tridentfb", &option))
1821 tridentfb_setup(option);
1823 return pci_register_driver(&tridentfb_pci_driver);
1826 static void __exit tridentfb_exit(void)
1828 pci_unregister_driver(&tridentfb_pci_driver);
1831 module_init(tridentfb_init);
1832 module_exit(tridentfb_exit);
1834 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1835 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1836 MODULE_LICENSE("GPL");
1837 MODULE_ALIAS("cyblafb");