2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
43 #include <linux/bitrev.h>
44 #ifdef CONFIG_PMAC_BACKLIGHT
45 #include <asm/machdep.h>
46 #include <asm/backlight.h>
52 /* version number of this driver */
53 #define RIVAFB_VERSION "0.9.5b"
55 /* ------------------------------------------------------------------------- *
57 * various helpful macros and constants
59 * ------------------------------------------------------------------------- */
60 #ifdef CONFIG_FB_RIVA_DEBUG
61 #define NVTRACE printk
63 #define NVTRACE if(0) printk
66 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
67 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
69 #ifdef CONFIG_FB_RIVA_DEBUG
70 #define assert(expr) \
72 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
73 #expr,__FILE__,__func__,__LINE__); \
80 #define PFX "rivafb: "
82 /* macro that allows you to set overflow bits */
83 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
84 #define SetBit(n) (1<<(n))
85 #define Set8Bits(value) ((value)&0xff)
87 /* HW cursor parameters */
90 /* ------------------------------------------------------------------------- *
94 * ------------------------------------------------------------------------- */
96 static int rivafb_blank(int blank, struct fb_info *info);
98 /* ------------------------------------------------------------------------- *
100 * card identification
102 * ------------------------------------------------------------------------- */
104 static struct pci_device_id rivafb_pci_tbl[] = {
105 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
107 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
109 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
111 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
113 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
115 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 // NF2/IGP version, GeForce 4 MX, NV18
146 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
156 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { 0, } /* terminate list */
192 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
194 /* ------------------------------------------------------------------------- *
198 * ------------------------------------------------------------------------- */
200 /* command line data, set in rivafb_setup() */
201 static int flatpanel = -1; /* Autodetect later */
202 static int forceCRTC = -1;
203 static bool noaccel = 0;
204 static bool nomtrr = 0;
205 #ifdef CONFIG_PMAC_BACKLIGHT
206 static int backlight = 1;
208 static int backlight = 0;
211 static char *mode_option = NULL;
212 static bool strictmode = 0;
214 static struct fb_fix_screeninfo rivafb_fix = {
215 .type = FB_TYPE_PACKED_PIXELS,
220 static struct fb_var_screeninfo rivafb_default_var = {
230 .activate = FB_ACTIVATE_NOW,
240 .vmode = FB_VMODE_NONINTERLACED
244 static const struct riva_regs reg_template = {
245 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
246 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
247 0x41, 0x01, 0x0F, 0x00, 0x00},
248 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
249 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
251 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
253 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
260 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
267 #ifdef CONFIG_FB_RIVA_BACKLIGHT
268 /* We do not have any information about which values are allowed, thus
269 * we used safe values.
271 #define MIN_LEVEL 0x158
272 #define MAX_LEVEL 0x534
273 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
275 static int riva_bl_get_level_brightness(struct riva_par *par,
278 struct fb_info *info = pci_get_drvdata(par->pdev);
281 /* Get and convert the value */
282 /* No locking on bl_curve since accessing a single value */
283 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
287 else if (nlevel < MIN_LEVEL)
289 else if (nlevel > MAX_LEVEL)
295 static int riva_bl_update_status(struct backlight_device *bd)
297 struct riva_par *par = bl_get_data(bd);
298 U032 tmp_pcrt, tmp_pmc;
301 if (bd->props.power != FB_BLANK_UNBLANK ||
302 bd->props.fb_blank != FB_BLANK_UNBLANK)
305 level = bd->props.brightness;
307 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
308 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
311 tmp_pmc |= (1 << 31); /* backlight bit */
312 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
314 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
315 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
320 static const struct backlight_ops riva_bl_ops = {
321 .update_status = riva_bl_update_status,
324 static void riva_bl_init(struct riva_par *par)
326 struct backlight_properties props;
327 struct fb_info *info = pci_get_drvdata(par->pdev);
328 struct backlight_device *bd;
334 #ifdef CONFIG_PMAC_BACKLIGHT
335 if (!machine_is(powermac) ||
336 !pmac_has_backlight_type("mnca"))
340 snprintf(name, sizeof(name), "rivabl%d", info->node);
342 memset(&props, 0, sizeof(struct backlight_properties));
343 props.type = BACKLIGHT_RAW;
344 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
345 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
349 printk(KERN_WARNING "riva: Backlight registration failed\n");
354 fb_bl_default_curve(info, 0,
355 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
358 bd->props.brightness = bd->props.max_brightness;
359 bd->props.power = FB_BLANK_UNBLANK;
360 backlight_update_status(bd);
362 printk("riva: Backlight initialized (%s)\n", name);
370 static void riva_bl_exit(struct fb_info *info)
372 struct backlight_device *bd = info->bl_dev;
374 backlight_device_unregister(bd);
375 printk("riva: Backlight unloaded\n");
378 static inline void riva_bl_init(struct riva_par *par) {}
379 static inline void riva_bl_exit(struct fb_info *info) {}
380 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
382 /* ------------------------------------------------------------------------- *
386 * ------------------------------------------------------------------------- */
388 static inline void CRTCout(struct riva_par *par, unsigned char index,
391 VGA_WR08(par->riva.PCIO, 0x3d4, index);
392 VGA_WR08(par->riva.PCIO, 0x3d5, val);
395 static inline unsigned char CRTCin(struct riva_par *par,
398 VGA_WR08(par->riva.PCIO, 0x3d4, index);
399 return (VGA_RD08(par->riva.PCIO, 0x3d5));
402 static inline void GRAout(struct riva_par *par, unsigned char index,
405 VGA_WR08(par->riva.PVIO, 0x3ce, index);
406 VGA_WR08(par->riva.PVIO, 0x3cf, val);
409 static inline unsigned char GRAin(struct riva_par *par,
412 VGA_WR08(par->riva.PVIO, 0x3ce, index);
413 return (VGA_RD08(par->riva.PVIO, 0x3cf));
416 static inline void SEQout(struct riva_par *par, unsigned char index,
419 VGA_WR08(par->riva.PVIO, 0x3c4, index);
420 VGA_WR08(par->riva.PVIO, 0x3c5, val);
423 static inline unsigned char SEQin(struct riva_par *par,
426 VGA_WR08(par->riva.PVIO, 0x3c4, index);
427 return (VGA_RD08(par->riva.PVIO, 0x3c5));
430 static inline void ATTRout(struct riva_par *par, unsigned char index,
433 VGA_WR08(par->riva.PCIO, 0x3c0, index);
434 VGA_WR08(par->riva.PCIO, 0x3c0, val);
437 static inline unsigned char ATTRin(struct riva_par *par,
440 VGA_WR08(par->riva.PCIO, 0x3c0, index);
441 return (VGA_RD08(par->riva.PCIO, 0x3c1));
444 static inline void MISCout(struct riva_par *par, unsigned char val)
446 VGA_WR08(par->riva.PVIO, 0x3c2, val);
449 static inline unsigned char MISCin(struct riva_par *par)
451 return (VGA_RD08(par->riva.PVIO, 0x3cc));
454 static inline void reverse_order(u32 *l)
457 a[0] = bitrev8(a[0]);
458 a[1] = bitrev8(a[1]);
459 a[2] = bitrev8(a[2]);
460 a[3] = bitrev8(a[3]);
463 /* ------------------------------------------------------------------------- *
467 * ------------------------------------------------------------------------- */
470 * rivafb_load_cursor_image - load cursor image to hardware
471 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
472 * @par: pointer to private data
473 * @w: width of cursor image in pixels
474 * @h: height of cursor image in scanlines
475 * @bg: background color (ARGB1555) - alpha bit determines opacity
476 * @fg: foreground color (ARGB1555)
479 * Loads cursor image based on a monochrome source and mask bitmap. The
480 * image bits determines the color of the pixel, 0 for background, 1 for
481 * foreground. Only the affected region (as determined by @w and @h
482 * parameters) will be updated.
487 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
488 u16 bg, u16 fg, u32 w, u32 h)
492 u32 *data = (u32 *)data8;
493 bg = le16_to_cpu(bg);
494 fg = le16_to_cpu(fg);
498 for (i = 0; i < h; i++) {
502 for (j = 0; j < w/2; j++) {
504 #if defined (__BIG_ENDIAN)
505 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
507 tmp |= (b & (1 << 31)) ? fg : bg;
510 tmp = (b & 1) ? fg : bg;
512 tmp |= (b & 1) ? fg << 16 : bg << 16;
515 writel(tmp, &par->riva.CURSOR[k++]);
517 k += (MAX_CURS - w)/2;
521 /* ------------------------------------------------------------------------- *
523 * general utility functions
525 * ------------------------------------------------------------------------- */
528 * riva_wclut - set CLUT entry
529 * @chip: pointer to RIVA_HW_INST object
530 * @regnum: register number
531 * @red: red component
532 * @green: green component
533 * @blue: blue component
536 * Sets color register @regnum.
541 static void riva_wclut(RIVA_HW_INST *chip,
542 unsigned char regnum, unsigned char red,
543 unsigned char green, unsigned char blue)
545 VGA_WR08(chip->PDIO, 0x3c8, regnum);
546 VGA_WR08(chip->PDIO, 0x3c9, red);
547 VGA_WR08(chip->PDIO, 0x3c9, green);
548 VGA_WR08(chip->PDIO, 0x3c9, blue);
552 * riva_rclut - read fromCLUT register
553 * @chip: pointer to RIVA_HW_INST object
554 * @regnum: register number
555 * @red: red component
556 * @green: green component
557 * @blue: blue component
560 * Reads red, green, and blue from color register @regnum.
565 static void riva_rclut(RIVA_HW_INST *chip,
566 unsigned char regnum, unsigned char *red,
567 unsigned char *green, unsigned char *blue)
570 VGA_WR08(chip->PDIO, 0x3c7, regnum);
571 *red = VGA_RD08(chip->PDIO, 0x3c9);
572 *green = VGA_RD08(chip->PDIO, 0x3c9);
573 *blue = VGA_RD08(chip->PDIO, 0x3c9);
577 * riva_save_state - saves current chip state
578 * @par: pointer to riva_par object containing info for current riva board
579 * @regs: pointer to riva_regs object
582 * Saves current chip state to @regs.
588 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
593 par->riva.LockUnlock(&par->riva, 0);
595 par->riva.UnloadStateExt(&par->riva, ®s->ext);
597 regs->misc_output = MISCin(par);
599 for (i = 0; i < NUM_CRT_REGS; i++)
600 regs->crtc[i] = CRTCin(par, i);
602 for (i = 0; i < NUM_ATC_REGS; i++)
603 regs->attr[i] = ATTRin(par, i);
605 for (i = 0; i < NUM_GRC_REGS; i++)
606 regs->gra[i] = GRAin(par, i);
608 for (i = 0; i < NUM_SEQ_REGS; i++)
609 regs->seq[i] = SEQin(par, i);
614 * riva_load_state - loads current chip state
615 * @par: pointer to riva_par object containing info for current riva board
616 * @regs: pointer to riva_regs object
619 * Loads chip state from @regs.
622 * riva_load_video_mode()
627 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
629 RIVA_HW_STATE *state = ®s->ext;
633 CRTCout(par, 0x11, 0x00);
635 par->riva.LockUnlock(&par->riva, 0);
637 par->riva.LoadStateExt(&par->riva, state);
639 MISCout(par, regs->misc_output);
641 for (i = 0; i < NUM_CRT_REGS; i++) {
647 CRTCout(par, i, regs->crtc[i]);
651 for (i = 0; i < NUM_ATC_REGS; i++)
652 ATTRout(par, i, regs->attr[i]);
654 for (i = 0; i < NUM_GRC_REGS; i++)
655 GRAout(par, i, regs->gra[i]);
657 for (i = 0; i < NUM_SEQ_REGS; i++)
658 SEQout(par, i, regs->seq[i]);
663 * riva_load_video_mode - calculate timings
664 * @info: pointer to fb_info object containing info for current riva board
667 * Calculate some timings and then send em off to riva_load_state().
672 static int riva_load_video_mode(struct fb_info *info)
674 int bpp, width, hDisplaySize, hDisplay, hStart,
675 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
676 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
678 struct riva_par *par = info->par;
679 struct riva_regs newmode;
682 /* time to calculate */
683 rivafb_blank(FB_BLANK_NORMAL, info);
685 bpp = info->var.bits_per_pixel;
686 if (bpp == 16 && info->var.green.length == 5)
688 width = info->var.xres_virtual;
689 hDisplaySize = info->var.xres;
690 hDisplay = (hDisplaySize / 8) - 1;
691 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
692 hEnd = (hDisplaySize + info->var.right_margin +
693 info->var.hsync_len) / 8 - 1;
694 hTotal = (hDisplaySize + info->var.right_margin +
695 info->var.hsync_len + info->var.left_margin) / 8 - 5;
696 hBlankStart = hDisplay;
697 hBlankEnd = hTotal + 4;
699 height = info->var.yres_virtual;
700 vDisplay = info->var.yres - 1;
701 vStart = info->var.yres + info->var.lower_margin - 1;
702 vEnd = info->var.yres + info->var.lower_margin +
703 info->var.vsync_len - 1;
704 vTotal = info->var.yres + info->var.lower_margin +
705 info->var.vsync_len + info->var.upper_margin + 2;
706 vBlankStart = vDisplay;
707 vBlankEnd = vTotal + 1;
708 dotClock = 1000000000 / info->var.pixclock;
710 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
712 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
715 if (par->FlatPanel) {
718 vBlankStart = vStart;
721 hBlankEnd = hTotal + 4;
724 newmode.crtc[0x0] = Set8Bits (hTotal);
725 newmode.crtc[0x1] = Set8Bits (hDisplay);
726 newmode.crtc[0x2] = Set8Bits (hBlankStart);
727 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
728 newmode.crtc[0x4] = Set8Bits (hStart);
729 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
730 | SetBitField (hEnd, 4: 0, 4:0);
731 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
732 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
733 | SetBitField (vDisplay, 8: 8, 1:1)
734 | SetBitField (vStart, 8: 8, 2:2)
735 | SetBitField (vBlankStart, 8: 8, 3:3)
737 | SetBitField (vTotal, 9: 9, 5:5)
738 | SetBitField (vDisplay, 9: 9, 6:6)
739 | SetBitField (vStart, 9: 9, 7:7);
740 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
742 newmode.crtc[0x10] = Set8Bits (vStart);
743 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
745 newmode.crtc[0x12] = Set8Bits (vDisplay);
746 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
747 newmode.crtc[0x15] = Set8Bits (vBlankStart);
748 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
750 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
751 | SetBitField(vBlankStart,10:10,3:3)
752 | SetBitField(vStart,10:10,2:2)
753 | SetBitField(vDisplay,10:10,1:1)
754 | SetBitField(vTotal,10:10,0:0);
755 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
756 | SetBitField(hDisplay,8:8,1:1)
757 | SetBitField(hBlankStart,8:8,2:2)
758 | SetBitField(hStart,8:8,3:3);
759 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
760 | SetBitField(vDisplay,11:11,2:2)
761 | SetBitField(vStart,11:11,4:4)
762 | SetBitField(vBlankStart,11:11,6:6);
764 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
765 int tmp = (hTotal >> 1) & ~1;
766 newmode.ext.interlace = Set8Bits(tmp);
767 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
769 newmode.ext.interlace = 0xff; /* interlace off */
771 if (par->riva.Architecture >= NV_ARCH_10)
772 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
774 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
775 newmode.misc_output &= ~0x40;
777 newmode.misc_output |= 0x40;
778 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
779 newmode.misc_output &= ~0x80;
781 newmode.misc_output |= 0x80;
783 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
784 hDisplaySize, height, dotClock);
788 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
790 if (par->FlatPanel == 1) {
791 newmode.ext.pixel |= (1 << 7);
792 newmode.ext.scale |= (1 << 8);
794 if (par->SecondCRTC) {
795 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
797 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
799 newmode.ext.crtcOwner = 3;
800 newmode.ext.pllsel |= 0x20000800;
801 newmode.ext.vpll2 = newmode.ext.vpll;
802 } else if (par->riva.twoHeads) {
803 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
805 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
807 newmode.ext.crtcOwner = 0;
808 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
810 if (par->FlatPanel == 1) {
811 newmode.ext.pixel |= (1 << 7);
812 newmode.ext.scale |= (1 << 8);
814 newmode.ext.cursorConfig = 0x02000100;
815 par->current_state = newmode;
816 riva_load_state(par, &par->current_state);
817 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
820 rivafb_blank(FB_BLANK_UNBLANK, info);
826 static void riva_update_var(struct fb_var_screeninfo *var,
827 const struct fb_videomode *modedb)
830 var->xres = var->xres_virtual = modedb->xres;
831 var->yres = modedb->yres;
832 if (var->yres_virtual < var->yres)
833 var->yres_virtual = var->yres;
834 var->xoffset = var->yoffset = 0;
835 var->pixclock = modedb->pixclock;
836 var->left_margin = modedb->left_margin;
837 var->right_margin = modedb->right_margin;
838 var->upper_margin = modedb->upper_margin;
839 var->lower_margin = modedb->lower_margin;
840 var->hsync_len = modedb->hsync_len;
841 var->vsync_len = modedb->vsync_len;
842 var->sync = modedb->sync;
843 var->vmode = modedb->vmode;
848 * rivafb_do_maximize -
849 * @info: pointer to fb_info object containing info for current riva board
858 * -EINVAL on failure, 0 on success
864 static int rivafb_do_maximize(struct fb_info *info,
865 struct fb_var_screeninfo *var,
881 /* use highest possible virtual resolution */
882 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
883 printk(KERN_WARNING PFX
884 "using maximum available virtual resolution\n");
885 for (i = 0; modes[i].xres != -1; i++) {
886 if (modes[i].xres * nom / den * modes[i].yres <
890 if (modes[i].xres == -1) {
892 "could not find a virtual resolution that fits into video memory!!\n");
893 NVTRACE("EXIT - EINVAL error\n");
896 var->xres_virtual = modes[i].xres;
897 var->yres_virtual = modes[i].yres;
900 "virtual resolution set to maximum of %dx%d\n",
901 var->xres_virtual, var->yres_virtual);
902 } else if (var->xres_virtual == -1) {
903 var->xres_virtual = (info->fix.smem_len * den /
904 (nom * var->yres_virtual)) & ~15;
905 printk(KERN_WARNING PFX
906 "setting virtual X resolution to %d\n", var->xres_virtual);
907 } else if (var->yres_virtual == -1) {
908 var->xres_virtual = (var->xres_virtual + 15) & ~15;
909 var->yres_virtual = info->fix.smem_len * den /
910 (nom * var->xres_virtual);
911 printk(KERN_WARNING PFX
912 "setting virtual Y resolution to %d\n", var->yres_virtual);
914 var->xres_virtual = (var->xres_virtual + 15) & ~15;
915 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
917 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
918 var->xres, var->yres, var->bits_per_pixel);
919 NVTRACE("EXIT - EINVAL error\n");
924 if (var->xres_virtual * nom / den >= 8192) {
925 printk(KERN_WARNING PFX
926 "virtual X resolution (%d) is too high, lowering to %d\n",
927 var->xres_virtual, 8192 * den / nom - 16);
928 var->xres_virtual = 8192 * den / nom - 16;
931 if (var->xres_virtual < var->xres) {
933 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
937 if (var->yres_virtual < var->yres) {
939 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
942 if (var->yres_virtual > 0x7fff/nom)
943 var->yres_virtual = 0x7fff/nom;
944 if (var->xres_virtual > 0x7fff/nom)
945 var->xres_virtual = 0x7fff/nom;
951 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
953 RIVA_FIFO_FREE(par->riva, Patt, 4);
954 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
955 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
956 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
957 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
960 /* acceleration routines */
961 static inline void wait_for_idle(struct riva_par *par)
963 while (par->riva.Busy(&par->riva));
967 * Set ROP. Translate X rop into ROP3. Internal routine.
970 riva_set_rop_solid(struct riva_par *par, int rop)
972 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
973 RIVA_FIFO_FREE(par->riva, Rop, 1);
974 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
978 static void riva_setup_accel(struct fb_info *info)
980 struct riva_par *par = info->par;
982 RIVA_FIFO_FREE(par->riva, Clip, 2);
983 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
984 NV_WR32(&par->riva.Clip->WidthHeight, 0,
985 (info->var.xres_virtual & 0xffff) |
986 (info->var.yres_virtual << 16));
987 riva_set_rop_solid(par, 0xcc);
992 * riva_get_cmap_len - query current color map length
993 * @var: standard kernel fb changeable data
996 * Get current color map length.
999 * Length of color map
1002 * rivafb_setcolreg()
1004 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1006 int rc = 256; /* reasonable default */
1008 switch (var->green.length) {
1010 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1013 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1016 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1019 /* should not occur */
1025 /* ------------------------------------------------------------------------- *
1027 * framebuffer operations
1029 * ------------------------------------------------------------------------- */
1031 static int rivafb_open(struct fb_info *info, int user)
1033 struct riva_par *par = info->par;
1036 mutex_lock(&par->open_lock);
1037 if (!par->ref_count) {
1039 memset(&par->state, 0, sizeof(struct vgastate));
1040 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1041 /* save the DAC for Riva128 */
1042 if (par->riva.Architecture == NV_ARCH_03)
1043 par->state.flags |= VGA_SAVE_CMAP;
1044 save_vga(&par->state);
1046 /* vgaHWunlock() + riva unlock (0x7F) */
1047 CRTCout(par, 0x11, 0xFF);
1048 par->riva.LockUnlock(&par->riva, 0);
1050 riva_save_state(par, &par->initial_state);
1053 mutex_unlock(&par->open_lock);
1058 static int rivafb_release(struct fb_info *info, int user)
1060 struct riva_par *par = info->par;
1063 mutex_lock(&par->open_lock);
1064 if (!par->ref_count) {
1065 mutex_unlock(&par->open_lock);
1068 if (par->ref_count == 1) {
1069 par->riva.LockUnlock(&par->riva, 0);
1070 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1071 riva_load_state(par, &par->initial_state);
1073 restore_vga(&par->state);
1075 par->riva.LockUnlock(&par->riva, 1);
1078 mutex_unlock(&par->open_lock);
1083 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1085 const struct fb_videomode *mode;
1086 struct riva_par *par = info->par;
1087 int nom, den; /* translating from pixels->bytes */
1094 switch (var->bits_per_pixel) {
1096 var->red.offset = var->green.offset = var->blue.offset = 0;
1097 var->red.length = var->green.length = var->blue.length = 8;
1098 var->bits_per_pixel = 8;
1102 var->green.length = 5;
1105 var->bits_per_pixel = 16;
1106 /* The Riva128 supports RGB555 only */
1107 if (par->riva.Architecture == NV_ARCH_03)
1108 var->green.length = 5;
1109 if (var->green.length == 5) {
1110 /* 0rrrrrgg gggbbbbb */
1111 var->red.offset = 10;
1112 var->green.offset = 5;
1113 var->blue.offset = 0;
1114 var->red.length = 5;
1115 var->green.length = 5;
1116 var->blue.length = 5;
1118 /* rrrrrggg gggbbbbb */
1119 var->red.offset = 11;
1120 var->green.offset = 5;
1121 var->blue.offset = 0;
1122 var->red.length = 5;
1123 var->green.length = 6;
1124 var->blue.length = 5;
1130 var->red.length = var->green.length = var->blue.length = 8;
1131 var->bits_per_pixel = 32;
1132 var->red.offset = 16;
1133 var->green.offset = 8;
1134 var->blue.offset = 0;
1140 "mode %dx%dx%d rejected...color depth not supported.\n",
1141 var->xres, var->yres, var->bits_per_pixel);
1142 NVTRACE("EXIT, returning -EINVAL\n");
1147 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1148 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1152 /* calculate modeline if supported by monitor */
1153 if (!mode_valid && info->monspecs.gtf) {
1154 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1159 mode = fb_find_best_mode(var, &info->modelist);
1161 riva_update_var(var, mode);
1166 if (!mode_valid && info->monspecs.modedb_len)
1169 if (var->xres_virtual < var->xres)
1170 var->xres_virtual = var->xres;
1171 if (var->yres_virtual <= var->yres)
1172 var->yres_virtual = -1;
1173 if (rivafb_do_maximize(info, var, nom, den) < 0)
1176 /* truncate xoffset and yoffset to maximum if too high */
1177 if (var->xoffset > var->xres_virtual - var->xres)
1178 var->xoffset = var->xres_virtual - var->xres - 1;
1180 if (var->yoffset > var->yres_virtual - var->yres)
1181 var->yoffset = var->yres_virtual - var->yres - 1;
1183 var->red.msb_right =
1184 var->green.msb_right =
1185 var->blue.msb_right =
1186 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1191 static int rivafb_set_par(struct fb_info *info)
1193 struct riva_par *par = info->par;
1197 /* vgaHWunlock() + riva unlock (0x7F) */
1198 CRTCout(par, 0x11, 0xFF);
1199 par->riva.LockUnlock(&par->riva, 0);
1200 rc = riva_load_video_mode(info);
1203 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1204 riva_setup_accel(info);
1206 par->cursor_reset = 1;
1207 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1208 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1209 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1211 if (info->flags & FBINFO_HWACCEL_DISABLED)
1212 info->pixmap.scan_align = 1;
1214 info->pixmap.scan_align = 4;
1222 * rivafb_pan_display
1223 * @var: standard kernel fb changeable data
1225 * @info: pointer to fb_info object containing info for current riva board
1228 * Pan (or wrap, depending on the `vmode' field) the display using the
1229 * `xoffset' and `yoffset' fields of the `var' structure.
1230 * If the values don't fit, return -EINVAL.
1232 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1234 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1235 struct fb_info *info)
1237 struct riva_par *par = info->par;
1241 base = var->yoffset * info->fix.line_length + var->xoffset;
1242 par->riva.SetStartAddress(&par->riva, base);
1247 static int rivafb_blank(int blank, struct fb_info *info)
1249 struct riva_par *par= info->par;
1250 unsigned char tmp, vesa;
1252 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1253 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1261 case FB_BLANK_UNBLANK:
1262 case FB_BLANK_NORMAL:
1264 case FB_BLANK_VSYNC_SUSPEND:
1267 case FB_BLANK_HSYNC_SUSPEND:
1270 case FB_BLANK_POWERDOWN:
1275 SEQout(par, 0x01, tmp);
1276 CRTCout(par, 0x1a, vesa);
1285 * @regno: register index
1286 * @red: red component
1287 * @green: green component
1288 * @blue: blue component
1289 * @transp: transparency
1290 * @info: pointer to fb_info object containing info for current riva board
1293 * Set a single color register. The values supplied have a 16 bit
1297 * Return != 0 for invalid regno.
1300 * fbcmap.c:fb_set_cmap()
1302 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1303 unsigned blue, unsigned transp,
1304 struct fb_info *info)
1306 struct riva_par *par = info->par;
1307 RIVA_HW_INST *chip = &par->riva;
1310 if (regno >= riva_get_cmap_len(&info->var))
1313 if (info->var.grayscale) {
1314 /* gray = 0.30*R + 0.59*G + 0.11*B */
1315 red = green = blue =
1316 (red * 77 + green * 151 + blue * 28) >> 8;
1319 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1320 ((u32 *) info->pseudo_palette)[regno] =
1321 (regno << info->var.red.offset) |
1322 (regno << info->var.green.offset) |
1323 (regno << info->var.blue.offset);
1325 * The Riva128 2D engine requires color information in
1326 * TrueColor format even if framebuffer is in DirectColor
1328 if (par->riva.Architecture == NV_ARCH_03) {
1329 switch (info->var.bits_per_pixel) {
1331 par->palette[regno] = ((red & 0xf800) >> 1) |
1332 ((green & 0xf800) >> 6) |
1333 ((blue & 0xf800) >> 11);
1336 par->palette[regno] = ((red & 0xff00) << 8) |
1337 ((green & 0xff00)) |
1338 ((blue & 0xff00) >> 8);
1344 switch (info->var.bits_per_pixel) {
1346 /* "transparent" stuff is completely ignored. */
1347 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1350 if (info->var.green.length == 5) {
1351 for (i = 0; i < 8; i++) {
1352 riva_wclut(chip, regno*8+i, red >> 8,
1353 green >> 8, blue >> 8);
1359 for (i = 0; i < 8; i++) {
1360 riva_wclut(chip, regno*8+i,
1361 red >> 8, green >> 8,
1365 riva_rclut(chip, regno*4, &r, &g, &b);
1366 for (i = 0; i < 4; i++)
1367 riva_wclut(chip, regno*4+i, r,
1372 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1382 * rivafb_fillrect - hardware accelerated color fill function
1383 * @info: pointer to fb_info structure
1384 * @rect: pointer to fb_fillrect structure
1387 * This function fills up a region of framebuffer memory with a solid
1388 * color with a choice of two different ROP's, copy or invert.
1393 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1395 struct riva_par *par = info->par;
1396 u_int color, rop = 0;
1398 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1399 cfb_fillrect(info, rect);
1403 if (info->var.bits_per_pixel == 8)
1404 color = rect->color;
1406 if (par->riva.Architecture != NV_ARCH_03)
1407 color = ((u32 *)info->pseudo_palette)[rect->color];
1409 color = par->palette[rect->color];
1412 switch (rect->rop) {
1422 riva_set_rop_solid(par, rop);
1424 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1425 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1427 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1428 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1429 (rect->dx << 16) | rect->dy);
1431 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1432 (rect->width << 16) | rect->height);
1434 riva_set_rop_solid(par, 0xcc);
1439 * rivafb_copyarea - hardware accelerated blit function
1440 * @info: pointer to fb_info structure
1441 * @region: pointer to fb_copyarea structure
1444 * This copies an area of pixels from one location to another
1449 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1451 struct riva_par *par = info->par;
1453 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1454 cfb_copyarea(info, region);
1458 RIVA_FIFO_FREE(par->riva, Blt, 3);
1459 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1460 (region->sy << 16) | region->sx);
1461 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1462 (region->dy << 16) | region->dx);
1464 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1465 (region->height << 16) | region->width);
1469 static inline void convert_bgcolor_16(u32 *col)
1471 *col = ((*col & 0x0000F800) << 8)
1472 | ((*col & 0x00007E0) << 5)
1473 | ((*col & 0x0000001F) << 3)
1479 * rivafb_imageblit: hardware accelerated color expand function
1480 * @info: pointer to fb_info structure
1481 * @image: pointer to fb_image structure
1484 * If the source is a monochrome bitmap, the function fills up a a region
1485 * of framebuffer memory with pixels whose color is determined by the bit
1486 * setting of the bitmap, 1 - foreground, 0 - background.
1488 * If the source is not a monochrome bitmap, color expansion is not done.
1489 * In this case, it is channeled to a software function.
1494 static void rivafb_imageblit(struct fb_info *info,
1495 const struct fb_image *image)
1497 struct riva_par *par = info->par;
1498 u32 fgx = 0, bgx = 0, width, tmp;
1499 u8 *cdat = (u8 *) image->data;
1500 volatile u32 __iomem *d;
1503 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1504 cfb_imageblit(info, image);
1508 switch (info->var.bits_per_pixel) {
1510 fgx = image->fg_color;
1511 bgx = image->bg_color;
1515 if (par->riva.Architecture != NV_ARCH_03) {
1516 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1517 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1519 fgx = par->palette[image->fg_color];
1520 bgx = par->palette[image->bg_color];
1522 if (info->var.green.length == 6)
1523 convert_bgcolor_16(&bgx);
1527 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1528 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1529 (image->dy << 16) | (image->dx & 0xFFFF));
1530 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1531 (((image->dy + image->height) << 16) |
1532 ((image->dx + image->width) & 0xffff)));
1533 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1534 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1535 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1536 (image->height << 16) | ((image->width + 31) & ~31));
1537 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1538 (image->height << 16) | ((image->width + 31) & ~31));
1539 NV_WR32(&par->riva.Bitmap->PointE, 0,
1540 (image->dy << 16) | (image->dx & 0xFFFF));
1542 d = &par->riva.Bitmap->MonochromeData01E;
1544 width = (image->width + 31)/32;
1545 size = width * image->height;
1546 while (size >= 16) {
1547 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1548 for (i = 0; i < 16; i++) {
1549 tmp = *((u32 *)cdat);
1550 cdat = (u8 *)((u32 *)cdat + 1);
1551 reverse_order(&tmp);
1552 NV_WR32(d, i*4, tmp);
1557 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1558 for (i = 0; i < size; i++) {
1559 tmp = *((u32 *) cdat);
1560 cdat = (u8 *)((u32 *)cdat + 1);
1561 reverse_order(&tmp);
1562 NV_WR32(d, i*4, tmp);
1568 * rivafb_cursor - hardware cursor function
1569 * @info: pointer to info structure
1570 * @cursor: pointer to fbcursor structure
1573 * A cursor function that supports displaying a cursor image via hardware.
1574 * Within the kernel, copy and invert rops are supported. If exported
1575 * to user space, only the copy rop will be supported.
1580 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1582 struct riva_par *par = info->par;
1583 u8 data[MAX_CURS * MAX_CURS/8];
1584 int i, set = cursor->set;
1587 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1590 par->riva.ShowHideCursor(&par->riva, 0);
1592 if (par->cursor_reset) {
1593 set = FB_CUR_SETALL;
1594 par->cursor_reset = 0;
1597 if (set & FB_CUR_SETSIZE)
1598 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1600 if (set & FB_CUR_SETPOS) {
1603 yy = cursor->image.dy - info->var.yoffset;
1604 xx = cursor->image.dx - info->var.xoffset;
1608 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1612 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1613 u32 bg_idx = cursor->image.bg_color;
1614 u32 fg_idx = cursor->image.fg_color;
1615 u32 s_pitch = (cursor->image.width+7) >> 3;
1616 u32 d_pitch = MAX_CURS/8;
1617 u8 *dat = (u8 *) cursor->image.data;
1618 u8 *msk = (u8 *) cursor->mask;
1621 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1624 switch (cursor->rop) {
1626 for (i = 0; i < s_pitch * cursor->image.height; i++)
1627 src[i] = dat[i] ^ msk[i];
1631 for (i = 0; i < s_pitch * cursor->image.height; i++)
1632 src[i] = dat[i] & msk[i];
1636 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1637 cursor->image.height);
1639 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1640 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1641 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1644 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1645 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1646 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1649 par->riva.LockUnlock(&par->riva, 0);
1651 rivafb_load_cursor_image(par, data, bg, fg,
1652 cursor->image.width,
1653 cursor->image.height);
1659 par->riva.ShowHideCursor(&par->riva, 1);
1664 static int rivafb_sync(struct fb_info *info)
1666 struct riva_par *par = info->par;
1672 /* ------------------------------------------------------------------------- *
1674 * initialization helper functions
1676 * ------------------------------------------------------------------------- */
1678 /* kernel interface */
1679 static struct fb_ops riva_fb_ops = {
1680 .owner = THIS_MODULE,
1681 .fb_open = rivafb_open,
1682 .fb_release = rivafb_release,
1683 .fb_check_var = rivafb_check_var,
1684 .fb_set_par = rivafb_set_par,
1685 .fb_setcolreg = rivafb_setcolreg,
1686 .fb_pan_display = rivafb_pan_display,
1687 .fb_blank = rivafb_blank,
1688 .fb_fillrect = rivafb_fillrect,
1689 .fb_copyarea = rivafb_copyarea,
1690 .fb_imageblit = rivafb_imageblit,
1691 .fb_cursor = rivafb_cursor,
1692 .fb_sync = rivafb_sync,
1695 static int riva_set_fbinfo(struct fb_info *info)
1697 unsigned int cmap_len;
1698 struct riva_par *par = info->par;
1701 info->flags = FBINFO_DEFAULT
1702 | FBINFO_HWACCEL_XPAN
1703 | FBINFO_HWACCEL_YPAN
1704 | FBINFO_HWACCEL_COPYAREA
1705 | FBINFO_HWACCEL_FILLRECT
1706 | FBINFO_HWACCEL_IMAGEBLIT;
1708 /* Accel seems to not work properly on NV30 yet...*/
1709 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1710 printk(KERN_DEBUG PFX "disabling acceleration\n");
1711 info->flags |= FBINFO_HWACCEL_DISABLED;
1714 info->var = rivafb_default_var;
1715 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1716 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1718 info->pseudo_palette = par->pseudo_palette;
1720 cmap_len = riva_get_cmap_len(&info->var);
1721 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1723 info->pixmap.size = 8 * 1024;
1724 info->pixmap.buf_align = 4;
1725 info->pixmap.access_align = 32;
1726 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1727 info->var.yres_virtual = -1;
1729 return (rivafb_check_var(&info->var, info));
1732 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1734 struct riva_par *par = info->par;
1735 struct device_node *dp;
1736 const unsigned char *pedid = NULL;
1737 const unsigned char *disptype = NULL;
1738 static char *propnames[] = {
1739 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1743 dp = pci_device_to_OF_node(pd);
1744 for (; dp != NULL; dp = dp->child) {
1745 disptype = of_get_property(dp, "display-type", NULL);
1746 if (disptype == NULL)
1748 if (strncmp(disptype, "LCD", 3) != 0)
1750 for (i = 0; propnames[i] != NULL; ++i) {
1751 pedid = of_get_property(dp, propnames[i], NULL);
1752 if (pedid != NULL) {
1753 par->EDID = (unsigned char *)pedid;
1754 NVTRACE("LCD found.\n");
1763 #if defined(CONFIG_FB_RIVA_I2C)
1764 static int riva_get_EDID_i2c(struct fb_info *info)
1766 struct riva_par *par = info->par;
1767 struct fb_var_screeninfo var;
1771 riva_create_i2c_busses(par);
1772 for (i = 0; i < 3; i++) {
1773 if (!par->chan[i].par)
1775 riva_probe_i2c_connector(par, i, &par->EDID);
1776 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1777 printk(PFX "Found EDID Block from BUS %i\n", i);
1783 return (par->EDID) ? 1 : 0;
1785 #endif /* CONFIG_FB_RIVA_I2C */
1787 static void riva_update_default_var(struct fb_var_screeninfo *var,
1788 struct fb_info *info)
1790 struct fb_monspecs *specs = &info->monspecs;
1791 struct fb_videomode modedb;
1794 /* respect mode options */
1796 fb_find_mode(var, info, mode_option,
1797 specs->modedb, specs->modedb_len,
1799 } else if (specs->modedb != NULL) {
1800 /* get first mode in database as fallback */
1801 modedb = specs->modedb[0];
1802 /* get preferred timing */
1803 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1806 for (i = 0; i < specs->modedb_len; i++) {
1807 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1808 modedb = specs->modedb[i];
1813 var->bits_per_pixel = 8;
1814 riva_update_var(var, &modedb);
1820 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1823 if (riva_get_EDID_OF(info, pdev)) {
1827 if (IS_ENABLED(CONFIG_OF))
1828 printk(PFX "could not retrieve EDID from OF\n");
1829 #if defined(CONFIG_FB_RIVA_I2C)
1830 if (!riva_get_EDID_i2c(info))
1831 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1837 static void riva_get_edidinfo(struct fb_info *info)
1839 struct fb_var_screeninfo *var = &rivafb_default_var;
1840 struct riva_par *par = info->par;
1842 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1843 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1845 riva_update_default_var(var, info);
1847 /* if user specified flatpanel, we respect that */
1848 if (info->monspecs.input & FB_DISP_DDI)
1852 /* ------------------------------------------------------------------------- *
1856 * ------------------------------------------------------------------------- */
1858 static u32 riva_get_arch(struct pci_dev *pd)
1862 switch (pd->device & 0x0ff0) {
1863 case 0x0100: /* GeForce 256 */
1864 case 0x0110: /* GeForce2 MX */
1865 case 0x0150: /* GeForce2 */
1866 case 0x0170: /* GeForce4 MX */
1867 case 0x0180: /* GeForce4 MX (8x AGP) */
1868 case 0x01A0: /* nForce */
1869 case 0x01F0: /* nForce2 */
1872 case 0x0200: /* GeForce3 */
1873 case 0x0250: /* GeForce4 Ti */
1874 case 0x0280: /* GeForce4 Ti (8x AGP) */
1877 case 0x0300: /* GeForceFX 5800 */
1878 case 0x0310: /* GeForceFX 5600 */
1879 case 0x0320: /* GeForceFX 5200 */
1880 case 0x0330: /* GeForceFX 5900 */
1881 case 0x0340: /* GeForceFX 5700 */
1884 case 0x0020: /* TNT, TNT2 */
1887 case 0x0010: /* Riva128 */
1890 default: /* unknown architecture */
1896 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1898 struct riva_par *default_par;
1899 struct fb_info *info;
1905 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1907 printk (KERN_ERR PFX "could not allocate memory\n");
1911 default_par = info->par;
1912 default_par->pdev = pd;
1914 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1915 if (info->pixmap.addr == NULL) {
1917 goto err_framebuffer_release;
1920 ret = pci_enable_device(pd);
1922 printk(KERN_ERR PFX "cannot enable PCI device\n");
1923 goto err_free_pixmap;
1926 ret = pci_request_regions(pd, "rivafb");
1928 printk(KERN_ERR PFX "cannot request PCI regions\n");
1929 goto err_disable_device;
1932 mutex_init(&default_par->open_lock);
1933 default_par->riva.Architecture = riva_get_arch(pd);
1935 default_par->Chipset = (pd->vendor << 16) | pd->device;
1936 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1938 if(default_par->riva.Architecture == 0) {
1939 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1941 goto err_release_region;
1943 if(default_par->riva.Architecture == NV_ARCH_10 ||
1944 default_par->riva.Architecture == NV_ARCH_20 ||
1945 default_par->riva.Architecture == NV_ARCH_30) {
1946 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1948 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1951 default_par->FlatPanel = flatpanel;
1953 printk(KERN_INFO PFX "flatpanel support enabled\n");
1954 default_par->forceCRTC = forceCRTC;
1956 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1957 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1960 /* enable IO and mem if not already done */
1963 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1964 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1965 pci_write_config_word(pd, PCI_COMMAND, cmd);
1968 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1969 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1971 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1972 rivafb_fix.mmio_len);
1973 if (!default_par->ctrl_base) {
1974 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1976 goto err_release_region;
1979 switch (default_par->riva.Architecture) {
1981 /* Riva128's PRAMIN is in the "framebuffer" space
1982 * Since these cards were never made with more than 8 megabytes
1983 * we can safely allocate this separately.
1985 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1986 if (!default_par->riva.PRAMIN) {
1987 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1989 goto err_iounmap_ctrl_base;
1996 default_par->riva.PCRTC0 =
1997 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1998 default_par->riva.PRAMIN =
1999 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2002 riva_common_setup(default_par);
2004 if (default_par->riva.Architecture == NV_ARCH_03) {
2005 default_par->riva.PCRTC = default_par->riva.PCRTC0
2006 = default_par->riva.PGRAPH;
2009 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2010 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2011 info->screen_base = ioremap_wc(rivafb_fix.smem_start,
2012 rivafb_fix.smem_len);
2013 if (!info->screen_base) {
2014 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2016 goto err_iounmap_pramin;
2020 default_par->wc_cookie =
2021 arch_phys_wc_add(rivafb_fix.smem_start,
2022 rivafb_fix.smem_len);
2024 info->fbops = &riva_fb_ops;
2025 info->fix = rivafb_fix;
2026 riva_get_EDID(info, pd);
2027 riva_get_edidinfo(info);
2029 ret=riva_set_fbinfo(info);
2031 printk(KERN_ERR PFX "error setting initial video mode\n");
2032 goto err_iounmap_screen_base;
2035 fb_destroy_modedb(info->monspecs.modedb);
2036 info->monspecs.modedb = NULL;
2038 pci_set_drvdata(pd, info);
2041 riva_bl_init(info->par);
2043 ret = register_framebuffer(info);
2046 "error registering riva framebuffer\n");
2047 goto err_iounmap_screen_base;
2050 printk(KERN_INFO PFX
2051 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2054 info->fix.smem_len / (1024 * 1024),
2055 info->fix.smem_start);
2060 err_iounmap_screen_base:
2061 #ifdef CONFIG_FB_RIVA_I2C
2062 riva_delete_i2c_busses(info->par);
2064 iounmap(info->screen_base);
2066 if (default_par->riva.Architecture == NV_ARCH_03)
2067 iounmap(default_par->riva.PRAMIN);
2068 err_iounmap_ctrl_base:
2069 iounmap(default_par->ctrl_base);
2071 pci_release_regions(pd);
2074 kfree(info->pixmap.addr);
2075 err_framebuffer_release:
2076 framebuffer_release(info);
2081 static void rivafb_remove(struct pci_dev *pd)
2083 struct fb_info *info = pci_get_drvdata(pd);
2084 struct riva_par *par = info->par;
2088 #ifdef CONFIG_FB_RIVA_I2C
2089 riva_delete_i2c_busses(par);
2093 unregister_framebuffer(info);
2096 arch_phys_wc_del(par->wc_cookie);
2097 iounmap(par->ctrl_base);
2098 iounmap(info->screen_base);
2099 if (par->riva.Architecture == NV_ARCH_03)
2100 iounmap(par->riva.PRAMIN);
2101 pci_release_regions(pd);
2102 kfree(info->pixmap.addr);
2103 framebuffer_release(info);
2107 /* ------------------------------------------------------------------------- *
2111 * ------------------------------------------------------------------------- */
2114 static int rivafb_setup(char *options)
2119 if (!options || !*options)
2122 while ((this_opt = strsep(&options, ",")) != NULL) {
2123 if (!strncmp(this_opt, "forceCRTC", 9)) {
2127 if (!*p || !*(++p)) continue;
2128 forceCRTC = *p - '0';
2129 if (forceCRTC < 0 || forceCRTC > 1)
2131 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2133 } else if (!strncmp(this_opt, "backlight:", 10)) {
2134 backlight = simple_strtoul(this_opt+10, NULL, 0);
2135 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2137 } else if (!strncmp(this_opt, "strictmode", 10)) {
2139 } else if (!strncmp(this_opt, "noaccel", 7)) {
2142 mode_option = this_opt;
2147 #endif /* !MODULE */
2149 static struct pci_driver rivafb_driver = {
2151 .id_table = rivafb_pci_tbl,
2152 .probe = rivafb_probe,
2153 .remove = rivafb_remove,
2158 /* ------------------------------------------------------------------------- *
2162 * ------------------------------------------------------------------------- */
2164 static int rivafb_init(void)
2167 char *option = NULL;
2169 if (fb_get_options("rivafb", &option))
2171 rivafb_setup(option);
2173 return pci_register_driver(&rivafb_driver);
2177 module_init(rivafb_init);
2179 static void __exit rivafb_exit(void)
2181 pci_unregister_driver(&rivafb_driver);
2184 module_exit(rivafb_exit);
2186 module_param(noaccel, bool, 0);
2187 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2188 module_param(flatpanel, int, 0);
2189 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2190 module_param(forceCRTC, int, 0);
2191 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2192 module_param(nomtrr, bool, 0);
2193 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2194 module_param(strictmode, bool, 0);
2195 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2197 MODULE_AUTHOR("Ani Joshi, maintainer");
2198 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2199 MODULE_LICENSE("GPL");