2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
41 #include <video/permedia2.h>
42 #include <video/cvisionppc.h>
44 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
45 #error "The endianness of the target host has not been defined."
48 #if !defined(CONFIG_PCI)
49 #error "Only generic PCI cards supported."
52 #undef PM2FB_MASTER_DEBUG
53 #ifdef PM2FB_MASTER_DEBUG
54 #define DPRINTK(a, b...) \
55 printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b)
57 #define DPRINTK(a, b...)
60 #define PM2_PIXMAP_SIZE (1600 * 4)
65 static int hwcursor = 1;
66 static char *mode_option;
69 * The XFree GLINT driver will (I think to implement hardware cursor
70 * support on TVP4010 and similar where there is no RAMDAC - see
71 * comment in set_video) always request +ve sync regardless of what
72 * the mode requires. This screws me because I have a Sun
73 * fixed-frequency monitor which absolutely has to have -ve sync. So
74 * these flags allow the user to specify that requests for +ve sync
75 * should be silently turned in -ve sync.
83 * The hardware state of the graphics card that isn't part of the
88 pm2type_t type; /* Board type */
89 unsigned char __iomem *v_regs;/* virtual address of p_regs */
90 u32 memclock; /* memclock */
91 u32 video; /* video flags before blanking */
92 u32 mem_config; /* MemConfig reg at probe */
93 u32 mem_control; /* MemControl reg at probe */
94 u32 boot_address; /* BootAddress reg at probe */
100 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
101 * if we don't use modedb.
103 static struct fb_fix_screeninfo pm2fb_fix = {
105 .type = FB_TYPE_PACKED_PIXELS,
106 .visual = FB_VISUAL_PSEUDOCOLOR,
110 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
114 * Default video mode. In case the modedb doesn't work.
116 static const struct fb_var_screeninfo pm2fb_var = {
117 /* "640x480, 8 bpp @ 60 Hz */
126 .activate = FB_ACTIVATE_NOW,
137 .vmode = FB_VMODE_NONINTERLACED
144 static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
146 return fb_readl(p->v_regs + off);
149 static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
151 fb_writel(v, p->v_regs + off);
154 static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
156 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
158 return pm2_RD(p, PM2R_RD_INDEXED_DATA);
161 static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
163 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
165 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
168 static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
170 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
172 pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
176 static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
178 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
180 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
184 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
185 #define WAIT_FIFO(p, a)
187 static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
189 while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)
195 * partial products for the supported horizontal resolutions.
197 #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
198 static const struct {
202 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
203 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
204 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
205 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
206 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
207 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
208 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
209 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
210 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
211 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
212 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
213 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
214 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
215 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
216 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
217 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
220 static u32 partprod(u32 xres)
224 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
226 if (pp_table[i].width == 0)
227 DPRINTK("invalid width %u\n", xres);
228 return pp_table[i].pp;
231 static u32 to3264(u32 timing, int bpp, int is64)
248 static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
259 for (n = 2; n < 15; n++) {
260 for (m = 2; m; m++) {
261 f = PM2_REFERENCE_CLOCK * m / n;
262 if (f >= 150000 && f <= 300000) {
263 for (p = 0; p < 5; p++, f >>= 1) {
264 curr = (clk > f) ? clk - f : f - clk;
277 static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
287 for (m = 1; m < 128; m++) {
288 for (n = 2 * m + 1; n; n++) {
289 for (p = 0; p < 2; p++) {
290 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
291 if (clk > f - delta && clk < f + delta) {
292 delta = (clk > f) ? clk - f : f - clk;
302 static void clear_palette(struct pm2fb_par *p)
307 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
311 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
312 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
313 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
317 static void reset_card(struct pm2fb_par *p)
319 if (p->type == PM2_TYPE_PERMEDIA2V)
320 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
321 pm2_WR(p, PM2R_RESET_STATUS, 0);
323 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
326 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
327 DPRINTK("FIFO disconnect enabled\n");
328 pm2_WR(p, PM2R_FIFO_DISCON, 1);
332 /* Restore stashed memory config information from probe */
334 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
335 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
337 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
340 static void reset_config(struct pm2fb_par *p)
343 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
344 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
345 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
346 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
347 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
348 pm2_WR(p, PM2R_APERTURE_ONE, 0);
349 pm2_WR(p, PM2R_APERTURE_TWO, 0);
350 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
351 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
352 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
353 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
354 pm2_WR(p, PM2R_LB_READ_MODE, 0);
355 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
356 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
357 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
358 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
359 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
360 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
361 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
362 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
363 pm2_WR(p, PM2R_DITHER_MODE, 0);
364 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
365 pm2_WR(p, PM2R_DEPTH_MODE, 0);
366 pm2_WR(p, PM2R_STENCIL_MODE, 0);
367 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
368 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
369 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
370 pm2_WR(p, PM2R_YUV_MODE, 0);
371 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
372 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
373 pm2_WR(p, PM2R_FOG_MODE, 0);
374 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
375 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
376 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
377 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
378 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
379 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
381 case PM2_TYPE_PERMEDIA2:
382 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
383 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
384 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
385 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
386 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
387 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
388 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
389 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
391 case PM2_TYPE_PERMEDIA2V:
392 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
397 static void set_aperture(struct pm2fb_par *p, u32 depth)
400 * The hardware is little-endian. When used in big-endian
401 * hosts, the on-chip aperture settings are used where
402 * possible to translate from host to card byte order.
405 #ifdef __LITTLE_ENDIAN
406 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
409 case 24: /* RGB->BGR */
411 * We can't use the aperture to translate host to
412 * card byte order here, so we switch to BGR mode
413 * in pm2fb_set_par().
416 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
418 case 16: /* HL->LH */
419 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
421 case 32: /* RGBA->ABGR */
422 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
427 /* We don't use aperture two, so this may be superflous */
428 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
431 static void set_color(struct pm2fb_par *p, unsigned char regno,
432 unsigned char r, unsigned char g, unsigned char b)
435 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
437 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
439 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
441 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
444 static void set_memclock(struct pm2fb_par *par, u32 clk)
447 unsigned char m, n, p;
450 case PM2_TYPE_PERMEDIA2V:
451 pm2v_mnp(clk/2, &m, &n, &p);
453 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
454 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
455 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
456 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
457 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
458 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
460 for (i = 256; i; i--)
461 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
463 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
465 case PM2_TYPE_PERMEDIA2:
466 pm2_mnp(clk, &m, &n, &p);
468 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
469 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
470 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
471 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
472 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
474 for (i = 256; i; i--)
475 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
481 static void set_pixclock(struct pm2fb_par *par, u32 clk)
484 unsigned char m, n, p;
487 case PM2_TYPE_PERMEDIA2:
488 pm2_mnp(clk, &m, &n, &p);
490 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
491 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
492 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
493 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
494 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
496 for (i = 256; i; i--)
497 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
500 case PM2_TYPE_PERMEDIA2V:
501 pm2v_mnp(clk/2, &m, &n, &p);
503 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
504 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
505 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
506 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
507 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
512 static void set_video(struct pm2fb_par *p, u32 video)
517 DPRINTK("video = 0x%x\n", video);
520 * The hardware cursor needs +vsync to recognise vert retrace.
521 * We may not be using the hardware cursor, but the X Glint
522 * driver may well. So always set +hsync/+vsync and then set
523 * the RAMDAC to invert the sync if necessary.
525 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
526 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
529 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
532 case PM2_TYPE_PERMEDIA2:
533 tmp = PM2F_RD_PALETTE_WIDTH_8;
534 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
535 tmp |= 4; /* invert hsync */
536 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
537 tmp |= 8; /* invert vsync */
538 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
540 case PM2_TYPE_PERMEDIA2V:
542 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
543 tmp |= 1; /* invert hsync */
544 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
545 tmp |= 4; /* invert vsync */
546 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
552 * pm2fb_check_var - Optional function. Validates a var passed in.
553 * @var: frame buffer variable screen structure
554 * @info: frame buffer structure that represents a single frame buffer
556 * Checks to see if the hardware supports the state requested by
559 * Returns negative errno on error, or zero on success.
561 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
565 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
566 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
567 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
571 if (var->xres != var->xres_virtual) {
572 DPRINTK("virtual x resolution != "
573 "physical x resolution not supported\n");
577 if (var->yres > var->yres_virtual) {
578 DPRINTK("virtual y resolution < "
579 "physical y resolution not possible\n");
583 /* permedia cannot blit over 2048 */
584 if (var->yres_virtual > 2047) {
585 var->yres_virtual = 2047;
589 DPRINTK("xoffset not supported\n");
593 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
594 DPRINTK("interlace not supported\n");
598 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
599 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
601 if (var->xres < 320 || var->xres > 1600) {
602 DPRINTK("width not supported: %u\n", var->xres);
606 if (var->yres < 200 || var->yres > 1200) {
607 DPRINTK("height not supported: %u\n", var->yres);
611 if (lpitch * var->yres_virtual > info->fix.smem_len) {
612 DPRINTK("no memory for screen (%ux%ux%u)\n",
613 var->xres, var->yres_virtual, var->bits_per_pixel);
617 if (!var->pixclock) {
618 DPRINTK("pixclock is zero\n");
622 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
623 DPRINTK("pixclock too high (%ldKHz)\n",
624 PICOS2KHZ(var->pixclock));
628 var->transp.offset = 0;
629 var->transp.length = 0;
630 switch (var->bits_per_pixel) {
633 var->green.length = 8;
634 var->blue.length = 8;
637 var->red.offset = 11;
639 var->green.offset = 5;
640 var->green.length = 6;
641 var->blue.offset = 0;
642 var->blue.length = 5;
645 var->transp.offset = 24;
646 var->transp.length = 8;
647 var->red.offset = 16;
648 var->green.offset = 8;
649 var->blue.offset = 0;
651 var->green.length = 8;
652 var->blue.length = 8;
657 var->blue.offset = 16;
659 var->red.offset = 16;
660 var->blue.offset = 0;
662 var->green.offset = 8;
664 var->green.length = 8;
665 var->blue.length = 8;
671 var->accel_flags = 0; /* Can't mmap if this is on */
673 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
674 var->xres, var->yres, var->bits_per_pixel);
679 * pm2fb_set_par - Alters the hardware state.
680 * @info: frame buffer structure that represents a single frame buffer
682 * Using the fb_var_screeninfo in fb_info we set the resolution of the
683 * this particular framebuffer.
685 static int pm2fb_set_par(struct fb_info *info)
687 struct pm2fb_par *par = info->par;
689 u32 width = (info->var.xres_virtual + 7) & ~7;
690 u32 height = info->var.yres_virtual;
691 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
692 u32 hsstart, hsend, hbend, htotal;
693 u32 vsstart, vsend, vbend, vtotal;
697 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
701 u32 misc = 1; /* 8-bit DAC */
702 u32 xres = (info->var.xres + 31) & ~31;
709 set_memclock(par, par->memclock);
711 depth = (depth > 32) ? 32 : depth;
712 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
714 pixclock = PICOS2KHZ(info->var.pixclock);
715 if (pixclock > PM2_MAX_PIXCLOCK) {
716 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
720 hsstart = to3264(info->var.right_margin, depth, data64);
721 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
722 hbend = hsend + to3264(info->var.left_margin, depth, data64);
723 htotal = to3264(xres, depth, data64) + hbend - 1;
724 vsstart = (info->var.lower_margin)
725 ? info->var.lower_margin - 1
727 vsend = info->var.lower_margin + info->var.vsync_len - 1;
728 vbend = info->var.lower_margin + info->var.vsync_len +
729 info->var.upper_margin;
730 vtotal = info->var.yres + vbend - 1;
731 stride = to3264(width, depth, 1);
732 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
734 video |= PM2F_DATA_64_ENABLE;
736 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
738 DPRINTK("ignoring +hsync, using -hsync.\n");
739 video |= PM2F_HSYNC_ACT_LOW;
741 video |= PM2F_HSYNC_ACT_HIGH;
743 video |= PM2F_HSYNC_ACT_LOW;
745 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
747 DPRINTK("ignoring +vsync, using -vsync.\n");
748 video |= PM2F_VSYNC_ACT_LOW;
750 video |= PM2F_VSYNC_ACT_HIGH;
752 video |= PM2F_VSYNC_ACT_LOW;
754 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
755 DPRINTK("interlaced not supported\n");
758 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
759 video |= PM2F_LINE_DOUBLE;
760 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
761 video |= PM2F_VIDEO_ENABLE;
765 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
766 info->fix.line_length = info->var.xres * depth / 8;
767 info->cmap.len = 256;
770 * Settings calculated. Now write them out.
772 if (par->type == PM2_TYPE_PERMEDIA2V) {
774 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
777 set_aperture(par, depth);
783 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
787 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
788 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
789 txtmap = PM2F_TEXTEL_SIZE_16;
795 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
796 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
797 txtmap = PM2F_TEXTEL_SIZE_32;
803 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
804 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
805 txtmap = PM2F_TEXTEL_SIZE_24;
811 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
812 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
813 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
814 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
815 pm2_WR(par, PM2R_H_TOTAL, htotal);
816 pm2_WR(par, PM2R_HS_START, hsstart);
817 pm2_WR(par, PM2R_HS_END, hsend);
818 pm2_WR(par, PM2R_HG_END, hbend);
819 pm2_WR(par, PM2R_HB_END, hbend);
820 pm2_WR(par, PM2R_V_TOTAL, vtotal);
821 pm2_WR(par, PM2R_VS_START, vsstart);
822 pm2_WR(par, PM2R_VS_END, vsend);
823 pm2_WR(par, PM2R_VB_END, vbend);
824 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
826 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
827 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
828 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
830 pm2_WR(par, PM2R_SCREEN_BASE, base);
832 set_video(par, video);
835 case PM2_TYPE_PERMEDIA2:
836 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
837 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
838 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
840 case PM2_TYPE_PERMEDIA2V:
841 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
842 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
843 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
844 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
845 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
848 set_pixclock(par, pixclock);
849 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
850 info->var.xres, info->var.yres, info->var.bits_per_pixel);
855 * pm2fb_setcolreg - Sets a color register.
856 * @regno: boolean, 0 copy local, 1 get_user() function
857 * @red: frame buffer colormap structure
858 * @green: The green value which can be up to 16 bits wide
859 * @blue: The blue value which can be up to 16 bits wide.
860 * @transp: If supported the alpha value which can be up to 16 bits wide.
861 * @info: frame buffer info structure
863 * Set a single color register. The values supplied have a 16 bit
864 * magnitude which needs to be scaled in this function for the hardware.
865 * Pretty much a direct lift from tdfxfb.c.
867 * Returns negative errno on error, or zero on success.
869 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
870 unsigned blue, unsigned transp,
871 struct fb_info *info)
873 struct pm2fb_par *par = info->par;
875 if (regno >= info->cmap.len) /* no. of hw registers */
878 * Program hardware... do anything you want with transp
881 /* grayscale works only partially under directcolor */
882 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
883 if (info->var.grayscale)
884 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
887 * var->{color}.offset contains start of bitfield
888 * var->{color}.length contains length of bitfield
889 * {hardwarespecific} contains width of DAC
890 * cmap[X] is programmed to
891 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
892 * RAMDAC[X] is programmed to (red, green, blue)
895 * uses offset = 0 && length = DAC register width.
896 * var->{color}.offset is 0
897 * var->{color}.length contains width of DAC
899 * DAC[X] is programmed to (red, green, blue)
901 * does not use RAMDAC (usually has 3 of them).
902 * var->{color}.offset contains start of bitfield
903 * var->{color}.length contains length of bitfield
904 * cmap is programmed to
905 * (red << red.offset) | (green << green.offset) |
906 * (blue << blue.offset) | (transp << transp.offset)
907 * RAMDAC does not exist
909 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
910 switch (info->fix.visual) {
911 case FB_VISUAL_TRUECOLOR:
912 case FB_VISUAL_PSEUDOCOLOR:
913 red = CNVT_TOHW(red, info->var.red.length);
914 green = CNVT_TOHW(green, info->var.green.length);
915 blue = CNVT_TOHW(blue, info->var.blue.length);
916 transp = CNVT_TOHW(transp, info->var.transp.length);
918 case FB_VISUAL_DIRECTCOLOR:
919 /* example here assumes 8 bit DAC. Might be different
920 * for your hardware */
921 red = CNVT_TOHW(red, 8);
922 green = CNVT_TOHW(green, 8);
923 blue = CNVT_TOHW(blue, 8);
924 /* hey, there is bug in transp handling... */
925 transp = CNVT_TOHW(transp, 8);
929 /* Truecolor has hardware independent palette */
930 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
936 v = (red << info->var.red.offset) |
937 (green << info->var.green.offset) |
938 (blue << info->var.blue.offset) |
939 (transp << info->var.transp.offset);
941 switch (info->var.bits_per_pixel) {
947 par->palette[regno] = v;
951 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
952 set_color(par, regno, red, green, blue);
958 * pm2fb_pan_display - Pans the display.
959 * @var: frame buffer variable screen structure
960 * @info: frame buffer structure that represents a single frame buffer
962 * Pan (or wrap, depending on the `vmode' field) the display using the
963 * `xoffset' and `yoffset' fields of the `var' structure.
964 * If the values don't fit, return -EINVAL.
966 * Returns negative errno on error, or zero on success.
969 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
970 struct fb_info *info)
972 struct pm2fb_par *p = info->par;
974 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
975 u32 xres = (info->var.xres + 31) & ~31;
977 depth = (depth > 32) ? 32 : depth;
978 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
980 pm2_WR(p, PM2R_SCREEN_BASE, base);
985 * pm2fb_blank - Blanks the display.
986 * @blank_mode: the blank mode we want.
987 * @info: frame buffer structure that represents a single frame buffer
989 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
990 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
991 * video mode which doesn't support it. Implements VESA suspend
992 * and powerdown modes on hardware that supports disabling hsync/vsync:
993 * blank_mode == 2: suspend vsync
994 * blank_mode == 3: suspend hsync
995 * blank_mode == 4: powerdown
997 * Returns negative errno on error, or zero on success.
1000 static int pm2fb_blank(int blank_mode, struct fb_info *info)
1002 struct pm2fb_par *par = info->par;
1003 u32 video = par->video;
1005 DPRINTK("blank_mode %d\n", blank_mode);
1007 switch (blank_mode) {
1008 case FB_BLANK_UNBLANK:
1010 video |= PM2F_VIDEO_ENABLE;
1012 case FB_BLANK_NORMAL:
1014 video &= ~PM2F_VIDEO_ENABLE;
1016 case FB_BLANK_VSYNC_SUSPEND:
1018 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
1020 case FB_BLANK_HSYNC_SUSPEND:
1022 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1024 case FB_BLANK_POWERDOWN:
1025 /* HSync: Off, VSync: Off */
1026 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1029 set_video(par, video);
1033 static int pm2fb_sync(struct fb_info *info)
1035 struct pm2fb_par *par = info->par;
1038 pm2_WR(par, PM2R_SYNC, 0);
1041 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1043 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1048 static void pm2fb_fillrect(struct fb_info *info,
1049 const struct fb_fillrect *region)
1051 struct pm2fb_par *par = info->par;
1052 struct fb_fillrect modded;
1054 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1055 ((u32 *)info->pseudo_palette)[region->color] : region->color;
1057 if (info->state != FBINFO_STATE_RUNNING)
1059 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1060 region->rop != ROP_COPY ) {
1061 cfb_fillrect(info, region);
1065 vxres = info->var.xres_virtual;
1066 vyres = info->var.yres_virtual;
1068 memcpy(&modded, region, sizeof(struct fb_fillrect));
1070 if (!modded.width || !modded.height ||
1071 modded.dx >= vxres || modded.dy >= vyres)
1074 if (modded.dx + modded.width > vxres)
1075 modded.width = vxres - modded.dx;
1076 if (modded.dy + modded.height > vyres)
1077 modded.height = vyres - modded.dy;
1079 if (info->var.bits_per_pixel == 8)
1080 color |= color << 8;
1081 if (info->var.bits_per_pixel <= 16)
1082 color |= color << 16;
1085 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
1086 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1087 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1088 if (info->var.bits_per_pixel != 24) {
1090 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1092 pm2_WR(par, PM2R_RENDER,
1093 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
1096 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1097 pm2_WR(par, PM2R_CONSTANT_COLOR, color);
1099 pm2_WR(par, PM2R_RENDER,
1100 PM2F_RENDER_RECTANGLE |
1101 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1102 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1106 static void pm2fb_copyarea(struct fb_info *info,
1107 const struct fb_copyarea *area)
1109 struct pm2fb_par *par = info->par;
1110 struct fb_copyarea modded;
1113 if (info->state != FBINFO_STATE_RUNNING)
1115 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1116 cfb_copyarea(info, area);
1120 memcpy(&modded, area, sizeof(struct fb_copyarea));
1122 vxres = info->var.xres_virtual;
1123 vyres = info->var.yres_virtual;
1125 if (!modded.width || !modded.height ||
1126 modded.sx >= vxres || modded.sy >= vyres ||
1127 modded.dx >= vxres || modded.dy >= vyres)
1130 if (modded.sx + modded.width > vxres)
1131 modded.width = vxres - modded.sx;
1132 if (modded.dx + modded.width > vxres)
1133 modded.width = vxres - modded.dx;
1134 if (modded.sy + modded.height > vyres)
1135 modded.height = vyres - modded.sy;
1136 if (modded.dy + modded.height > vyres)
1137 modded.height = vyres - modded.dy;
1140 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1141 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1142 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1143 ((modded.sy - modded.dy) & 0xfff) << 16 |
1144 ((modded.sx - modded.dx) & 0xfff));
1145 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1146 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1148 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
1149 (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
1150 (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
1153 static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1155 struct pm2fb_par *par = info->par;
1156 u32 height = image->height;
1158 const u32 *src = (const u32 *)image->data;
1159 u32 xres = (info->var.xres + 31) & ~31;
1160 int raster_mode = 1; /* invert bits */
1162 #ifdef __LITTLE_ENDIAN
1163 raster_mode |= 3 << 7; /* reverse byte order */
1166 if (info->state != FBINFO_STATE_RUNNING)
1168 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1169 cfb_imageblit(info, image);
1172 switch (info->fix.visual) {
1173 case FB_VISUAL_PSEUDOCOLOR:
1174 fgx = image->fg_color;
1175 bgx = image->bg_color;
1177 case FB_VISUAL_TRUECOLOR:
1179 fgx = par->palette[image->fg_color];
1180 bgx = par->palette[image->bg_color];
1183 if (info->var.bits_per_pixel == 8) {
1187 if (info->var.bits_per_pixel <= 16) {
1193 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1194 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1195 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1196 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1197 (((image->dy + image->height) & 0x0fff) << 16) |
1198 ((image->dx + image->width) & 0x0fff));
1199 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1200 /* GXcopy & UNIT_ENABLE */
1201 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
1202 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1203 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1204 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1205 ((image->height & 0x0fff) << 16) |
1206 ((image->width) & 0x0fff));
1207 if (info->var.bits_per_pixel == 24) {
1208 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1210 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1211 pm2_WR(par, PM2R_RENDER,
1212 PM2F_RENDER_RECTANGLE |
1213 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1214 /* BitMapPackEachScanline */
1215 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9));
1216 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1217 pm2_WR(par, PM2R_RENDER,
1218 PM2F_RENDER_RECTANGLE |
1219 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1220 PM2F_RENDER_SYNC_ON_BIT_MASK);
1222 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1224 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1225 pm2_WR(par, PM2R_RENDER,
1226 PM2F_RENDER_RECTANGLE |
1227 PM2F_RENDER_FASTFILL |
1228 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1229 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode);
1230 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1231 pm2_WR(par, PM2R_RENDER,
1232 PM2F_RENDER_RECTANGLE |
1233 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1234 PM2F_RENDER_FASTFILL |
1235 PM2F_RENDER_SYNC_ON_BIT_MASK);
1239 int width = ((image->width + 7) >> 3)
1240 + info->pixmap.scan_align - 1;
1242 WAIT_FIFO(par, width);
1244 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1249 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1250 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1251 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1255 * Hardware cursor support.
1257 static const u8 cursor_bits_lookup[16] = {
1258 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
1259 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
1262 static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1264 struct pm2fb_par *par = info->par;
1265 u8 mode = PM2F_CURSORMODE_TYPE_X;
1266 int x = cursor->image.dx - info->var.xoffset;
1267 int y = cursor->image.dy - info->var.yoffset;
1270 mode |= PM2F_CURSORMODE_CURSOR_ENABLE;
1272 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode);
1274 if (!cursor->enable)
1275 x = 2047; /* push it outside display */
1276 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff);
1277 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf);
1278 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff);
1279 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf);
1282 * If the cursor is not be changed this means either we want the
1283 * current cursor state (if enable is set) or we want to query what
1284 * we can do with the cursor (if enable is not set)
1289 if (cursor->set & FB_CUR_SETHOT) {
1290 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT,
1291 cursor->hot.x & 0x3f);
1292 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT,
1293 cursor->hot.y & 0x3f);
1296 if (cursor->set & FB_CUR_SETCMAP) {
1297 u32 fg_idx = cursor->image.fg_color;
1298 u32 bg_idx = cursor->image.bg_color;
1299 struct fb_cmap cmap = info->cmap;
1301 /* the X11 driver says one should use these color registers */
1302 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8);
1303 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0,
1304 cmap.red[bg_idx] >> 8 );
1305 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1,
1306 cmap.green[bg_idx] >> 8 );
1307 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2,
1308 cmap.blue[bg_idx] >> 8 );
1310 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3,
1311 cmap.red[fg_idx] >> 8 );
1312 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4,
1313 cmap.green[fg_idx] >> 8 );
1314 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5,
1315 cmap.blue[fg_idx] >> 8 );
1316 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1319 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1320 u8 *bitmap = (u8 *)cursor->image.data;
1321 u8 *mask = (u8 *)cursor->mask;
1323 int pos = PM2VI_RD_CURSOR_PATTERN;
1325 for (i = 0; i < cursor->image.height; i++) {
1326 int j = (cursor->image.width + 7) >> 3;
1329 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1331 for (; j > 0; j--) {
1332 u8 data = *bitmap ^ *mask;
1334 if (cursor->rop == ROP_COPY)
1335 data = *mask & *bitmap;
1336 /* Upper 4 bits of bitmap data */
1337 pm2v_RDAC_WR(par, pos++,
1338 cursor_bits_lookup[data >> 4] |
1339 (cursor_bits_lookup[*mask >> 4] << 1));
1340 /* Lower 4 bits of bitmap */
1341 pm2v_RDAC_WR(par, pos++,
1342 cursor_bits_lookup[data & 0xf] |
1343 (cursor_bits_lookup[*mask & 0xf] << 1));
1347 for (; k > 0; k--) {
1348 pm2v_RDAC_WR(par, pos++, 0);
1349 pm2v_RDAC_WR(par, pos++, 0);
1353 while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) {
1354 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1355 pm2v_RDAC_WR(par, pos++, 0);
1358 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1363 static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1365 struct pm2fb_par *par = info->par;
1369 return -EINVAL; /* just to force soft_cursor() call */
1371 /* Too large of a cursor or wrong bpp :-( */
1372 if (cursor->image.width > 64 ||
1373 cursor->image.height > 64 ||
1374 cursor->image.depth > 1)
1377 if (par->type == PM2_TYPE_PERMEDIA2V)
1378 return pm2vfb_cursor(info, cursor);
1384 pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode);
1387 * If the cursor is not be changed this means either we want the
1388 * current cursor state (if enable is set) or we want to query what
1389 * we can do with the cursor (if enable is not set)
1394 if (cursor->set & FB_CUR_SETPOS) {
1395 int x = cursor->image.dx - info->var.xoffset + 63;
1396 int y = cursor->image.dy - info->var.yoffset + 63;
1399 pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff);
1400 pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7);
1401 pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff);
1402 pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7);
1405 if (cursor->set & FB_CUR_SETCMAP) {
1406 u32 fg_idx = cursor->image.fg_color;
1407 u32 bg_idx = cursor->image.bg_color;
1410 pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1);
1411 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1412 info->cmap.red[bg_idx] >> 8);
1413 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1414 info->cmap.green[bg_idx] >> 8);
1415 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1416 info->cmap.blue[bg_idx] >> 8);
1418 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1419 info->cmap.red[fg_idx] >> 8);
1420 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1421 info->cmap.green[fg_idx] >> 8);
1422 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1423 info->cmap.blue[fg_idx] >> 8);
1426 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1427 u8 *bitmap = (u8 *)cursor->image.data;
1428 u8 *mask = (u8 *)cursor->mask;
1432 pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
1434 for (i = 0; i < cursor->image.height; i++) {
1435 int j = (cursor->image.width + 7) >> 3;
1439 for (; j > 0; j--) {
1440 u8 data = *bitmap ^ *mask;
1442 if (cursor->rop == ROP_COPY)
1443 data = *mask & *bitmap;
1445 pm2_WR(par, PM2R_RD_CURSOR_DATA, data);
1450 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1452 for (; i < 64; i++) {
1456 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1459 mask = (u8 *)cursor->mask;
1460 for (i = 0; i < cursor->image.height; i++) {
1461 int j = (cursor->image.width + 7) >> 3;
1465 for (; j > 0; j--) {
1467 pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask);
1471 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1473 for (; i < 64; i++) {
1477 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1483 /* ------------ Hardware Independent Functions ------------ */
1486 * Frame buffer operations
1489 static struct fb_ops pm2fb_ops = {
1490 .owner = THIS_MODULE,
1491 .fb_check_var = pm2fb_check_var,
1492 .fb_set_par = pm2fb_set_par,
1493 .fb_setcolreg = pm2fb_setcolreg,
1494 .fb_blank = pm2fb_blank,
1495 .fb_pan_display = pm2fb_pan_display,
1496 .fb_fillrect = pm2fb_fillrect,
1497 .fb_copyarea = pm2fb_copyarea,
1498 .fb_imageblit = pm2fb_imageblit,
1499 .fb_sync = pm2fb_sync,
1500 .fb_cursor = pm2fb_cursor,
1509 * Device initialisation
1511 * Initialise and allocate resource for PCI device.
1513 * @param pdev PCI device.
1514 * @param id PCI device ID.
1516 static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1518 struct pm2fb_par *default_par;
1519 struct fb_info *info;
1521 int retval = -ENXIO;
1523 err = pci_enable_device(pdev);
1525 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1529 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1532 default_par = info->par;
1534 switch (pdev->device) {
1535 case PCI_DEVICE_ID_TI_TVP4020:
1536 strcpy(pm2fb_fix.id, "TVP4020");
1537 default_par->type = PM2_TYPE_PERMEDIA2;
1539 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1540 strcpy(pm2fb_fix.id, "Permedia2");
1541 default_par->type = PM2_TYPE_PERMEDIA2;
1543 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1544 strcpy(pm2fb_fix.id, "Permedia2v");
1545 default_par->type = PM2_TYPE_PERMEDIA2V;
1549 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1550 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1552 #if defined(__BIG_ENDIAN)
1554 * PM2 has a 64k register file, mapped twice in 128k. Lower
1555 * map is little-endian, upper map is big-endian.
1557 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1558 DPRINTK("Adjusting register base for big-endian.\n");
1560 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1562 /* Registers - request region and map it. */
1563 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1565 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1566 goto err_exit_neither;
1568 default_par->v_regs =
1569 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1570 if (!default_par->v_regs) {
1571 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1573 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1574 goto err_exit_neither;
1577 /* Stash away memory register info for use when we reset the board */
1578 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1579 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1580 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1581 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1582 default_par->mem_control, default_par->boot_address,
1583 default_par->mem_config);
1585 if (default_par->mem_control == 0 &&
1586 default_par->boot_address == 0x31 &&
1587 default_par->mem_config == 0x259fffff) {
1588 default_par->memclock = CVPPC_MEMCLOCK;
1589 default_par->mem_control = 0;
1590 default_par->boot_address = 0x20;
1591 default_par->mem_config = 0xe6002021;
1592 if (pdev->subsystem_vendor == 0x1048 &&
1593 pdev->subsystem_device == 0x0a31) {
1594 DPRINTK("subsystem_vendor: %04x, "
1595 "subsystem_device: %04x\n",
1596 pdev->subsystem_vendor, pdev->subsystem_device);
1597 DPRINTK("We have not been initialized by VGA BIOS and "
1598 "are running on an Elsa Winner 2000 Office\n");
1599 DPRINTK("Initializing card timings manually...\n");
1600 default_par->memclock = 100000;
1602 if (pdev->subsystem_vendor == 0x3d3d &&
1603 pdev->subsystem_device == 0x0100) {
1604 DPRINTK("subsystem_vendor: %04x, "
1605 "subsystem_device: %04x\n",
1606 pdev->subsystem_vendor, pdev->subsystem_device);
1607 DPRINTK("We have not been initialized by VGA BIOS and "
1608 "are running on an 3dlabs reference board\n");
1609 DPRINTK("Initializing card timings manually...\n");
1610 default_par->memclock = 74894;
1614 /* Now work out how big lfb is going to be. */
1615 switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1616 case PM2F_MEM_BANKS_1:
1617 pm2fb_fix.smem_len = 0x200000;
1619 case PM2F_MEM_BANKS_2:
1620 pm2fb_fix.smem_len = 0x400000;
1622 case PM2F_MEM_BANKS_3:
1623 pm2fb_fix.smem_len = 0x600000;
1625 case PM2F_MEM_BANKS_4:
1626 pm2fb_fix.smem_len = 0x800000;
1629 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1631 /* Linear frame buffer - request region and map it. */
1632 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1634 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1638 ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1639 if (!info->screen_base) {
1640 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1641 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1646 default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start,
1647 pm2fb_fix.smem_len);
1649 info->fbops = &pm2fb_ops;
1650 info->fix = pm2fb_fix;
1651 info->pseudo_palette = default_par->palette;
1652 info->flags = FBINFO_DEFAULT |
1653 FBINFO_HWACCEL_YPAN |
1654 FBINFO_HWACCEL_COPYAREA |
1655 FBINFO_HWACCEL_IMAGEBLIT |
1656 FBINFO_HWACCEL_FILLRECT;
1658 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1659 if (!info->pixmap.addr) {
1661 goto err_exit_pixmap;
1663 info->pixmap.size = PM2_PIXMAP_SIZE;
1664 info->pixmap.buf_align = 4;
1665 info->pixmap.scan_align = 4;
1666 info->pixmap.access_align = 32;
1667 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1670 printk(KERN_DEBUG "disabling acceleration\n");
1671 info->flags |= FBINFO_HWACCEL_DISABLED;
1672 info->pixmap.scan_align = 1;
1676 mode_option = "640x480@60";
1678 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1679 if (!err || err == 4)
1680 info->var = pm2fb_var;
1682 retval = fb_alloc_cmap(&info->cmap, 256, 0);
1686 retval = register_framebuffer(info);
1690 fb_info(info, "%s frame buffer device, memory = %dK\n",
1691 info->fix.id, pm2fb_fix.smem_len / 1024);
1696 pci_set_drvdata(pdev, info);
1701 fb_dealloc_cmap(&info->cmap);
1703 kfree(info->pixmap.addr);
1705 iounmap(info->screen_base);
1706 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1708 iounmap(default_par->v_regs);
1709 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1711 framebuffer_release(info);
1718 * Release all device resources.
1720 * @param pdev PCI device to clean up.
1722 static void pm2fb_remove(struct pci_dev *pdev)
1724 struct fb_info *info = pci_get_drvdata(pdev);
1725 struct fb_fix_screeninfo *fix = &info->fix;
1726 struct pm2fb_par *par = info->par;
1728 unregister_framebuffer(info);
1729 arch_phys_wc_del(par->wc_cookie);
1730 iounmap(info->screen_base);
1731 release_mem_region(fix->smem_start, fix->smem_len);
1732 iounmap(par->v_regs);
1733 release_mem_region(fix->mmio_start, fix->mmio_len);
1735 fb_dealloc_cmap(&info->cmap);
1736 kfree(info->pixmap.addr);
1737 framebuffer_release(info);
1740 static const struct pci_device_id pm2fb_id_table[] = {
1741 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1743 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1745 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1750 static struct pci_driver pm2fb_driver = {
1752 .id_table = pm2fb_id_table,
1753 .probe = pm2fb_probe,
1754 .remove = pm2fb_remove,
1757 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1762 * Parse user specified options.
1764 * This is, comma-separated options following `video=pm2fb:'.
1766 static int __init pm2fb_setup(char *options)
1770 if (!options || !*options)
1773 while ((this_opt = strsep(&options, ",")) != NULL) {
1776 if (!strcmp(this_opt, "lowhsync"))
1778 else if (!strcmp(this_opt, "lowvsync"))
1780 else if (!strncmp(this_opt, "hwcursor=", 9))
1781 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1782 else if (!strncmp(this_opt, "nomtrr", 6))
1784 else if (!strncmp(this_opt, "noaccel", 7))
1787 mode_option = this_opt;
1794 static int __init pm2fb_init(void)
1797 char *option = NULL;
1799 if (fb_get_options("pm2fb", &option))
1801 pm2fb_setup(option);
1804 return pci_register_driver(&pm2fb_driver);
1807 module_init(pm2fb_init);
1814 static void __exit pm2fb_exit(void)
1816 pci_unregister_driver(&pm2fb_driver);
1821 module_exit(pm2fb_exit);
1823 module_param(mode_option, charp, 0);
1824 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1825 module_param_named(mode, mode_option, charp, 0);
1826 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1827 module_param(lowhsync, bool, 0);
1828 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1829 module_param(lowvsync, bool, 0);
1830 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1831 module_param(noaccel, bool, 0);
1832 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1833 module_param(hwcursor, int, 0644);
1834 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1835 "(1=enable, 0=disable, default=1)");
1836 module_param(nomtrr, bool, 0);
1837 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1839 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1840 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1841 MODULE_LICENSE("GPL");