2 * Copyright (C) 2014 Texas Instruments Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * You should have received a copy of the GNU General Public License along with
9 * this program. If not, see <http://www.gnu.org/licenses/>.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
20 #include <video/omapfb_dss.h>
23 #include "dss_features.h"
25 struct dss_video_pll {
30 void __iomem *clkctrl_base;
33 #define REG_MOD(reg, val, start, end) \
34 writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
36 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
38 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
41 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
43 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
46 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
48 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
51 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
52 * so we have to use fixed delay here.
57 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
59 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
62 static int dss_video_pll_enable(struct dss_pll *pll)
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
67 r = dss_runtime_get();
71 dss_ctrl_pll_enable(pll->id, true);
73 dss_dpll_enable_scp_clk(vpll);
75 r = dss_pll_wait_reset_done(pll);
79 dss_dpll_power_enable(vpll);
84 dss_dpll_disable_scp_clk(vpll);
85 dss_ctrl_pll_enable(pll->id, false);
91 static void dss_video_pll_disable(struct dss_pll *pll)
93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
95 dss_dpll_power_disable(vpll);
97 dss_dpll_disable_scp_clk(vpll);
99 dss_ctrl_pll_enable(pll->id, false);
104 static const struct dss_pll_ops dss_pll_ops = {
105 .enable = dss_video_pll_enable,
106 .disable = dss_video_pll_disable,
107 .set_config = dss_pll_write_config_type_a,
110 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
111 .n_max = (1 << 8) - 1,
112 .m_max = (1 << 12) - 1,
113 .mX_max = (1 << 5) - 1,
116 .clkdco_max = 1800000000,
131 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
132 struct regulator *regulator)
134 const char * const reg_name[] = { "pll1", "pll2" };
135 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
136 const char * const clkin_name[] = { "video1_clk", "video2_clk" };
138 struct resource *res;
139 struct dss_video_pll *vpll;
140 void __iomem *pll_base, *clkctrl_base;
147 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
150 "missing platform resource data for pll%d\n", id);
151 return ERR_PTR(-ENODEV);
154 pll_base = devm_ioremap_resource(&pdev->dev, res);
155 if (IS_ERR(pll_base)) {
156 dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
157 return ERR_CAST(pll_base);
162 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
166 "missing platform resource data for pll%d\n", id);
167 return ERR_PTR(-ENODEV);
170 clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
171 if (IS_ERR(clkctrl_base)) {
172 dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
173 return ERR_CAST(clkctrl_base);
178 clk = devm_clk_get(&pdev->dev, clkin_name[id]);
180 DSSERR("can't get video pll clkin\n");
181 return ERR_CAST(clk);
184 vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
186 return ERR_PTR(-ENOMEM);
188 vpll->dev = &pdev->dev;
189 vpll->clkctrl_base = clkctrl_base;
193 pll->name = id == 0 ? "video0" : "video1";
194 pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
196 pll->regulator = regulator;
197 pll->base = pll_base;
198 pll->hw = &dss_dra7_video_pll_hw;
199 pll->ops = &dss_pll_ops;
201 r = dss_pll_register(pll);
208 void dss_video_pll_uninit(struct dss_pll *pll)
210 dss_pll_unregister(pll);